| 1 | /* |
| 2 | * QEMU IDE Emulation: PCI VIA82C686B support. |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * Copyright (c) 2006 Openedhand Ltd. |
| 6 | * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include "qemu/osdep.h" |
| 28 | #include "hw/pci/pci.h" |
| 29 | #include "migration/vmstate.h" |
| 30 | #include "qemu/module.h" |
| 31 | #include "qemu/range.h" |
| 32 | #include "system/dma.h" |
| 33 | #include "hw/isa/vt82c686.h" |
| 34 | #include "hw/ide/pci.h" |
| 35 | #include "hw/core/irq.h" |
| 36 | #include "ide-internal.h" |
| 37 | #include "trace.h" |
| 38 | |
| 39 | static uint64_t bmdma_read(void *opaque, hwaddr addr, |
| 40 | unsigned size) |
| 41 | { |
| 42 | BMDMAState *bm = opaque; |
| 43 | uint32_t val; |
| 44 | |
| 45 | if (size != 1) { |
| 46 | return ((uint64_t)1 << (size * 8)) - 1; |
| 47 | } |
| 48 | |
| 49 | switch (addr & 3) { |
| 50 | case 0: |
| 51 | val = bm->cmd; |
| 52 | break; |
| 53 | case 2: |
| 54 | val = bm->status; |
| 55 | break; |
| 56 | default: |
| 57 | val = 0xff; |
| 58 | break; |
| 59 | } |
| 60 | |
| 61 | trace_bmdma_read_via(addr, val); |
| 62 | return val; |
| 63 | } |
| 64 | |
| 65 | static void bmdma_write(void *opaque, hwaddr addr, |
| 66 | uint64_t val, unsigned size) |
| 67 | { |
| 68 | BMDMAState *bm = opaque; |
| 69 | |
| 70 | if (size != 1) { |
| 71 | return; |
| 72 | } |
| 73 | |
| 74 | trace_bmdma_write_via(addr, val); |
| 75 | switch (addr & 3) { |
| 76 | case 0: |
| 77 | bmdma_cmd_writeb(bm, val); |
| 78 | break; |
| 79 | case 2: |
| 80 | bmdma_status_writeb(bm, val); |
| 81 | break; |
| 82 | default:; |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | static const MemoryRegionOps via_bmdma_ops = { |
| 87 | .read = bmdma_read, |
| 88 | .write = bmdma_write, |
| 89 | }; |
| 90 | |
| 91 | static void bmdma_setup_bar(PCIIDEState *d) |
| 92 | { |
| 93 | int i; |
| 94 | |
| 95 | memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); |
| 96 | for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) { |
| 97 | BMDMAState *bm = &d->bmdma[i]; |
| 98 | |
| 99 | memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, |
| 100 | "via-bmdma", 4); |
| 101 | memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); |
| 102 | memory_region_init_io(&bm->addr_ioport, OBJECT(d), |
| 103 | &bmdma_addr_ioport_ops, bm, "bmdma", 4); |
| 104 | memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | static void via_ide_set_irq(void *opaque, int n, int level) |
| 109 | { |
| 110 | PCIIDEState *s = opaque; |
| 111 | PCIDevice *d = PCI_DEVICE(s); |
| 112 | |
| 113 | if (level) { |
| 114 | d->config[0x70 + n * 8] |= 0x80; |
| 115 | } else { |
| 116 | d->config[0x70 + n * 8] &= ~0x80; |
| 117 | } |
| 118 | |
| 119 | qemu_set_irq(s->isa_irq[n], level); |
| 120 | } |
| 121 | |
| 122 | static void via_ide_reset(DeviceState *dev) |
| 123 | { |
| 124 | PCIIDEState *d = PCI_IDE(dev); |
| 125 | PCIDevice *pd = PCI_DEVICE(dev); |
| 126 | uint8_t *pci_conf = pd->config; |
| 127 | int i; |
| 128 | |
| 129 | for (i = 0; i < ARRAY_SIZE(d->bus); i++) { |
| 130 | ide_bus_reset(&d->bus[i], IDE_RESET_HARDWARE); |
| 131 | } |
| 132 | |
| 133 | pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */ |
| 134 | pci_ide_update_mode(d); |
| 135 | |
| 136 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT); |
| 137 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | |
| 138 | PCI_STATUS_DEVSEL_MEDIUM); |
| 139 | |
| 140 | pci_set_byte(pci_conf + PCI_INTERRUPT_LINE, 0xe); |
| 141 | |
| 142 | /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ |
| 143 | pci_set_long(pci_conf + 0x40, 0x0a090600); |
| 144 | /* IDE misc configuration 1/2/3 */ |
| 145 | pci_set_long(pci_conf + 0x44, 0x00c00068); |
| 146 | /* IDE Timing control */ |
| 147 | pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); |
| 148 | /* IDE Address Setup Time */ |
| 149 | pci_set_long(pci_conf + 0x4c, 0x000000ff); |
| 150 | /* UltraDMA Extended Timing Control*/ |
| 151 | pci_set_long(pci_conf + 0x50, 0x07070707); |
| 152 | /* UltraDMA FIFO Control */ |
| 153 | pci_set_long(pci_conf + 0x54, 0x00000004); |
| 154 | /* IDE primary sector size */ |
| 155 | pci_set_long(pci_conf + 0x60, 0x00000200); |
| 156 | /* IDE secondary sector size */ |
| 157 | pci_set_long(pci_conf + 0x68, 0x00000200); |
| 158 | /* PCI PM Block */ |
| 159 | pci_set_long(pci_conf + 0xc0, 0x00020001); |
| 160 | } |
| 161 | |
| 162 | static uint32_t via_ide_cfg_read(PCIDevice *pd, uint32_t addr, int len) |
| 163 | { |
| 164 | uint32_t val = pci_default_read_config(pd, addr, len); |
| 165 | uint8_t mode = pd->config[PCI_CLASS_PROG]; |
| 166 | |
| 167 | if ((mode & 0xf) == 0xa) { |
| 168 | if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 16)) { |
| 169 | /* BARs 0-3 always read back zero in legacy mode */ |
| 170 | for (int i = addr; i < addr + len; i++) { |
| 171 | if (i >= PCI_BASE_ADDRESS_0 && i < PCI_BASE_ADDRESS_0 + 16) { |
| 172 | val &= ~(0xffULL << ((i - addr) << 3)); |
| 173 | } |
| 174 | } |
| 175 | } |
| 176 | if (addr == PCI_BASE_ADDRESS_4 && val == PCI_BASE_ADDRESS_SPACE_IO) { |
| 177 | /* BAR4 default value if unset */ |
| 178 | val = 0xcc00 | PCI_BASE_ADDRESS_SPACE_IO; |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | return val; |
| 183 | } |
| 184 | |
| 185 | static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr, |
| 186 | uint32_t val, int len) |
| 187 | { |
| 188 | PCIIDEState *d = PCI_IDE(pd); |
| 189 | |
| 190 | pci_default_write_config(pd, addr, val, len); |
| 191 | |
| 192 | if (range_covers_byte(addr, len, PCI_CLASS_PROG)) { |
| 193 | pci_ide_update_mode(d); |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | static void via_ide_realize(PCIDevice *dev, Error **errp) |
| 198 | { |
| 199 | PCIIDEState *d = PCI_IDE(dev); |
| 200 | DeviceState *ds = DEVICE(dev); |
| 201 | uint8_t *pci_conf = dev->config; |
| 202 | int i; |
| 203 | |
| 204 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); |
| 205 | dev->wmask[PCI_INTERRUPT_LINE] = 0; |
| 206 | dev->wmask[PCI_CLASS_PROG] = 5; |
| 207 | |
| 208 | memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, |
| 209 | &d->bus[0], "via-ide0-data", 8); |
| 210 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); |
| 211 | |
| 212 | memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, |
| 213 | &d->bus[0], "via-ide0-cmd", 4); |
| 214 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); |
| 215 | |
| 216 | memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, |
| 217 | &d->bus[1], "via-ide1-data", 8); |
| 218 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); |
| 219 | |
| 220 | memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, |
| 221 | &d->bus[1], "via-ide1-cmd", 4); |
| 222 | pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); |
| 223 | |
| 224 | bmdma_setup_bar(d); |
| 225 | pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); |
| 226 | |
| 227 | qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus)); |
| 228 | for (i = 0; i < ARRAY_SIZE(d->bus); i++) { |
| 229 | ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, MAX_IDE_DEVS); |
| 230 | ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i)); |
| 231 | |
| 232 | bmdma_init(&d->bus[i], &d->bmdma[i], d); |
| 233 | ide_bus_register_restart_cb(&d->bus[i]); |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static void via_ide_exitfn(PCIDevice *dev) |
| 238 | { |
| 239 | PCIIDEState *d = PCI_IDE(dev); |
| 240 | unsigned i; |
| 241 | |
| 242 | for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) { |
| 243 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); |
| 244 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | static void via_ide_class_init(ObjectClass *klass, const void *data) |
| 249 | { |
| 250 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 251 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 252 | |
| 253 | device_class_set_legacy_reset(dc, via_ide_reset); |
| 254 | dc->vmsd = &vmstate_ide_pci; |
| 255 | /* Reason: only works as function of VIA southbridge */ |
| 256 | dc->user_creatable = false; |
| 257 | |
| 258 | k->config_read = via_ide_cfg_read; |
| 259 | k->config_write = via_ide_cfg_write; |
| 260 | k->realize = via_ide_realize; |
| 261 | k->exit = via_ide_exitfn; |
| 262 | k->vendor_id = PCI_VENDOR_ID_VIA; |
| 263 | k->device_id = PCI_DEVICE_ID_VIA_IDE; |
| 264 | k->revision = 0x06; |
| 265 | k->class_id = PCI_CLASS_STORAGE_IDE; |
| 266 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
| 267 | } |
| 268 | |
| 269 | static const TypeInfo via_ide_info = { |
| 270 | .name = TYPE_VIA_IDE, |
| 271 | .parent = TYPE_PCI_IDE, |
| 272 | .class_init = via_ide_class_init, |
| 273 | }; |
| 274 | |
| 275 | static void via_ide_register_types(void) |
| 276 | { |
| 277 | type_register_static(&via_ide_info); |
| 278 | } |
| 279 | |
| 280 | type_init(via_ide_register_types) |