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1 /*
2 * Allwinner A10 interrupt controller device emulation
3 *
4 * Copyright (C) 2013 Li Guang
5 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "hw/core/sysbus.h"
20 #include "migration/vmstate.h"
21 #include "hw/intc/allwinner-a10-pic.h"
22 #include "hw/core/irq.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25
26 static void aw_a10_pic_update(AwA10PICState *s)
27 {
28 uint8_t i;
29 int irq = 0, fiq = 0, zeroes;
30
31 s->vector = 0;
32
33 for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
34 irq |= s->irq_pending[i] & ~s->mask[i];
35 fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
36
37 if (!s->vector) {
38 zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]);
39 if (zeroes != 32) {
40 s->vector = (i * 32 + zeroes) * 4;
41 }
42 }
43 }
44
45 qemu_set_irq(s->parent_irq, !!irq);
46 qemu_set_irq(s->parent_fiq, !!fiq);
47 }
48
49 static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
50 {
51 AwA10PICState *s = opaque;
52 uint32_t *pending_reg = &s->irq_pending[irq / 32];
53
54 *pending_reg = deposit32(*pending_reg, irq % 32, 1, !!level);
55 aw_a10_pic_update(s);
56 }
57
58 static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
59 {
60 AwA10PICState *s = opaque;
61 uint8_t index = (offset & 0xc) / 4;
62
63 switch (offset) {
64 case AW_A10_PIC_VECTOR:
65 return s->vector;
66 case AW_A10_PIC_BASE_ADDR:
67 return s->base_addr;
68 case AW_A10_PIC_PROTECT:
69 return s->protect;
70 case AW_A10_PIC_NMI:
71 return s->nmi;
72 case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
73 return s->irq_pending[index];
74 case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
75 return s->fiq_pending[index];
76 case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
77 return s->select[index];
78 case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
79 return s->enable[index];
80 case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
81 return s->mask[index];
82 default:
83 qemu_log_mask(LOG_GUEST_ERROR,
84 "%s: Bad offset 0x%x\n", __func__, (int)offset);
85 break;
86 }
87
88 return 0;
89 }
90
91 static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
92 unsigned size)
93 {
94 AwA10PICState *s = opaque;
95 uint8_t index = (offset & 0xc) / 4;
96
97 switch (offset) {
98 case AW_A10_PIC_BASE_ADDR:
99 s->base_addr = value & ~0x3;
100 break;
101 case AW_A10_PIC_PROTECT:
102 s->protect = value;
103 break;
104 case AW_A10_PIC_NMI:
105 s->nmi = value;
106 break;
107 case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
108 /*
109 * The register is read-only; nevertheless, Linux (including
110 * the version originally shipped by Allwinner) pretends to
111 * write to the register. Just ignore it.
112 */
113 break;
114 case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
115 s->fiq_pending[index] &= ~value;
116 break;
117 case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
118 s->select[index] = value;
119 break;
120 case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
121 s->enable[index] = value;
122 break;
123 case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
124 s->mask[index] = value;
125 break;
126 default:
127 qemu_log_mask(LOG_GUEST_ERROR,
128 "%s: Bad offset 0x%x\n", __func__, (int)offset);
129 break;
130 }
131
132 aw_a10_pic_update(s);
133 }
134
135 static const MemoryRegionOps aw_a10_pic_ops = {
136 .read = aw_a10_pic_read,
137 .write = aw_a10_pic_write,
138 .endianness = DEVICE_LITTLE_ENDIAN,
139 };
140
141 static const VMStateDescription vmstate_aw_a10_pic = {
142 .name = "a10.pic",
143 .version_id = 1,
144 .minimum_version_id = 1,
145 .fields = (const VMStateField[]) {
146 VMSTATE_UINT32(vector, AwA10PICState),
147 VMSTATE_UINT32(base_addr, AwA10PICState),
148 VMSTATE_UINT32(protect, AwA10PICState),
149 VMSTATE_UINT32(nmi, AwA10PICState),
150 VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
151 VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
152 VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM),
153 VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM),
154 VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM),
155 VMSTATE_END_OF_LIST()
156 }
157 };
158
159 static void aw_a10_pic_init(Object *obj)
160 {
161 AwA10PICState *s = AW_A10_PIC(obj);
162 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
163
164 qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);
165 sysbus_init_irq(dev, &s->parent_irq);
166 sysbus_init_irq(dev, &s->parent_fiq);
167 memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,
168 TYPE_AW_A10_PIC, 0x400);
169 sysbus_init_mmio(dev, &s->iomem);
170 }
171
172 static void aw_a10_pic_reset(DeviceState *d)
173 {
174 AwA10PICState *s = AW_A10_PIC(d);
175 uint8_t i;
176
177 s->base_addr = 0;
178 s->protect = 0;
179 s->nmi = 0;
180 s->vector = 0;
181 for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
182 s->irq_pending[i] = 0;
183 s->fiq_pending[i] = 0;
184 s->select[i] = 0;
185 s->enable[i] = 0;
186 s->mask[i] = 0;
187 }
188 }
189
190 static void aw_a10_pic_class_init(ObjectClass *klass, const void *data)
191 {
192 DeviceClass *dc = DEVICE_CLASS(klass);
193
194 device_class_set_legacy_reset(dc, aw_a10_pic_reset);
195 dc->desc = "allwinner a10 pic";
196 dc->vmsd = &vmstate_aw_a10_pic;
197 }
198
199 static const TypeInfo aw_a10_pic_info = {
200 .name = TYPE_AW_A10_PIC,
201 .parent = TYPE_SYS_BUS_DEVICE,
202 .instance_size = sizeof(AwA10PICState),
203 .instance_init = aw_a10_pic_init,
204 .class_init = aw_a10_pic_class_init,
205 };
206
207 static void aw_a10_register_types(void)
208 {
209 type_register_static(&aw_a10_pic_info);
210 }
211
212 type_init(aw_a10_register_types);