| 1 | /* |
| 2 | * APIC support |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
| 18 | */ |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu/thread.h" |
| 21 | #include "qemu/error-report.h" |
| 22 | #include "hw/i386/apic_internal.h" |
| 23 | #include "hw/i386/apic.h" |
| 24 | #include "hw/intc/ioapic.h" |
| 25 | #include "hw/intc/i8259.h" |
| 26 | #include "hw/intc/kvm_irqcount.h" |
| 27 | #include "hw/pci/msi.h" |
| 28 | #include "qemu/host-utils.h" |
| 29 | #include "system/kvm.h" |
| 30 | #include "system/mshv.h" |
| 31 | #include "system/physmem.h" |
| 32 | #include "trace.h" |
| 33 | #include "hw/i386/apic-msidef.h" |
| 34 | #include "exec/cpu-common.h" |
| 35 | #include "qapi/error.h" |
| 36 | #include "qom/object.h" |
| 37 | |
| 38 | #define SYNC_FROM_VAPIC 0x1 |
| 39 | #define SYNC_TO_VAPIC 0x2 |
| 40 | #define SYNC_ISR_IRR_TO_VAPIC 0x4 |
| 41 | |
| 42 | static APICCommonState **local_apics; |
| 43 | static uint32_t max_apics; |
| 44 | static uint32_t max_apic_words; |
| 45 | |
| 46 | #define TYPE_APIC "apic" |
| 47 | /*This is reusing the APICCommonState typedef from APIC_COMMON */ |
| 48 | DECLARE_INSTANCE_CHECKER(APICCommonState, APIC, |
| 49 | TYPE_APIC) |
| 50 | |
| 51 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); |
| 52 | static void apic_update_irq(APICCommonState *s); |
| 53 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
| 54 | uint32_t dest, uint8_t dest_mode); |
| 55 | |
| 56 | void apic_set_max_apic_id(uint32_t max_apic_id) |
| 57 | { |
| 58 | int word_size = 32; |
| 59 | |
| 60 | /* round up the max apic id to next multiple of words */ |
| 61 | max_apics = (max_apic_id + word_size - 1) & ~(word_size - 1); |
| 62 | |
| 63 | local_apics = g_malloc0(sizeof(*local_apics) * max_apics); |
| 64 | max_apic_words = max_apics >> 5; |
| 65 | } |
| 66 | |
| 67 | |
| 68 | /* Find first bit starting from msb */ |
| 69 | static int apic_fls_bit(uint32_t value) |
| 70 | { |
| 71 | return 31 - clz32(value); |
| 72 | } |
| 73 | |
| 74 | /* Find first bit starting from lsb */ |
| 75 | static int apic_ffs_bit(uint32_t value) |
| 76 | { |
| 77 | return ctz32(value); |
| 78 | } |
| 79 | |
| 80 | static inline void apic_reset_bit(uint32_t *tab, int index) |
| 81 | { |
| 82 | int i, mask; |
| 83 | i = index >> 5; |
| 84 | mask = 1 << (index & 0x1f); |
| 85 | tab[i] &= ~mask; |
| 86 | } |
| 87 | |
| 88 | /* return -1 if no bit is set */ |
| 89 | static int get_highest_priority_int(uint32_t *tab) |
| 90 | { |
| 91 | int i; |
| 92 | for (i = 7; i >= 0; i--) { |
| 93 | if (tab[i] != 0) { |
| 94 | return i * 32 + apic_fls_bit(tab[i]); |
| 95 | } |
| 96 | } |
| 97 | return -1; |
| 98 | } |
| 99 | |
| 100 | static void apic_sync_vapic(APICCommonState *s, int sync_type) |
| 101 | { |
| 102 | VAPICState vapic_state; |
| 103 | size_t length; |
| 104 | off_t start; |
| 105 | int vector; |
| 106 | |
| 107 | if (!s->vapic_paddr) { |
| 108 | return; |
| 109 | } |
| 110 | if (sync_type & SYNC_FROM_VAPIC) { |
| 111 | physical_memory_read(s->vapic_paddr, &vapic_state, |
| 112 | sizeof(vapic_state)); |
| 113 | s->tpr = vapic_state.tpr; |
| 114 | } |
| 115 | if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { |
| 116 | start = offsetof(VAPICState, isr); |
| 117 | length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); |
| 118 | |
| 119 | if (sync_type & SYNC_TO_VAPIC) { |
| 120 | assert(qemu_cpu_is_self(CPU(s->cpu))); |
| 121 | |
| 122 | vapic_state.tpr = s->tpr; |
| 123 | vapic_state.enabled = 1; |
| 124 | start = 0; |
| 125 | length = sizeof(VAPICState); |
| 126 | } |
| 127 | |
| 128 | vector = get_highest_priority_int(s->isr); |
| 129 | if (vector < 0) { |
| 130 | vector = 0; |
| 131 | } |
| 132 | vapic_state.isr = vector & 0xf0; |
| 133 | |
| 134 | vapic_state.zero = 0; |
| 135 | |
| 136 | vector = get_highest_priority_int(s->irr); |
| 137 | if (vector < 0) { |
| 138 | vector = 0; |
| 139 | } |
| 140 | vapic_state.irr = vector & 0xff; |
| 141 | |
| 142 | address_space_write_rom(&address_space_memory, |
| 143 | s->vapic_paddr + start, |
| 144 | MEMTXATTRS_UNSPECIFIED, |
| 145 | ((void *)&vapic_state) + start, length); |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | static void apic_vapic_base_update(APICCommonState *s) |
| 150 | { |
| 151 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 152 | } |
| 153 | |
| 154 | static void apic_local_deliver(APICCommonState *s, int vector) |
| 155 | { |
| 156 | uint32_t lvt = s->lvt[vector]; |
| 157 | int trigger_mode; |
| 158 | |
| 159 | trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
| 160 | |
| 161 | if (lvt & APIC_LVT_MASKED) |
| 162 | return; |
| 163 | |
| 164 | switch ((lvt >> 8) & 7) { |
| 165 | case APIC_DM_SMI: |
| 166 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); |
| 167 | break; |
| 168 | |
| 169 | case APIC_DM_NMI: |
| 170 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); |
| 171 | break; |
| 172 | |
| 173 | case APIC_DM_EXTINT: |
| 174 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); |
| 175 | break; |
| 176 | |
| 177 | case APIC_DM_FIXED: |
| 178 | trigger_mode = APIC_TRIGGER_EDGE; |
| 179 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && |
| 180 | (lvt & APIC_LVT_LEVEL_TRIGGER)) |
| 181 | trigger_mode = APIC_TRIGGER_LEVEL; |
| 182 | apic_set_irq(s, lvt & 0xff, trigger_mode); |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | void apic_deliver_pic_intr(APICCommonState *s, int level) |
| 187 | { |
| 188 | if (level) { |
| 189 | apic_local_deliver(s, APIC_LVT_LINT0); |
| 190 | } else { |
| 191 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
| 192 | |
| 193 | switch ((lvt >> 8) & 7) { |
| 194 | case APIC_DM_FIXED: |
| 195 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) |
| 196 | break; |
| 197 | apic_reset_bit(s->irr, lvt & 0xff); |
| 198 | /* fall through */ |
| 199 | case APIC_DM_EXTINT: |
| 200 | apic_update_irq(s); |
| 201 | break; |
| 202 | } |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | static void apic_external_nmi(APICCommonState *s) |
| 207 | { |
| 208 | apic_local_deliver(s, APIC_LVT_LINT1); |
| 209 | } |
| 210 | |
| 211 | #define foreach_apic(apic, deliver_bitmask, code) \ |
| 212 | {\ |
| 213 | int __i, __j;\ |
| 214 | for (__i = 0; __i < max_apic_words; __i++) {\ |
| 215 | uint32_t __mask = deliver_bitmask[__i];\ |
| 216 | if (__mask) {\ |
| 217 | for (__j = 0; __j < 32; __j++) {\ |
| 218 | if (__mask & (1U << __j)) {\ |
| 219 | apic = local_apics[__i * 32 + __j];\ |
| 220 | if (apic) {\ |
| 221 | code;\ |
| 222 | }\ |
| 223 | }\ |
| 224 | }\ |
| 225 | }\ |
| 226 | }\ |
| 227 | } |
| 228 | |
| 229 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
| 230 | uint8_t delivery_mode, uint8_t vector_num, |
| 231 | uint8_t trigger_mode) |
| 232 | { |
| 233 | APICCommonState *apic_iter; |
| 234 | |
| 235 | switch (delivery_mode) { |
| 236 | case APIC_DM_LOWPRI: |
| 237 | /* XXX: search for focus processor, arbitration */ |
| 238 | { |
| 239 | int i, d; |
| 240 | d = -1; |
| 241 | for (i = 0; i < max_apic_words; i++) { |
| 242 | if (deliver_bitmask[i]) { |
| 243 | d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); |
| 244 | break; |
| 245 | } |
| 246 | } |
| 247 | if (d >= 0) { |
| 248 | apic_iter = local_apics[d]; |
| 249 | if (apic_iter) { |
| 250 | apic_set_irq(apic_iter, vector_num, trigger_mode); |
| 251 | } |
| 252 | } |
| 253 | } |
| 254 | return; |
| 255 | |
| 256 | case APIC_DM_FIXED: |
| 257 | break; |
| 258 | |
| 259 | case APIC_DM_SMI: |
| 260 | foreach_apic(apic_iter, deliver_bitmask, |
| 261 | cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) |
| 262 | ); |
| 263 | return; |
| 264 | |
| 265 | case APIC_DM_NMI: |
| 266 | foreach_apic(apic_iter, deliver_bitmask, |
| 267 | cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) |
| 268 | ); |
| 269 | return; |
| 270 | |
| 271 | case APIC_DM_INIT: |
| 272 | /* normal INIT IPI sent to processors */ |
| 273 | foreach_apic(apic_iter, deliver_bitmask, |
| 274 | cpu_interrupt(CPU(apic_iter->cpu), |
| 275 | CPU_INTERRUPT_INIT) |
| 276 | ); |
| 277 | return; |
| 278 | |
| 279 | case APIC_DM_EXTINT: |
| 280 | /* handled in I/O APIC code */ |
| 281 | break; |
| 282 | |
| 283 | default: |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | foreach_apic(apic_iter, deliver_bitmask, |
| 288 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
| 289 | } |
| 290 | |
| 291 | static void apic_deliver_irq(uint32_t dest, uint8_t dest_mode, |
| 292 | uint8_t delivery_mode, uint8_t vector_num, |
| 293 | uint8_t trigger_mode) |
| 294 | { |
| 295 | g_autofree uint32_t *deliver_bitmask = g_new(uint32_t, max_apic_words); |
| 296 | |
| 297 | trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
| 298 | trigger_mode); |
| 299 | |
| 300 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 301 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
| 302 | } |
| 303 | |
| 304 | bool is_x2apic_mode(APICCommonState *s) |
| 305 | { |
| 306 | return s->apicbase & MSR_IA32_APICBASE_EXTD; |
| 307 | } |
| 308 | |
| 309 | static int apic_set_base_check(APICCommonState *s, uint64_t val) |
| 310 | { |
| 311 | /* Enable x2apic when x2apic is not supported by CPU */ |
| 312 | if (!cpu_has_x2apic_feature(&s->cpu->env) && |
| 313 | val & MSR_IA32_APICBASE_EXTD) { |
| 314 | return -1; |
| 315 | } |
| 316 | |
| 317 | /* |
| 318 | * Transition into invalid state |
| 319 | * (s->apicbase & MSR_IA32_APICBASE_ENABLE == 0) && |
| 320 | * (s->apicbase & MSR_IA32_APICBASE_EXTD) == 1 |
| 321 | */ |
| 322 | if (!(val & MSR_IA32_APICBASE_ENABLE) && |
| 323 | (val & MSR_IA32_APICBASE_EXTD)) { |
| 324 | return -1; |
| 325 | } |
| 326 | |
| 327 | /* Invalid transition from disabled mode to x2APIC */ |
| 328 | if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && |
| 329 | !(s->apicbase & MSR_IA32_APICBASE_EXTD) && |
| 330 | (val & MSR_IA32_APICBASE_ENABLE) && |
| 331 | (val & MSR_IA32_APICBASE_EXTD)) { |
| 332 | return -1; |
| 333 | } |
| 334 | |
| 335 | /* Invalid transition from x2APIC to xAPIC */ |
| 336 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) && |
| 337 | (s->apicbase & MSR_IA32_APICBASE_EXTD) && |
| 338 | (val & MSR_IA32_APICBASE_ENABLE) && |
| 339 | !(val & MSR_IA32_APICBASE_EXTD)) { |
| 340 | return -1; |
| 341 | } |
| 342 | |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | static int apic_set_base(APICCommonState *s, uint64_t val) |
| 347 | { |
| 348 | if (apic_set_base_check(s, val) < 0) { |
| 349 | return -1; |
| 350 | } |
| 351 | |
| 352 | s->apicbase = (val & MSR_IA32_APICBASE_BASE) | |
| 353 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
| 354 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { |
| 355 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
| 356 | cpu_clear_apic_feature(&s->cpu->env); |
| 357 | s->spurious_vec &= ~APIC_SV_ENABLE; |
| 358 | } |
| 359 | |
| 360 | /* Transition from disabled mode to xAPIC */ |
| 361 | if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && |
| 362 | (val & MSR_IA32_APICBASE_ENABLE)) { |
| 363 | s->apicbase |= MSR_IA32_APICBASE_ENABLE; |
| 364 | cpu_set_apic_feature(&s->cpu->env); |
| 365 | } |
| 366 | |
| 367 | /* Transition from xAPIC to x2APIC */ |
| 368 | if (cpu_has_x2apic_feature(&s->cpu->env) && |
| 369 | !(s->apicbase & MSR_IA32_APICBASE_EXTD) && |
| 370 | (val & MSR_IA32_APICBASE_EXTD)) { |
| 371 | s->apicbase |= MSR_IA32_APICBASE_EXTD; |
| 372 | |
| 373 | s->log_dest = ((s->initial_apic_id & 0xffff0) << 16) | |
| 374 | (1 << (s->initial_apic_id & 0xf)); |
| 375 | } |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | static void apic_set_tpr(APICCommonState *s, uint8_t val) |
| 381 | { |
| 382 | /* Updates from cr8 are ignored while the VAPIC is active */ |
| 383 | if (!s->vapic_paddr) { |
| 384 | s->tpr = val << 4; |
| 385 | apic_update_irq(s); |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | int apic_get_highest_priority_irr(APICCommonState *s) |
| 390 | { |
| 391 | if (!s) { |
| 392 | /* no interrupts */ |
| 393 | return -1; |
| 394 | } |
| 395 | return get_highest_priority_int(s->irr); |
| 396 | } |
| 397 | |
| 398 | static uint8_t apic_get_tpr(APICCommonState *s) |
| 399 | { |
| 400 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 401 | return s->tpr >> 4; |
| 402 | } |
| 403 | |
| 404 | int apic_get_ppr(APICCommonState *s) |
| 405 | { |
| 406 | int tpr, isrv, ppr; |
| 407 | |
| 408 | tpr = (s->tpr >> 4); |
| 409 | isrv = get_highest_priority_int(s->isr); |
| 410 | if (isrv < 0) |
| 411 | isrv = 0; |
| 412 | isrv >>= 4; |
| 413 | if (tpr >= isrv) |
| 414 | ppr = s->tpr; |
| 415 | else |
| 416 | ppr = isrv << 4; |
| 417 | return ppr; |
| 418 | } |
| 419 | |
| 420 | static int apic_get_arb_pri(APICCommonState *s) |
| 421 | { |
| 422 | /* XXX: arbitration */ |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | |
| 427 | /* |
| 428 | * <0 - low prio interrupt, |
| 429 | * 0 - no interrupt, |
| 430 | * >0 - interrupt number |
| 431 | */ |
| 432 | static int apic_irq_pending(APICCommonState *s) |
| 433 | { |
| 434 | int irrv, ppr; |
| 435 | |
| 436 | if (!(s->spurious_vec & APIC_SV_ENABLE)) { |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | irrv = get_highest_priority_int(s->irr); |
| 441 | if (irrv < 0) { |
| 442 | return 0; |
| 443 | } |
| 444 | ppr = apic_get_ppr(s); |
| 445 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
| 446 | return -1; |
| 447 | } |
| 448 | |
| 449 | return irrv; |
| 450 | } |
| 451 | |
| 452 | /* signal the CPU if an irq is pending */ |
| 453 | static void apic_update_irq(APICCommonState *s) |
| 454 | { |
| 455 | CPUState *cpu; |
| 456 | |
| 457 | cpu = CPU(s->cpu); |
| 458 | if (!qemu_cpu_is_self(cpu)) { |
| 459 | cpu_interrupt(cpu, CPU_INTERRUPT_POLL); |
| 460 | } else if (apic_irq_pending(s) > 0) { |
| 461 | cpu_interrupt(cpu, CPU_INTERRUPT_HARD); |
| 462 | } else if (!apic_accept_pic_intr(s) || !pic_get_output(isa_pic)) { |
| 463 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | void apic_poll_irq(APICCommonState *s) |
| 468 | { |
| 469 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 470 | apic_update_irq(s); |
| 471 | } |
| 472 | |
| 473 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) |
| 474 | { |
| 475 | kvm_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); |
| 476 | |
| 477 | apic_set_bit(s->irr, vector_num); |
| 478 | if (trigger_mode) |
| 479 | apic_set_bit(s->tmr, vector_num); |
| 480 | else |
| 481 | apic_reset_bit(s->tmr, vector_num); |
| 482 | if (s->vapic_paddr) { |
| 483 | apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); |
| 484 | /* |
| 485 | * The vcpu thread needs to see the new IRR before we pull its current |
| 486 | * TPR value. That way, if we miss a lowering of the TRP, the guest |
| 487 | * has the chance to notice the new IRR and poll for IRQs on its own. |
| 488 | */ |
| 489 | smp_wmb(); |
| 490 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 491 | } |
| 492 | apic_update_irq(s); |
| 493 | } |
| 494 | |
| 495 | static void apic_eoi(APICCommonState *s) |
| 496 | { |
| 497 | int isrv; |
| 498 | isrv = get_highest_priority_int(s->isr); |
| 499 | if (isrv < 0) |
| 500 | return; |
| 501 | apic_reset_bit(s->isr, isrv); |
| 502 | if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { |
| 503 | ioapic_eoi_broadcast(isrv); |
| 504 | } |
| 505 | apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); |
| 506 | apic_update_irq(s); |
| 507 | } |
| 508 | |
| 509 | static bool apic_match_dest(APICCommonState *apic, uint32_t dest) |
| 510 | { |
| 511 | if (is_x2apic_mode(apic)) { |
| 512 | return apic->initial_apic_id == dest; |
| 513 | } else { |
| 514 | return apic->id == (uint8_t)dest; |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | static void apic_find_dest(uint32_t *deliver_bitmask, uint32_t dest) |
| 519 | { |
| 520 | APICCommonState *apic = NULL; |
| 521 | int i; |
| 522 | |
| 523 | for (i = 0; i < max_apics; i++) { |
| 524 | apic = local_apics[i]; |
| 525 | if (apic && apic_match_dest(apic, dest)) { |
| 526 | apic_set_bit(deliver_bitmask, i); |
| 527 | } |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | /* |
| 532 | * Deliver interrupt to x2APIC CPUs if it is x2APIC broadcast. |
| 533 | * Otherwise, deliver interrupt to xAPIC CPUs if it is xAPIC |
| 534 | * broadcast. |
| 535 | */ |
| 536 | static void apic_get_broadcast_bitmask(uint32_t *deliver_bitmask, |
| 537 | bool is_x2apic_broadcast) |
| 538 | { |
| 539 | int i; |
| 540 | APICCommonState *apic_iter; |
| 541 | |
| 542 | for (i = 0; i < max_apics; i++) { |
| 543 | apic_iter = local_apics[i]; |
| 544 | if (apic_iter) { |
| 545 | bool apic_in_x2apic = is_x2apic_mode(apic_iter); |
| 546 | |
| 547 | if (is_x2apic_broadcast && apic_in_x2apic) { |
| 548 | apic_set_bit(deliver_bitmask, i); |
| 549 | } else if (!is_x2apic_broadcast && !apic_in_x2apic) { |
| 550 | apic_set_bit(deliver_bitmask, i); |
| 551 | } |
| 552 | } |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
| 557 | uint32_t dest, uint8_t dest_mode) |
| 558 | { |
| 559 | APICCommonState *apic; |
| 560 | int i; |
| 561 | |
| 562 | memset(deliver_bitmask, 0x00, max_apic_words * sizeof(uint32_t)); |
| 563 | |
| 564 | /* |
| 565 | * x2APIC broadcast is delivered to all x2APIC CPUs regardless of |
| 566 | * destination mode. In case the destination mode is physical, it is |
| 567 | * broadcasted to all xAPIC CPUs too. Otherwise, if the destination |
| 568 | * mode is logical, we need to continue checking if xAPIC CPUs accepts |
| 569 | * the interrupt. |
| 570 | */ |
| 571 | if (dest == 0xffffffff) { |
| 572 | if (dest_mode == APIC_DESTMODE_PHYSICAL) { |
| 573 | memset(deliver_bitmask, 0xff, max_apic_words * sizeof(uint32_t)); |
| 574 | return; |
| 575 | } else { |
| 576 | apic_get_broadcast_bitmask(deliver_bitmask, true); |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | if (dest_mode == APIC_DESTMODE_PHYSICAL) { |
| 581 | apic_find_dest(deliver_bitmask, dest); |
| 582 | /* Any APIC in xAPIC mode will interpret 0xFF as broadcast */ |
| 583 | if (dest == 0xff) { |
| 584 | apic_get_broadcast_bitmask(deliver_bitmask, false); |
| 585 | } |
| 586 | } else { |
| 587 | /* XXX: logical mode */ |
| 588 | for (i = 0; i < max_apics; i++) { |
| 589 | apic = local_apics[i]; |
| 590 | if (apic) { |
| 591 | /* x2APIC logical mode */ |
| 592 | if (apic->apicbase & MSR_IA32_APICBASE_EXTD) { |
| 593 | if ((dest >> 16) == (apic->extended_log_dest >> 16) && |
| 594 | (dest & apic->extended_log_dest & 0xffff)) { |
| 595 | apic_set_bit(deliver_bitmask, i); |
| 596 | } |
| 597 | continue; |
| 598 | } |
| 599 | |
| 600 | /* xAPIC logical mode */ |
| 601 | dest = (uint8_t)dest; |
| 602 | if (apic->dest_mode == APIC_DESTMODE_LOGICAL_FLAT) { |
| 603 | if (dest & apic->log_dest) { |
| 604 | apic_set_bit(deliver_bitmask, i); |
| 605 | } |
| 606 | } else if (apic->dest_mode == APIC_DESTMODE_LOGICAL_CLUSTER) { |
| 607 | /* |
| 608 | * In cluster model of xAPIC logical mode IPI, 4 higher |
| 609 | * bits are used as cluster address, 4 lower bits are |
| 610 | * the bitmask for local APICs in the cluster. The IPI |
| 611 | * is delivered to an APIC if the cluster address |
| 612 | * matches and the APIC's address bit in the cluster is |
| 613 | * set in bitmask of destination ID in IPI. |
| 614 | * |
| 615 | * The cluster address ranges from 0 - 14, the cluster |
| 616 | * address 15 (0xf) is the broadcast address to all |
| 617 | * clusters. |
| 618 | */ |
| 619 | if ((dest & 0xf0) == 0xf0 || |
| 620 | (dest & 0xf0) == (apic->log_dest & 0xf0)) { |
| 621 | if (dest & apic->log_dest & 0x0f) { |
| 622 | apic_set_bit(deliver_bitmask, i); |
| 623 | } |
| 624 | } |
| 625 | } |
| 626 | } |
| 627 | } |
| 628 | } |
| 629 | } |
| 630 | |
| 631 | static void apic_startup(APICCommonState *s, int vector_num) |
| 632 | { |
| 633 | s->sipi_vector = vector_num; |
| 634 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); |
| 635 | } |
| 636 | |
| 637 | void apic_sipi(APICCommonState *s) |
| 638 | { |
| 639 | if (!s->wait_for_sipi) |
| 640 | return; |
| 641 | cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); |
| 642 | s->wait_for_sipi = 0; |
| 643 | } |
| 644 | |
| 645 | static void apic_deliver(APICCommonState *s, uint32_t dest, uint8_t dest_mode, |
| 646 | uint8_t delivery_mode, uint8_t vector_num, |
| 647 | uint8_t trigger_mode, uint8_t dest_shorthand) |
| 648 | { |
| 649 | APICCommonState *apic_iter; |
| 650 | uint32_t deliver_bitmask_size = max_apic_words * sizeof(uint32_t); |
| 651 | g_autofree uint32_t *deliver_bitmask = g_new(uint32_t, max_apic_words); |
| 652 | |
| 653 | switch (dest_shorthand) { |
| 654 | case 0: |
| 655 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 656 | break; |
| 657 | case 1: |
| 658 | memset(deliver_bitmask, 0x00, deliver_bitmask_size); |
| 659 | /* |
| 660 | * The self and all-but-self cases do not use apic_match_dest() and |
| 661 | * directly fill in deliver_bitmask; the bitmask's indexes in turn |
| 662 | * map to local_apics[] slots which are never changed even if the |
| 663 | * xAPIC id is modified. So use s->initial_apic_id instead of s->id. |
| 664 | */ |
| 665 | apic_set_bit(deliver_bitmask, s->initial_apic_id); |
| 666 | break; |
| 667 | case 2: |
| 668 | memset(deliver_bitmask, 0xff, deliver_bitmask_size); |
| 669 | break; |
| 670 | case 3: |
| 671 | memset(deliver_bitmask, 0xff, deliver_bitmask_size); |
| 672 | apic_reset_bit(deliver_bitmask, s->initial_apic_id); |
| 673 | break; |
| 674 | } |
| 675 | |
| 676 | switch (delivery_mode) { |
| 677 | case APIC_DM_INIT: |
| 678 | { |
| 679 | int trig_mode = (s->icr[0] >> 15) & 1; |
| 680 | int level = (s->icr[0] >> 14) & 1; |
| 681 | if (level == 0 && trig_mode == 1) { |
| 682 | foreach_apic(apic_iter, deliver_bitmask, |
| 683 | apic_iter->arb_id = apic_iter->id ); |
| 684 | return; |
| 685 | } |
| 686 | } |
| 687 | break; |
| 688 | |
| 689 | case APIC_DM_SIPI: |
| 690 | foreach_apic(apic_iter, deliver_bitmask, |
| 691 | apic_startup(apic_iter, vector_num) ); |
| 692 | return; |
| 693 | } |
| 694 | |
| 695 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
| 696 | } |
| 697 | |
| 698 | static bool apic_check_pic(APICCommonState *s) |
| 699 | { |
| 700 | if (!apic_accept_pic_intr(s) || !pic_get_output(isa_pic)) { |
| 701 | return false; |
| 702 | } |
| 703 | apic_deliver_pic_intr(s, 1); |
| 704 | return true; |
| 705 | } |
| 706 | |
| 707 | int apic_get_interrupt(APICCommonState *s) |
| 708 | { |
| 709 | int intno; |
| 710 | |
| 711 | /* if the APIC is installed or enabled, we let the 8259 handle the |
| 712 | IRQs */ |
| 713 | if (!s) |
| 714 | return -1; |
| 715 | if (!(s->spurious_vec & APIC_SV_ENABLE)) |
| 716 | return -1; |
| 717 | |
| 718 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 719 | intno = apic_irq_pending(s); |
| 720 | |
| 721 | /* if there is an interrupt from the 8259, let the caller handle |
| 722 | * that first since ExtINT interrupts ignore the priority. |
| 723 | */ |
| 724 | if (intno == 0 || apic_check_pic(s)) { |
| 725 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 726 | return -1; |
| 727 | } else if (intno < 0) { |
| 728 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 729 | return s->spurious_vec & 0xff; |
| 730 | } |
| 731 | apic_reset_bit(s->irr, intno); |
| 732 | apic_set_bit(s->isr, intno); |
| 733 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 734 | |
| 735 | apic_update_irq(s); |
| 736 | |
| 737 | return intno; |
| 738 | } |
| 739 | |
| 740 | int apic_accept_pic_intr(APICCommonState *s) |
| 741 | { |
| 742 | uint32_t lvt0; |
| 743 | |
| 744 | if (!s) |
| 745 | return -1; |
| 746 | |
| 747 | lvt0 = s->lvt[APIC_LVT_LINT0]; |
| 748 | |
| 749 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
| 750 | (lvt0 & APIC_LVT_MASKED) == 0) |
| 751 | return isa_pic != NULL; |
| 752 | |
| 753 | return 0; |
| 754 | } |
| 755 | |
| 756 | static void apic_timer_update(APICCommonState *s, int64_t current_time) |
| 757 | { |
| 758 | if (apic_next_timer(s, current_time)) { |
| 759 | timer_mod(s->timer, s->next_time); |
| 760 | } else { |
| 761 | timer_del(s->timer); |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | static void apic_timer(void *opaque) |
| 766 | { |
| 767 | APICCommonState *s = opaque; |
| 768 | |
| 769 | apic_local_deliver(s, APIC_LVT_TIMER); |
| 770 | apic_timer_update(s, s->next_time); |
| 771 | } |
| 772 | |
| 773 | static int apic_register_read(APICCommonState *s, int index, uint64_t *value) |
| 774 | { |
| 775 | uint32_t val; |
| 776 | int ret = 0; |
| 777 | |
| 778 | switch(index) { |
| 779 | case 0x02: /* id */ |
| 780 | if (is_x2apic_mode(s)) { |
| 781 | val = s->initial_apic_id; |
| 782 | } else { |
| 783 | val = s->id << 24; |
| 784 | } |
| 785 | break; |
| 786 | case 0x03: /* version */ |
| 787 | val = s->version | ((APIC_LVT_NB - 1) << 16); |
| 788 | break; |
| 789 | case 0x08: |
| 790 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 791 | if (apic_report_tpr_access) { |
| 792 | cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); |
| 793 | } |
| 794 | val = s->tpr; |
| 795 | break; |
| 796 | case 0x09: |
| 797 | val = apic_get_arb_pri(s); |
| 798 | break; |
| 799 | case 0x0a: |
| 800 | /* ppr */ |
| 801 | val = apic_get_ppr(s); |
| 802 | break; |
| 803 | case 0x0b: |
| 804 | val = 0; |
| 805 | break; |
| 806 | case 0x0d: |
| 807 | if (is_x2apic_mode(s)) { |
| 808 | val = s->extended_log_dest; |
| 809 | } else { |
| 810 | val = s->log_dest << 24; |
| 811 | } |
| 812 | break; |
| 813 | case 0x0e: |
| 814 | if (is_x2apic_mode(s)) { |
| 815 | val = 0; |
| 816 | ret = -1; |
| 817 | } else { |
| 818 | val = (s->dest_mode << 28) | 0xfffffff; |
| 819 | } |
| 820 | break; |
| 821 | case 0x0f: |
| 822 | val = s->spurious_vec; |
| 823 | break; |
| 824 | case 0x10 ... 0x17: |
| 825 | val = s->isr[index & 7]; |
| 826 | break; |
| 827 | case 0x18 ... 0x1f: |
| 828 | val = s->tmr[index & 7]; |
| 829 | break; |
| 830 | case 0x20 ... 0x27: |
| 831 | val = s->irr[index & 7]; |
| 832 | break; |
| 833 | case 0x28: |
| 834 | val = s->esr; |
| 835 | break; |
| 836 | case 0x30: |
| 837 | case 0x31: |
| 838 | val = s->icr[index & 1]; |
| 839 | break; |
| 840 | case 0x32 ... 0x37: |
| 841 | val = s->lvt[index - 0x32]; |
| 842 | break; |
| 843 | case 0x38: |
| 844 | val = s->initial_count; |
| 845 | break; |
| 846 | case 0x39: |
| 847 | val = apic_get_current_count(s); |
| 848 | break; |
| 849 | case 0x3e: |
| 850 | val = s->divide_conf; |
| 851 | break; |
| 852 | default: |
| 853 | s->esr |= APIC_ESR_ILLEGAL_ADDRESS; |
| 854 | val = 0; |
| 855 | ret = -1; |
| 856 | break; |
| 857 | } |
| 858 | |
| 859 | trace_apic_register_read(index, val); |
| 860 | *value = val; |
| 861 | return ret; |
| 862 | } |
| 863 | |
| 864 | static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) |
| 865 | { |
| 866 | APICCommonState *s = cpu_get_current_apic(); |
| 867 | uint64_t val; |
| 868 | int index; |
| 869 | |
| 870 | if (size < 4) { |
| 871 | return 0; |
| 872 | } |
| 873 | |
| 874 | if (!s) { |
| 875 | return -1; |
| 876 | } |
| 877 | |
| 878 | /* if the xAPIC is disabled, return early. */ |
| 879 | if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE)) { |
| 880 | return 0xffffffff; |
| 881 | } |
| 882 | |
| 883 | if (is_x2apic_mode(s)) { |
| 884 | return 0xffffffff; |
| 885 | } |
| 886 | |
| 887 | index = (addr >> 4) & 0xff; |
| 888 | apic_register_read(s, index, &val); |
| 889 | |
| 890 | return val; |
| 891 | } |
| 892 | |
| 893 | int apic_msr_read(APICCommonState *s, int index, uint64_t *val) |
| 894 | { |
| 895 | if (!s) { |
| 896 | return -1; |
| 897 | } |
| 898 | |
| 899 | if (!is_x2apic_mode(s)) { |
| 900 | return -1; |
| 901 | } |
| 902 | |
| 903 | return apic_register_read(s, index, val); |
| 904 | } |
| 905 | |
| 906 | static void apic_send_msi(MSIMessage *msi) |
| 907 | { |
| 908 | uint64_t addr = msi->address; |
| 909 | uint32_t data = msi->data; |
| 910 | uint32_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
| 911 | /* |
| 912 | * The higher 3 bytes of destination id is stored in higher word of |
| 913 | * msi address. See x86_iommu_irq_to_msi_message() |
| 914 | */ |
| 915 | dest = dest | (addr >> 32); |
| 916 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
| 917 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; |
| 918 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; |
| 919 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; |
| 920 | /* XXX: Ignore redirection hint. */ |
| 921 | #ifdef CONFIG_MSHV |
| 922 | if (mshv_enabled()) { |
| 923 | mshv_request_interrupt(mshv_state, delivery, vector, dest, |
| 924 | dest_mode, trigger_mode); |
| 925 | return; |
| 926 | } |
| 927 | #endif |
| 928 | apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
| 929 | } |
| 930 | |
| 931 | static int apic_register_write(APICCommonState *s, int index, uint64_t val) |
| 932 | { |
| 933 | trace_apic_register_write(index, val); |
| 934 | |
| 935 | switch(index) { |
| 936 | case 0x02: |
| 937 | if (is_x2apic_mode(s)) { |
| 938 | return -1; |
| 939 | } |
| 940 | |
| 941 | s->id = (val >> 24); |
| 942 | break; |
| 943 | case 0x03: |
| 944 | break; |
| 945 | case 0x08: |
| 946 | if (apic_report_tpr_access) { |
| 947 | cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); |
| 948 | } |
| 949 | s->tpr = val; |
| 950 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 951 | apic_update_irq(s); |
| 952 | break; |
| 953 | case 0x09: |
| 954 | case 0x0a: |
| 955 | break; |
| 956 | case 0x0b: /* EOI */ |
| 957 | apic_eoi(s); |
| 958 | break; |
| 959 | case 0x0d: |
| 960 | if (is_x2apic_mode(s)) { |
| 961 | return -1; |
| 962 | } |
| 963 | |
| 964 | s->log_dest = val >> 24; |
| 965 | break; |
| 966 | case 0x0e: |
| 967 | if (is_x2apic_mode(s)) { |
| 968 | return -1; |
| 969 | } |
| 970 | |
| 971 | s->dest_mode = val >> 28; |
| 972 | break; |
| 973 | case 0x0f: |
| 974 | s->spurious_vec = val & 0x1ff; |
| 975 | apic_update_irq(s); |
| 976 | break; |
| 977 | case 0x10 ... 0x17: |
| 978 | case 0x18 ... 0x1f: |
| 979 | case 0x20 ... 0x27: |
| 980 | case 0x28: |
| 981 | break; |
| 982 | case 0x30: { |
| 983 | uint32_t dest; |
| 984 | |
| 985 | s->icr[0] = val; |
| 986 | if (is_x2apic_mode(s)) { |
| 987 | s->icr[1] = val >> 32; |
| 988 | dest = s->icr[1]; |
| 989 | } else { |
| 990 | dest = (s->icr[1] >> 24) & 0xff; |
| 991 | } |
| 992 | |
| 993 | apic_deliver(s, dest, (s->icr[0] >> 11) & 1, |
| 994 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
| 995 | (s->icr[0] >> 15) & 1, (s->icr[0] >> 18) & 3); |
| 996 | break; |
| 997 | } |
| 998 | case 0x31: |
| 999 | if (is_x2apic_mode(s)) { |
| 1000 | return -1; |
| 1001 | } |
| 1002 | |
| 1003 | s->icr[1] = val; |
| 1004 | break; |
| 1005 | case 0x32 ... 0x37: |
| 1006 | { |
| 1007 | int n = index - 0x32; |
| 1008 | s->lvt[n] = val; |
| 1009 | if (n == APIC_LVT_TIMER) { |
| 1010 | apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
| 1011 | } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { |
| 1012 | apic_update_irq(s); |
| 1013 | } |
| 1014 | } |
| 1015 | break; |
| 1016 | case 0x38: |
| 1017 | s->initial_count = val; |
| 1018 | s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 1019 | apic_timer_update(s, s->initial_count_load_time); |
| 1020 | break; |
| 1021 | case 0x39: |
| 1022 | break; |
| 1023 | case 0x3e: |
| 1024 | { |
| 1025 | int v; |
| 1026 | s->divide_conf = val & 0xb; |
| 1027 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
| 1028 | s->count_shift = (v + 1) & 7; |
| 1029 | } |
| 1030 | break; |
| 1031 | case 0x3f: { |
| 1032 | int vector = val & 0xff; |
| 1033 | |
| 1034 | if (!is_x2apic_mode(s)) { |
| 1035 | return -1; |
| 1036 | } |
| 1037 | |
| 1038 | /* |
| 1039 | * Self IPI is identical to IPI with |
| 1040 | * - Destination shorthand: 1 (Self) |
| 1041 | * - Trigger mode: 0 (Edge) |
| 1042 | * - Delivery mode: 0 (Fixed) |
| 1043 | */ |
| 1044 | apic_deliver(s, 0, 0, APIC_DM_FIXED, vector, 0, 1); |
| 1045 | |
| 1046 | break; |
| 1047 | } |
| 1048 | default: |
| 1049 | s->esr |= APIC_ESR_ILLEGAL_ADDRESS; |
| 1050 | return -1; |
| 1051 | } |
| 1052 | |
| 1053 | return 0; |
| 1054 | } |
| 1055 | |
| 1056 | static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, |
| 1057 | unsigned size) |
| 1058 | { |
| 1059 | APICCommonState *s = cpu_get_current_apic(); |
| 1060 | int index = (addr >> 4) & 0xff; |
| 1061 | |
| 1062 | if (size < 4) { |
| 1063 | return; |
| 1064 | } |
| 1065 | |
| 1066 | if (addr > 0xfff || !index) { |
| 1067 | /* |
| 1068 | * MSI and MMIO APIC are at the same memory location, |
| 1069 | * but actually not on the global bus: MSI is on PCI bus |
| 1070 | * APIC is connected directly to the CPU. |
| 1071 | * Mapping them on the global bus happens to work because |
| 1072 | * MSI registers are reserved in APIC MMIO and vice versa. |
| 1073 | */ |
| 1074 | MSIMessage msi = { .address = addr, .data = val }; |
| 1075 | apic_send_msi(&msi); |
| 1076 | return; |
| 1077 | } |
| 1078 | |
| 1079 | if (!s) { |
| 1080 | return; |
| 1081 | } |
| 1082 | |
| 1083 | apic_register_write(s, index, val); |
| 1084 | } |
| 1085 | |
| 1086 | int apic_msr_write(APICCommonState *s, int index, uint64_t val) |
| 1087 | { |
| 1088 | if (!s) { |
| 1089 | return -1; |
| 1090 | } |
| 1091 | |
| 1092 | if (!is_x2apic_mode(s)) { |
| 1093 | return -1; |
| 1094 | } |
| 1095 | |
| 1096 | return apic_register_write(s, index, val); |
| 1097 | } |
| 1098 | |
| 1099 | static void apic_pre_save(APICCommonState *s) |
| 1100 | { |
| 1101 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 1102 | } |
| 1103 | |
| 1104 | static void apic_post_load(APICCommonState *s) |
| 1105 | { |
| 1106 | if (s->timer_expiry != -1) { |
| 1107 | timer_mod(s->timer, s->timer_expiry); |
| 1108 | } else { |
| 1109 | timer_del(s->timer); |
| 1110 | } |
| 1111 | } |
| 1112 | |
| 1113 | static const MemoryRegionOps apic_io_ops = { |
| 1114 | .read = apic_mem_read, |
| 1115 | .write = apic_mem_write, |
| 1116 | .impl.min_access_size = 1, |
| 1117 | .impl.max_access_size = 4, |
| 1118 | .valid.min_access_size = 1, |
| 1119 | .valid.max_access_size = 4, |
| 1120 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1121 | }; |
| 1122 | |
| 1123 | static void apic_realize(DeviceState *dev, Error **errp) |
| 1124 | { |
| 1125 | APICCommonState *s = APIC(dev); |
| 1126 | |
| 1127 | if (kvm_enabled()) { |
| 1128 | warn_report("Userspace local APIC is deprecated for KVM."); |
| 1129 | warn_report("Do not use kernel-irqchip except for the -M isapc machine type."); |
| 1130 | } |
| 1131 | |
| 1132 | memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", |
| 1133 | APIC_SPACE_SIZE); |
| 1134 | |
| 1135 | /* |
| 1136 | * apic-msi's apic_mem_write can call into ioapic_eoi_broadcast, which can |
| 1137 | * write back to apic-msi. As such mark the apic-msi region re-entrancy |
| 1138 | * safe. |
| 1139 | */ |
| 1140 | s->io_memory.disable_reentrancy_guard = true; |
| 1141 | |
| 1142 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); |
| 1143 | |
| 1144 | /* |
| 1145 | * The --machine none does not call apic_set_max_apic_id before creating |
| 1146 | * apic, so we need to call it here and set it to 1 which is the max cpus |
| 1147 | * in machine none. |
| 1148 | */ |
| 1149 | if (!local_apics) { |
| 1150 | apic_set_max_apic_id(1); |
| 1151 | } |
| 1152 | local_apics[s->initial_apic_id] = s; |
| 1153 | |
| 1154 | msi_nonbroken = true; |
| 1155 | } |
| 1156 | |
| 1157 | static void apic_unrealize(DeviceState *dev) |
| 1158 | { |
| 1159 | APICCommonState *s = APIC(dev); |
| 1160 | |
| 1161 | timer_free(s->timer); |
| 1162 | local_apics[s->initial_apic_id] = NULL; |
| 1163 | } |
| 1164 | |
| 1165 | static void apic_class_init(ObjectClass *klass, const void *data) |
| 1166 | { |
| 1167 | APICCommonClass *k = APIC_COMMON_CLASS(klass); |
| 1168 | |
| 1169 | k->realize = apic_realize; |
| 1170 | k->unrealize = apic_unrealize; |
| 1171 | k->set_base = apic_set_base; |
| 1172 | k->set_tpr = apic_set_tpr; |
| 1173 | k->get_tpr = apic_get_tpr; |
| 1174 | k->vapic_base_update = apic_vapic_base_update; |
| 1175 | k->external_nmi = apic_external_nmi; |
| 1176 | k->pre_save = apic_pre_save; |
| 1177 | k->post_load = apic_post_load; |
| 1178 | k->send_msi = apic_send_msi; |
| 1179 | } |
| 1180 | |
| 1181 | static const TypeInfo apic_info = { |
| 1182 | .name = TYPE_APIC, |
| 1183 | .instance_size = sizeof(APICCommonState), |
| 1184 | .parent = TYPE_APIC_COMMON, |
| 1185 | .class_init = apic_class_init, |
| 1186 | }; |
| 1187 | |
| 1188 | static void apic_register_types(void) |
| 1189 | { |
| 1190 | type_register_static(&apic_info); |
| 1191 | } |
| 1192 | |
| 1193 | type_init(apic_register_types) |