| 1 | /* |
| 2 | * APIC support - common bits of emulated and KVM kernel model |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Fabrice Bellard |
| 5 | * Copyright (c) 2011 Jan Kiszka, Siemens AG |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/error-report.h" |
| 23 | #include "qemu/module.h" |
| 24 | #include "qapi/error.h" |
| 25 | #include "qapi/visitor.h" |
| 26 | #include "hw/i386/apic.h" |
| 27 | #include "hw/i386/apic_internal.h" |
| 28 | #include "hw/intc/kvm_irqcount.h" |
| 29 | #include "trace.h" |
| 30 | #include "hw/core/boards.h" |
| 31 | #include "system/kvm.h" |
| 32 | #include "hw/core/qdev-properties.h" |
| 33 | #include "hw/core/sysbus.h" |
| 34 | #include "migration/vmstate.h" |
| 35 | |
| 36 | bool apic_report_tpr_access; |
| 37 | |
| 38 | int cpu_set_apic_base(APICCommonState *s, uint64_t val) |
| 39 | { |
| 40 | trace_cpu_set_apic_base(val); |
| 41 | |
| 42 | if (s) { |
| 43 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 44 | /* Reset possibly modified xAPIC ID */ |
| 45 | s->id = s->initial_apic_id; |
| 46 | return info->set_base(s, val); |
| 47 | } |
| 48 | |
| 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | uint64_t cpu_get_apic_base(APICCommonState *s) |
| 53 | { |
| 54 | if (s) { |
| 55 | trace_cpu_get_apic_base((uint64_t)s->apicbase); |
| 56 | return s->apicbase; |
| 57 | } else { |
| 58 | trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); |
| 59 | return MSR_IA32_APICBASE_BSP; |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | bool cpu_is_apic_enabled(APICCommonState *s) |
| 64 | { |
| 65 | if (!s) { |
| 66 | return false; |
| 67 | } |
| 68 | |
| 69 | return s->apicbase & MSR_IA32_APICBASE_ENABLE; |
| 70 | } |
| 71 | |
| 72 | void cpu_set_apic_tpr(APICCommonState *s, uint8_t val) |
| 73 | { |
| 74 | APICCommonClass *info; |
| 75 | |
| 76 | if (!s) { |
| 77 | return; |
| 78 | } |
| 79 | |
| 80 | info = APIC_COMMON_GET_CLASS(s); |
| 81 | |
| 82 | info->set_tpr(s, val); |
| 83 | } |
| 84 | |
| 85 | uint8_t cpu_get_apic_tpr(APICCommonState *s) |
| 86 | { |
| 87 | APICCommonClass *info; |
| 88 | |
| 89 | if (!s) { |
| 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | info = APIC_COMMON_GET_CLASS(s); |
| 94 | |
| 95 | return info->get_tpr(s); |
| 96 | } |
| 97 | |
| 98 | void apic_enable_tpr_access_reporting(APICCommonState *s, bool enable) |
| 99 | { |
| 100 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 101 | |
| 102 | apic_report_tpr_access = enable; |
| 103 | if (info->enable_tpr_reporting) { |
| 104 | info->enable_tpr_reporting(s, enable); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | void apic_enable_vapic(APICCommonState *s, hwaddr paddr) |
| 109 | { |
| 110 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 111 | |
| 112 | s->vapic_paddr = paddr; |
| 113 | info->vapic_base_update(s); |
| 114 | } |
| 115 | |
| 116 | void apic_handle_tpr_access_report(APICCommonState *s, target_ulong ip, |
| 117 | TPRAccess access) |
| 118 | { |
| 119 | vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); |
| 120 | } |
| 121 | |
| 122 | void apic_deliver_nmi(APICCommonState *s) |
| 123 | { |
| 124 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 125 | |
| 126 | info->external_nmi(s); |
| 127 | } |
| 128 | |
| 129 | bool apic_next_timer(APICCommonState *s, int64_t current_time) |
| 130 | { |
| 131 | int64_t d; |
| 132 | |
| 133 | /* We need to store the timer state separately to support APIC |
| 134 | * implementations that maintain a non-QEMU timer, e.g. inside the |
| 135 | * host kernel. This open-coded state allows us to migrate between |
| 136 | * both models. */ |
| 137 | s->timer_expiry = -1; |
| 138 | |
| 139 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { |
| 140 | return false; |
| 141 | } |
| 142 | |
| 143 | d = (current_time - s->initial_count_load_time) >> s->count_shift; |
| 144 | |
| 145 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { |
| 146 | if (!s->initial_count) { |
| 147 | return false; |
| 148 | } |
| 149 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * |
| 150 | ((uint64_t)s->initial_count + 1); |
| 151 | } else { |
| 152 | if (d >= s->initial_count) { |
| 153 | return false; |
| 154 | } |
| 155 | d = (uint64_t)s->initial_count + 1; |
| 156 | } |
| 157 | s->next_time = s->initial_count_load_time + (d << s->count_shift); |
| 158 | s->timer_expiry = s->next_time; |
| 159 | return true; |
| 160 | } |
| 161 | |
| 162 | uint32_t apic_get_current_count(APICCommonState *s) |
| 163 | { |
| 164 | int64_t d; |
| 165 | uint32_t val; |
| 166 | d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >> |
| 167 | s->count_shift; |
| 168 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { |
| 169 | /* periodic */ |
| 170 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
| 171 | } else { |
| 172 | if (d >= s->initial_count) { |
| 173 | val = 0; |
| 174 | } else { |
| 175 | val = s->initial_count - d; |
| 176 | } |
| 177 | } |
| 178 | return val; |
| 179 | } |
| 180 | |
| 181 | void apic_init_reset(APICCommonState *s) |
| 182 | { |
| 183 | APICCommonClass *info; |
| 184 | int i; |
| 185 | |
| 186 | if (!s) { |
| 187 | return; |
| 188 | } |
| 189 | s->tpr = 0; |
| 190 | s->spurious_vec = 0xff; |
| 191 | s->log_dest = 0; |
| 192 | s->dest_mode = 0xf; |
| 193 | memset(s->isr, 0, sizeof(s->isr)); |
| 194 | memset(s->tmr, 0, sizeof(s->tmr)); |
| 195 | memset(s->irr, 0, sizeof(s->irr)); |
| 196 | for (i = 0; i < APIC_LVT_NB; i++) { |
| 197 | s->lvt[i] = APIC_LVT_MASKED; |
| 198 | } |
| 199 | s->esr = 0; |
| 200 | memset(s->icr, 0, sizeof(s->icr)); |
| 201 | s->divide_conf = 0; |
| 202 | s->count_shift = 0; |
| 203 | s->initial_count = 0; |
| 204 | s->initial_count_load_time = 0; |
| 205 | s->next_time = 0; |
| 206 | s->wait_for_sipi = !cpu_is_bsp(s->cpu); |
| 207 | |
| 208 | if (s->timer) { |
| 209 | timer_del(s->timer); |
| 210 | } |
| 211 | s->timer_expiry = -1; |
| 212 | |
| 213 | info = APIC_COMMON_GET_CLASS(s); |
| 214 | if (info->reset) { |
| 215 | info->reset(s); |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | void apic_designate_bsp(APICCommonState *s, bool bsp) |
| 220 | { |
| 221 | if (s == NULL) { |
| 222 | return; |
| 223 | } |
| 224 | |
| 225 | if (bsp) { |
| 226 | s->apicbase |= MSR_IA32_APICBASE_BSP; |
| 227 | } else { |
| 228 | s->apicbase &= ~MSR_IA32_APICBASE_BSP; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | static void apic_reset_common(DeviceState *dev) |
| 233 | { |
| 234 | APICCommonState *s = APIC_COMMON(dev); |
| 235 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 236 | uint32_t bsp; |
| 237 | |
| 238 | bsp = s->apicbase & MSR_IA32_APICBASE_BSP; |
| 239 | s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; |
| 240 | s->id = s->initial_apic_id; |
| 241 | |
| 242 | kvm_reset_irq_delivered(); |
| 243 | |
| 244 | s->vapic_paddr = 0; |
| 245 | info->vapic_base_update(s); |
| 246 | |
| 247 | apic_init_reset(s); |
| 248 | } |
| 249 | |
| 250 | static const VMStateDescription vmstate_apic_common; |
| 251 | |
| 252 | static void apic_common_realize(DeviceState *dev, Error **errp) |
| 253 | { |
| 254 | ERRP_GUARD(); |
| 255 | APICCommonState *s = APIC_COMMON(dev); |
| 256 | APICCommonClass *info; |
| 257 | static DeviceState *vapic; |
| 258 | uint32_t instance_id = s->initial_apic_id; |
| 259 | |
| 260 | if (!s->cpu) { |
| 261 | error_setg(errp, "APIC is not attached to a CPU"); |
| 262 | return; |
| 263 | } |
| 264 | |
| 265 | if (s->initial_apic_id >= 255 && |
| 266 | !cpu_has_x2apic_feature(&s->cpu->env)) { |
| 267 | error_setg(errp, "APIC ID %d requires x2APIC feature in CPU", |
| 268 | s->initial_apic_id); |
| 269 | error_append_hint(errp, "Try x2apic=on in -cpu.\n"); |
| 270 | return; |
| 271 | } |
| 272 | |
| 273 | /* Normally initial APIC ID should be no more than hundreds */ |
| 274 | assert(instance_id != VMSTATE_INSTANCE_ID_ANY); |
| 275 | |
| 276 | info = APIC_COMMON_GET_CLASS(s); |
| 277 | info->realize(dev, errp); |
| 278 | if (*errp) { |
| 279 | return; |
| 280 | } |
| 281 | |
| 282 | /* Note: We need at least 1M to map the VAPIC option ROM */ |
| 283 | if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && |
| 284 | current_machine->ram_size >= 1024 * 1024) { |
| 285 | vapic = sysbus_create_simple("kvmvapic", -1, NULL); |
| 286 | } |
| 287 | s->vapic = vapic; |
| 288 | if (apic_report_tpr_access && info->enable_tpr_reporting) { |
| 289 | info->enable_tpr_reporting(s, true); |
| 290 | } |
| 291 | |
| 292 | vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, |
| 293 | s, -1, 0, NULL); |
| 294 | |
| 295 | /* APIC LDR in x2APIC mode */ |
| 296 | s->extended_log_dest = ((s->initial_apic_id >> 4) << 16) | |
| 297 | (1 << (s->initial_apic_id & 0xf)); |
| 298 | } |
| 299 | |
| 300 | static void apic_common_unrealize(DeviceState *dev) |
| 301 | { |
| 302 | APICCommonState *s = APIC_COMMON(dev); |
| 303 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 304 | |
| 305 | vmstate_unregister(NULL, &vmstate_apic_common, s); |
| 306 | info->unrealize(dev); |
| 307 | |
| 308 | if (apic_report_tpr_access && info->enable_tpr_reporting) { |
| 309 | info->enable_tpr_reporting(s, false); |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | static int apic_pre_load(void *opaque) |
| 314 | { |
| 315 | APICCommonState *s = APIC_COMMON(opaque); |
| 316 | |
| 317 | /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 |
| 318 | * so that's what apic_common_sipi_needed checks for. Reset to |
| 319 | * the value that is assumed when the apic_sipi subsection is |
| 320 | * absent. |
| 321 | */ |
| 322 | s->wait_for_sipi = 0; |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static int apic_dispatch_pre_save(void *opaque) |
| 327 | { |
| 328 | APICCommonState *s = APIC_COMMON(opaque); |
| 329 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 330 | |
| 331 | if (info->pre_save) { |
| 332 | info->pre_save(s); |
| 333 | } |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | static int apic_dispatch_post_load(void *opaque, int version_id) |
| 339 | { |
| 340 | APICCommonState *s = APIC_COMMON(opaque); |
| 341 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
| 342 | |
| 343 | if (info->post_load) { |
| 344 | info->post_load(s); |
| 345 | } |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | static bool apic_common_sipi_needed(void *opaque) |
| 350 | { |
| 351 | APICCommonState *s = APIC_COMMON(opaque); |
| 352 | return s->wait_for_sipi != 0; |
| 353 | } |
| 354 | |
| 355 | static const VMStateDescription vmstate_apic_common_sipi = { |
| 356 | .name = "apic_sipi", |
| 357 | .version_id = 1, |
| 358 | .minimum_version_id = 1, |
| 359 | .needed = apic_common_sipi_needed, |
| 360 | .fields = (const VMStateField[]) { |
| 361 | VMSTATE_INT32(sipi_vector, APICCommonState), |
| 362 | VMSTATE_INT32(wait_for_sipi, APICCommonState), |
| 363 | VMSTATE_END_OF_LIST() |
| 364 | } |
| 365 | }; |
| 366 | |
| 367 | static const VMStateDescription vmstate_apic_common = { |
| 368 | .name = "apic", |
| 369 | .version_id = 3, |
| 370 | .minimum_version_id = 3, |
| 371 | .pre_load = apic_pre_load, |
| 372 | .pre_save = apic_dispatch_pre_save, |
| 373 | .post_load = apic_dispatch_post_load, |
| 374 | .priority = MIG_PRI_APIC, |
| 375 | .fields = (const VMStateField[]) { |
| 376 | VMSTATE_UINT32(apicbase, APICCommonState), |
| 377 | VMSTATE_UINT8(id, APICCommonState), |
| 378 | VMSTATE_UINT8(arb_id, APICCommonState), |
| 379 | VMSTATE_UINT8(tpr, APICCommonState), |
| 380 | VMSTATE_UINT32(spurious_vec, APICCommonState), |
| 381 | VMSTATE_UINT8(log_dest, APICCommonState), |
| 382 | VMSTATE_UINT8(dest_mode, APICCommonState), |
| 383 | VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), |
| 384 | VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), |
| 385 | VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), |
| 386 | VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), |
| 387 | VMSTATE_UINT32(esr, APICCommonState), |
| 388 | VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), |
| 389 | VMSTATE_UINT32(divide_conf, APICCommonState), |
| 390 | VMSTATE_INT32(count_shift, APICCommonState), |
| 391 | VMSTATE_UINT32(initial_count, APICCommonState), |
| 392 | VMSTATE_INT64(initial_count_load_time, APICCommonState), |
| 393 | VMSTATE_INT64(next_time, APICCommonState), |
| 394 | VMSTATE_INT64(timer_expiry, |
| 395 | APICCommonState), /* open-coded timer state */ |
| 396 | VMSTATE_END_OF_LIST() |
| 397 | }, |
| 398 | .subsections = (const VMStateDescription * const []) { |
| 399 | &vmstate_apic_common_sipi, |
| 400 | NULL |
| 401 | } |
| 402 | }; |
| 403 | |
| 404 | static const Property apic_properties_common[] = { |
| 405 | DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), |
| 406 | DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, |
| 407 | true), |
| 408 | }; |
| 409 | |
| 410 | static void apic_common_get_id(Object *obj, Visitor *v, const char *name, |
| 411 | void *opaque, Error **errp) |
| 412 | { |
| 413 | APICCommonState *s = APIC_COMMON(obj); |
| 414 | uint32_t value; |
| 415 | |
| 416 | value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id; |
| 417 | visit_type_uint32(v, name, &value, errp); |
| 418 | } |
| 419 | |
| 420 | static void apic_common_set_id(Object *obj, Visitor *v, const char *name, |
| 421 | void *opaque, Error **errp) |
| 422 | { |
| 423 | APICCommonState *s = APIC_COMMON(obj); |
| 424 | DeviceState *dev = DEVICE(obj); |
| 425 | uint32_t value; |
| 426 | |
| 427 | if (qdev_is_realized(dev)) { |
| 428 | qdev_prop_set_after_realize(dev, name, errp); |
| 429 | return; |
| 430 | } |
| 431 | |
| 432 | if (!visit_type_uint32(v, name, &value, errp)) { |
| 433 | return; |
| 434 | } |
| 435 | |
| 436 | s->initial_apic_id = value; |
| 437 | s->id = (uint8_t)value; |
| 438 | } |
| 439 | |
| 440 | static void apic_common_initfn(Object *obj) |
| 441 | { |
| 442 | APICCommonState *s = APIC_COMMON(obj); |
| 443 | |
| 444 | s->id = s->initial_apic_id = -1; |
| 445 | object_property_add(obj, "id", "uint32", |
| 446 | apic_common_get_id, |
| 447 | apic_common_set_id, NULL, NULL); |
| 448 | } |
| 449 | |
| 450 | static void apic_common_class_init(ObjectClass *klass, const void *data) |
| 451 | { |
| 452 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 453 | |
| 454 | device_class_set_legacy_reset(dc, apic_reset_common); |
| 455 | device_class_set_props(dc, apic_properties_common); |
| 456 | dc->realize = apic_common_realize; |
| 457 | dc->unrealize = apic_common_unrealize; |
| 458 | /* |
| 459 | * Reason: APIC and CPU need to be wired up by |
| 460 | * x86_cpu_apic_create() |
| 461 | */ |
| 462 | dc->user_creatable = false; |
| 463 | } |
| 464 | |
| 465 | static const TypeInfo apic_common_type = { |
| 466 | .name = TYPE_APIC_COMMON, |
| 467 | .parent = TYPE_DEVICE, |
| 468 | .instance_size = sizeof(APICCommonState), |
| 469 | .instance_init = apic_common_initfn, |
| 470 | .class_size = sizeof(APICCommonClass), |
| 471 | .class_init = apic_common_class_init, |
| 472 | .abstract = true, |
| 473 | }; |
| 474 | |
| 475 | static void apic_common_register_types(void) |
| 476 | { |
| 477 | type_register_static(&apic_common_type); |
| 478 | } |
| 479 | |
| 480 | type_init(apic_common_register_types) |