| 1 | /* |
| 2 | * ARM GICv3 support - common bits of emulated and KVM kernel model |
| 3 | * |
| 4 | * Copyright (c) 2012 Linaro Limited |
| 5 | * Copyright (c) 2015 Huawei. |
| 6 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. |
| 7 | * Written by Peter Maydell |
| 8 | * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation, either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along |
| 21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 22 | */ |
| 23 | |
| 24 | #include "qemu/osdep.h" |
| 25 | #include "qapi/error.h" |
| 26 | #include "qemu/module.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "hw/core/cpu.h" |
| 29 | #include "hw/intc/arm_gicv3_common.h" |
| 30 | #include "hw/core/qdev-properties.h" |
| 31 | #include "migration/vmstate.h" |
| 32 | #include "gicv3_internal.h" |
| 33 | #include "hw/arm/linux-boot-if.h" |
| 34 | #include "system/kvm.h" |
| 35 | #include "system/whpx.h" |
| 36 | #include "system/hvf.h" |
| 37 | |
| 38 | |
| 39 | static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) |
| 40 | { |
| 41 | if (cs->gicd_no_migration_shift_bug) { |
| 42 | return; |
| 43 | } |
| 44 | |
| 45 | /* Older versions of QEMU had a bug in the handling of state save/restore |
| 46 | * to the KVM GICv3: they got the offset in the bitmap arrays wrong, |
| 47 | * so that instead of the data for external interrupts 32 and up |
| 48 | * starting at bit position 32 in the bitmap, it started at bit |
| 49 | * position 64. If we're receiving data from a QEMU with that bug, |
| 50 | * we must move the data down into the right place. |
| 51 | */ |
| 52 | memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8, |
| 53 | sizeof(cs->group) - GIC_INTERNAL / 8); |
| 54 | memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8, |
| 55 | sizeof(cs->grpmod) - GIC_INTERNAL / 8); |
| 56 | memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8, |
| 57 | sizeof(cs->enabled) - GIC_INTERNAL / 8); |
| 58 | memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8, |
| 59 | sizeof(cs->pending) - GIC_INTERNAL / 8); |
| 60 | memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8, |
| 61 | sizeof(cs->active) - GIC_INTERNAL / 8); |
| 62 | memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8, |
| 63 | sizeof(cs->edge_trigger) - GIC_INTERNAL / 8); |
| 64 | |
| 65 | /* |
| 66 | * While this new version QEMU doesn't have this kind of bug as we fix it, |
| 67 | * so it needs to set the flag to true to indicate that and it's necessary |
| 68 | * for next migration to work from this new version QEMU. |
| 69 | */ |
| 70 | cs->gicd_no_migration_shift_bug = true; |
| 71 | } |
| 72 | |
| 73 | static int gicv3_pre_save(void *opaque) |
| 74 | { |
| 75 | GICv3State *s = (GICv3State *)opaque; |
| 76 | ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); |
| 77 | |
| 78 | if (c->pre_save) { |
| 79 | c->pre_save(s); |
| 80 | } |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | static int gicv3_post_load(void *opaque, int version_id) |
| 86 | { |
| 87 | GICv3State *s = (GICv3State *)opaque; |
| 88 | ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); |
| 89 | |
| 90 | gicv3_gicd_no_migration_shift_bug_post_load(s); |
| 91 | |
| 92 | if (c->post_load) { |
| 93 | c->post_load(s); |
| 94 | } |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static bool virt_state_needed(void *opaque) |
| 99 | { |
| 100 | GICv3CPUState *cs = opaque; |
| 101 | |
| 102 | return cs->num_list_regs != 0; |
| 103 | } |
| 104 | |
| 105 | static const VMStateDescription vmstate_gicv3_cpu_virt = { |
| 106 | .name = "arm_gicv3_cpu/virt", |
| 107 | .version_id = 1, |
| 108 | .minimum_version_id = 1, |
| 109 | .needed = virt_state_needed, |
| 110 | .fields = (const VMStateField[]) { |
| 111 | VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4), |
| 112 | VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState), |
| 113 | VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX), |
| 114 | VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState), |
| 115 | VMSTATE_END_OF_LIST() |
| 116 | } |
| 117 | }; |
| 118 | |
| 119 | static int vmstate_gicv3_cpu_pre_load(void *opaque) |
| 120 | { |
| 121 | GICv3CPUState *cs = opaque; |
| 122 | |
| 123 | /* |
| 124 | * If the sre_el1 subsection is not transferred this |
| 125 | * means SRE_EL1 is 0x7 (which might not be the same as |
| 126 | * our reset value). |
| 127 | */ |
| 128 | cs->icc_sre_el1 = 0x7; |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | static bool icc_sre_el1_reg_needed(void *opaque) |
| 133 | { |
| 134 | GICv3CPUState *cs = opaque; |
| 135 | |
| 136 | return cs->icc_sre_el1 != 7; |
| 137 | } |
| 138 | |
| 139 | const VMStateDescription vmstate_gicv3_cpu_sre_el1 = { |
| 140 | .name = "arm_gicv3_cpu/sre_el1", |
| 141 | .version_id = 1, |
| 142 | .minimum_version_id = 1, |
| 143 | .needed = icc_sre_el1_reg_needed, |
| 144 | .fields = (const VMStateField[]) { |
| 145 | VMSTATE_UINT64(icc_sre_el1, GICv3CPUState), |
| 146 | VMSTATE_END_OF_LIST() |
| 147 | } |
| 148 | }; |
| 149 | |
| 150 | static bool gicv4_needed(void *opaque) |
| 151 | { |
| 152 | GICv3CPUState *cs = opaque; |
| 153 | |
| 154 | return cs->gic->revision > 3; |
| 155 | } |
| 156 | |
| 157 | const VMStateDescription vmstate_gicv3_gicv4 = { |
| 158 | .name = "arm_gicv3_cpu/gicv4", |
| 159 | .version_id = 1, |
| 160 | .minimum_version_id = 1, |
| 161 | .needed = gicv4_needed, |
| 162 | .fields = (const VMStateField[]) { |
| 163 | VMSTATE_UINT64(gicr_vpropbaser, GICv3CPUState), |
| 164 | VMSTATE_UINT64(gicr_vpendbaser, GICv3CPUState), |
| 165 | VMSTATE_END_OF_LIST() |
| 166 | } |
| 167 | }; |
| 168 | |
| 169 | static bool gicv3_cpu_nmi_needed(void *opaque) |
| 170 | { |
| 171 | GICv3CPUState *cs = opaque; |
| 172 | |
| 173 | return cs->gic->nmi_support; |
| 174 | } |
| 175 | |
| 176 | static const VMStateDescription vmstate_gicv3_cpu_nmi = { |
| 177 | .name = "arm_gicv3_cpu/nmi", |
| 178 | .version_id = 1, |
| 179 | .minimum_version_id = 1, |
| 180 | .needed = gicv3_cpu_nmi_needed, |
| 181 | .fields = (const VMStateField[]) { |
| 182 | VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), |
| 183 | VMSTATE_END_OF_LIST() |
| 184 | } |
| 185 | }; |
| 186 | |
| 187 | static const VMStateDescription vmstate_gicv3_cpu = { |
| 188 | .name = "arm_gicv3_cpu", |
| 189 | .version_id = 1, |
| 190 | .minimum_version_id = 1, |
| 191 | .pre_load = vmstate_gicv3_cpu_pre_load, |
| 192 | .fields = (const VMStateField[]) { |
| 193 | VMSTATE_UINT32(level, GICv3CPUState), |
| 194 | VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), |
| 195 | VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2), |
| 196 | VMSTATE_UINT32(gicr_waker, GICv3CPUState), |
| 197 | VMSTATE_UINT64(gicr_propbaser, GICv3CPUState), |
| 198 | VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState), |
| 199 | VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState), |
| 200 | VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState), |
| 201 | VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState), |
| 202 | VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState), |
| 203 | VMSTATE_UINT32(edge_trigger, GICv3CPUState), |
| 204 | VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), |
| 205 | VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), |
| 206 | VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), |
| 207 | VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), |
| 208 | VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), |
| 209 | VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3), |
| 210 | VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), |
| 211 | VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), |
| 212 | VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), |
| 213 | VMSTATE_END_OF_LIST() |
| 214 | }, |
| 215 | .subsections = (const VMStateDescription * const []) { |
| 216 | &vmstate_gicv3_cpu_virt, |
| 217 | &vmstate_gicv3_cpu_sre_el1, |
| 218 | &vmstate_gicv3_gicv4, |
| 219 | &vmstate_gicv3_cpu_nmi, |
| 220 | NULL |
| 221 | } |
| 222 | }; |
| 223 | |
| 224 | static int gicv3_pre_load(void *opaque) |
| 225 | { |
| 226 | GICv3State *cs = opaque; |
| 227 | |
| 228 | /* |
| 229 | * The gicd_no_migration_shift_bug flag is used for migration compatibility |
| 230 | * for old version QEMU which may have the GICD bmp shift bug under KVM mode. |
| 231 | * Strictly, what we want to know is whether the migration source is using |
| 232 | * KVM. Since we don't have any way to determine that, we look at whether the |
| 233 | * destination is using KVM; this is close enough because for the older QEMU |
| 234 | * versions with this bug KVM -> TCG migration didn't work anyway. If the |
| 235 | * source is a newer QEMU without this bug it will transmit the migration |
| 236 | * subsection which sets the flag to true; otherwise it will remain set to |
| 237 | * the value we select here. |
| 238 | */ |
| 239 | if (kvm_enabled()) { |
| 240 | cs->gicd_no_migration_shift_bug = false; |
| 241 | } |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static bool needed_always(void *opaque) |
| 247 | { |
| 248 | return true; |
| 249 | } |
| 250 | |
| 251 | const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = { |
| 252 | .name = "arm_gicv3/gicd_no_migration_shift_bug", |
| 253 | .version_id = 1, |
| 254 | .minimum_version_id = 1, |
| 255 | .needed = needed_always, |
| 256 | .fields = (const VMStateField[]) { |
| 257 | VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State), |
| 258 | VMSTATE_END_OF_LIST() |
| 259 | } |
| 260 | }; |
| 261 | |
| 262 | static bool gicv3_nmi_needed(void *opaque) |
| 263 | { |
| 264 | GICv3State *cs = opaque; |
| 265 | |
| 266 | return cs->nmi_support; |
| 267 | } |
| 268 | |
| 269 | const VMStateDescription vmstate_gicv3_gicd_nmi = { |
| 270 | .name = "arm_gicv3/gicd_nmi", |
| 271 | .version_id = 1, |
| 272 | .minimum_version_id = 1, |
| 273 | .needed = gicv3_nmi_needed, |
| 274 | .fields = (const VMStateField[]) { |
| 275 | VMSTATE_UINT32_ARRAY(nmi, GICv3State, GICV3_BMP_SIZE), |
| 276 | VMSTATE_END_OF_LIST() |
| 277 | } |
| 278 | }; |
| 279 | |
| 280 | static const VMStateDescription vmstate_gicv3 = { |
| 281 | .name = "arm_gicv3", |
| 282 | .version_id = 1, |
| 283 | .minimum_version_id = 1, |
| 284 | .pre_load = gicv3_pre_load, |
| 285 | .pre_save = gicv3_pre_save, |
| 286 | .post_load = gicv3_post_load, |
| 287 | .priority = MIG_PRI_GICV3, |
| 288 | .fields = (const VMStateField[]) { |
| 289 | VMSTATE_UINT32(gicd_ctlr, GICv3State), |
| 290 | VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), |
| 291 | VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE), |
| 292 | VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE), |
| 293 | VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE), |
| 294 | VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE), |
| 295 | VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE), |
| 296 | VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE), |
| 297 | VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE), |
| 298 | VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ), |
| 299 | VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ), |
| 300 | VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State, |
| 301 | DIV_ROUND_UP(GICV3_MAXIRQ, 16)), |
| 302 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, |
| 303 | vmstate_gicv3_cpu, GICv3CPUState), |
| 304 | VMSTATE_END_OF_LIST() |
| 305 | }, |
| 306 | .subsections = (const VMStateDescription * const []) { |
| 307 | &vmstate_gicv3_gicd_no_migration_shift_bug, |
| 308 | &vmstate_gicv3_gicd_nmi, |
| 309 | &vmstate_gicv3_hvf, |
| 310 | NULL |
| 311 | } |
| 312 | }; |
| 313 | |
| 314 | void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, |
| 315 | const MemoryRegionOps *ops) |
| 316 | { |
| 317 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); |
| 318 | int i; |
| 319 | int cpuidx; |
| 320 | |
| 321 | /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. |
| 322 | * GPIO array layout is thus: |
| 323 | * [0..N-1] spi |
| 324 | * [N..N+31] PPIs for CPU 0 |
| 325 | * [N+32..N+63] PPIs for CPU 1 |
| 326 | * ... |
| 327 | */ |
| 328 | i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; |
| 329 | qdev_init_gpio_in(DEVICE(s), handler, i); |
| 330 | |
| 331 | for (i = 0; i < s->num_cpu; i++) { |
| 332 | sysbus_init_irq(sbd, &s->cpu[i].parent_irq); |
| 333 | } |
| 334 | for (i = 0; i < s->num_cpu; i++) { |
| 335 | sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); |
| 336 | } |
| 337 | for (i = 0; i < s->num_cpu; i++) { |
| 338 | sysbus_init_irq(sbd, &s->cpu[i].parent_virq); |
| 339 | } |
| 340 | for (i = 0; i < s->num_cpu; i++) { |
| 341 | sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); |
| 342 | } |
| 343 | for (i = 0; i < s->num_cpu; i++) { |
| 344 | sysbus_init_irq(sbd, &s->cpu[i].parent_nmi); |
| 345 | } |
| 346 | for (i = 0; i < s->num_cpu; i++) { |
| 347 | sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi); |
| 348 | } |
| 349 | |
| 350 | memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, |
| 351 | "gicv3_dist", 0x10000); |
| 352 | sysbus_init_mmio(sbd, &s->iomem_dist); |
| 353 | |
| 354 | s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions); |
| 355 | cpuidx = 0; |
| 356 | for (i = 0; i < s->nb_redist_regions; i++) { |
| 357 | char *name = g_strdup_printf("gicv3_redist_region[%d]", i); |
| 358 | GICv3RedistRegion *region = &s->redist_regions[i]; |
| 359 | |
| 360 | region->gic = s; |
| 361 | region->cpuidx = cpuidx; |
| 362 | cpuidx += s->redist_region_count[i]; |
| 363 | |
| 364 | memory_region_init_io(®ion->iomem, OBJECT(s), |
| 365 | ops ? &ops[1] : NULL, region, name, |
| 366 | s->redist_region_count[i] * gicv3_redist_size(s)); |
| 367 | sysbus_init_mmio(sbd, ®ion->iomem); |
| 368 | g_free(name); |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) |
| 373 | { |
| 374 | GICv3State *s = ARM_GICV3_COMMON(dev); |
| 375 | int i, rdist_capacity, cpuidx; |
| 376 | |
| 377 | /* |
| 378 | * This GIC device supports only revisions 3 and 4. The GICv1/v2 |
| 379 | * is a separate device. |
| 380 | * Note that subclasses of this device may impose further restrictions |
| 381 | * on the GIC revision: notably, the in-kernel KVM GIC doesn't |
| 382 | * support GICv4. |
| 383 | */ |
| 384 | if (s->revision != 3 && s->revision != 4) { |
| 385 | error_setg(errp, "unsupported GIC revision %d", s->revision); |
| 386 | return; |
| 387 | } |
| 388 | |
| 389 | if (s->num_irq > GICV3_MAXIRQ) { |
| 390 | error_setg(errp, |
| 391 | "requested %u interrupt lines exceeds GIC maximum %d", |
| 392 | s->num_irq, GICV3_MAXIRQ); |
| 393 | return; |
| 394 | } |
| 395 | if (s->num_irq < GIC_INTERNAL) { |
| 396 | error_setg(errp, |
| 397 | "requested %u interrupt lines is below GIC minimum %d", |
| 398 | s->num_irq, GIC_INTERNAL); |
| 399 | return; |
| 400 | } |
| 401 | if (s->num_cpu == 0) { |
| 402 | error_setg(errp, "num-cpu must be at least 1"); |
| 403 | return; |
| 404 | } |
| 405 | |
| 406 | /* ITLinesNumber is represented as (N / 32) - 1, so this is an |
| 407 | * implementation imposed restriction, not an architectural one, |
| 408 | * so we don't have to deal with bitfields where only some of the |
| 409 | * bits in a 32-bit word should be valid. |
| 410 | */ |
| 411 | if (s->num_irq % 32) { |
| 412 | error_setg(errp, |
| 413 | "%d interrupt lines unsupported: not divisible by 32", |
| 414 | s->num_irq); |
| 415 | return; |
| 416 | } |
| 417 | |
| 418 | if (s->lpi_enable && !s->dma) { |
| 419 | error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set"); |
| 420 | return; |
| 421 | } |
| 422 | |
| 423 | rdist_capacity = 0; |
| 424 | for (i = 0; i < s->nb_redist_regions; i++) { |
| 425 | rdist_capacity += s->redist_region_count[i]; |
| 426 | } |
| 427 | if (rdist_capacity != s->num_cpu) { |
| 428 | error_setg(errp, "Capacity of the redist regions(%d) " |
| 429 | "does not match the number of vcpus(%d)", |
| 430 | rdist_capacity, s->num_cpu); |
| 431 | return; |
| 432 | } |
| 433 | |
| 434 | if (s->lpi_enable) { |
| 435 | address_space_init(&s->dma_as, s->dma, |
| 436 | "gicv3-its-sysmem"); |
| 437 | } |
| 438 | |
| 439 | s->cpu = g_new0(GICv3CPUState, s->num_cpu); |
| 440 | |
| 441 | for (i = 0; i < s->num_cpu; i++) { |
| 442 | CPUState *cpu = qemu_get_cpu(s->first_cpu_idx + i); |
| 443 | uint64_t cpu_affid; |
| 444 | |
| 445 | s->cpu[i].cpu = cpu; |
| 446 | s->cpu[i].gic = s; |
| 447 | /* Store GICv3CPUState in CPUARMState gicv3state pointer */ |
| 448 | gicv3_set_gicv3state(cpu, &s->cpu[i]); |
| 449 | |
| 450 | /* Pre-construct the GICR_TYPER: |
| 451 | * For our implementation: |
| 452 | * Top 32 bits are the affinity value of the associated CPU |
| 453 | * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table) |
| 454 | * Processor_Number == CPU index starting from 0 |
| 455 | * DPGS == 0 (GICR_CTLR.DPG* not supported) |
| 456 | * Last == 1 if this is the last redistributor in a series of |
| 457 | * contiguous redistributor pages |
| 458 | * DirectLPI == 0 (direct injection of LPIs not supported) |
| 459 | * VLPIS == 1 if vLPIs supported (GICv4 and up) |
| 460 | * PLPIS == 1 if LPIs supported |
| 461 | */ |
| 462 | cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL); |
| 463 | |
| 464 | /* The CPU mp-affinity property is in MPIDR register format; squash |
| 465 | * the affinity bytes into 32 bits as the GICR_TYPER has them. |
| 466 | */ |
| 467 | cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) | |
| 468 | (cpu_affid & 0xFFFFFF); |
| 469 | s->cpu[i].gicr_typer = (cpu_affid << 32) | |
| 470 | (1 << 24) | |
| 471 | (i << 8); |
| 472 | |
| 473 | if (s->lpi_enable) { |
| 474 | s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS; |
| 475 | if (s->revision > 3) { |
| 476 | s->cpu[i].gicr_typer |= GICR_TYPER_VLPIS; |
| 477 | } |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | /* |
| 482 | * Now go through and set GICR_TYPER.Last for the final |
| 483 | * redistributor in each region. |
| 484 | */ |
| 485 | cpuidx = 0; |
| 486 | for (i = 0; i < s->nb_redist_regions; i++) { |
| 487 | cpuidx += s->redist_region_count[i]; |
| 488 | s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST; |
| 489 | } |
| 490 | |
| 491 | s->itslist = g_ptr_array_new(); |
| 492 | } |
| 493 | |
| 494 | static void arm_gicv3_common_reset_hold(Object *obj, ResetType type) |
| 495 | { |
| 496 | GICv3State *s = ARM_GICV3_COMMON(obj); |
| 497 | int i; |
| 498 | |
| 499 | for (i = 0; i < s->num_cpu; i++) { |
| 500 | GICv3CPUState *cs = &s->cpu[i]; |
| 501 | |
| 502 | cs->level = 0; |
| 503 | cs->gicr_ctlr = 0; |
| 504 | if (s->lpi_enable) { |
| 505 | /* Our implementation supports clearing GICR_CTLR.EnableLPIs */ |
| 506 | cs->gicr_ctlr |= GICR_CTLR_CES; |
| 507 | } |
| 508 | cs->gicr_statusr[GICV3_S] = 0; |
| 509 | cs->gicr_statusr[GICV3_NS] = 0; |
| 510 | cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; |
| 511 | cs->gicr_propbaser = 0; |
| 512 | cs->gicr_pendbaser = 0; |
| 513 | cs->gicr_vpropbaser = 0; |
| 514 | cs->gicr_vpendbaser = 0; |
| 515 | /* If we're resetting a TZ-aware GIC as if secure firmware |
| 516 | * had set it up ready to start a kernel in non-secure, we |
| 517 | * need to set interrupts to group 1 so the kernel can use them. |
| 518 | * Otherwise they reset to group 0 like the hardware. |
| 519 | */ |
| 520 | if (s->irq_reset_nonsecure) { |
| 521 | cs->gicr_igroupr0 = 0xffffffff; |
| 522 | } else { |
| 523 | cs->gicr_igroupr0 = 0; |
| 524 | } |
| 525 | |
| 526 | cs->gicr_ienabler0 = 0; |
| 527 | cs->gicr_ipendr0 = 0; |
| 528 | cs->gicr_iactiver0 = 0; |
| 529 | cs->edge_trigger = 0xffff; |
| 530 | cs->gicr_igrpmodr0 = 0; |
| 531 | cs->gicr_nsacr = 0; |
| 532 | memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); |
| 533 | |
| 534 | cs->hppi.prio = 0xff; |
| 535 | cs->hppi.nmi = false; |
| 536 | cs->hpplpi.prio = 0xff; |
| 537 | cs->hpplpi.nmi = false; |
| 538 | cs->hppvlpi.prio = 0xff; |
| 539 | cs->hppvlpi.nmi = false; |
| 540 | |
| 541 | /* State in the CPU interface must *not* be reset here, because it |
| 542 | * is part of the CPU's reset domain, not the GIC device's. |
| 543 | */ |
| 544 | } |
| 545 | |
| 546 | /* For our implementation affinity routing is always enabled */ |
| 547 | if (s->security_extn) { |
| 548 | s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS; |
| 549 | } else { |
| 550 | s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE; |
| 551 | } |
| 552 | |
| 553 | s->gicd_statusr[GICV3_S] = 0; |
| 554 | s->gicd_statusr[GICV3_NS] = 0; |
| 555 | |
| 556 | memset(s->group, 0, sizeof(s->group)); |
| 557 | memset(s->grpmod, 0, sizeof(s->grpmod)); |
| 558 | memset(s->enabled, 0, sizeof(s->enabled)); |
| 559 | memset(s->pending, 0, sizeof(s->pending)); |
| 560 | memset(s->active, 0, sizeof(s->active)); |
| 561 | memset(s->level, 0, sizeof(s->level)); |
| 562 | memset(s->edge_trigger, 0, sizeof(s->edge_trigger)); |
| 563 | memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority)); |
| 564 | memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter)); |
| 565 | memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr)); |
| 566 | /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must |
| 567 | * write these to get sane behaviour and we need not populate the |
| 568 | * pointer cache here; however having the cache be different for |
| 569 | * "happened to be 0 from reset" and "guest wrote 0" would be |
| 570 | * too confusing. |
| 571 | */ |
| 572 | gicv3_cache_all_target_cpustates(s); |
| 573 | |
| 574 | if (s->irq_reset_nonsecure) { |
| 575 | /* If we're resetting a TZ-aware GIC as if secure firmware |
| 576 | * had set it up ready to start a kernel in non-secure, we |
| 577 | * need to set interrupts to group 1 so the kernel can use them. |
| 578 | * Otherwise they reset to group 0 like the hardware. |
| 579 | */ |
| 580 | for (i = GIC_INTERNAL; i < s->num_irq; i++) { |
| 581 | gicv3_gicd_group_set(s, i); |
| 582 | } |
| 583 | } |
| 584 | s->gicd_no_migration_shift_bug = true; |
| 585 | } |
| 586 | |
| 587 | static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, |
| 588 | bool secure_boot) |
| 589 | { |
| 590 | GICv3State *s = ARM_GICV3_COMMON(obj); |
| 591 | |
| 592 | if (s->security_extn && !secure_boot) { |
| 593 | /* We're directly booting a kernel into NonSecure. If this GIC |
| 594 | * implements the security extensions then we must configure it |
| 595 | * to have all the interrupts be NonSecure (this is a job that |
| 596 | * is done by the Secure boot firmware in real hardware, and in |
| 597 | * this mode QEMU is acting as a minimalist firmware-and-bootloader |
| 598 | * equivalent). |
| 599 | */ |
| 600 | s->irq_reset_nonsecure = true; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | static const Property arm_gicv3_common_properties[] = { |
| 605 | DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), |
| 606 | DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), |
| 607 | DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), |
| 608 | DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), |
| 609 | DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0), |
| 610 | DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), |
| 611 | DEFINE_PROP_UINT32("maintenance-interrupt-id", GICv3State, maint_irq, 0), |
| 612 | /* |
| 613 | * Compatibility property: force 8 bits of physical priority, even |
| 614 | * if the CPU being emulated should have fewer. |
| 615 | */ |
| 616 | DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State, force_8bit_prio, 0), |
| 617 | DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, |
| 618 | redist_region_count, qdev_prop_uint32, uint32_t), |
| 619 | DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, |
| 620 | MemoryRegion *), |
| 621 | DEFINE_PROP_UINT32("first-cpu-index", GICv3State, first_cpu_idx, 0), |
| 622 | }; |
| 623 | |
| 624 | static void arm_gicv3_common_class_init(ObjectClass *klass, const void *data) |
| 625 | { |
| 626 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 627 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 628 | ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); |
| 629 | |
| 630 | rc->phases.hold = arm_gicv3_common_reset_hold; |
| 631 | dc->realize = arm_gicv3_common_realize; |
| 632 | device_class_set_props(dc, arm_gicv3_common_properties); |
| 633 | dc->vmsd = &vmstate_gicv3; |
| 634 | albifc->arm_linux_init = arm_gic_common_linux_init; |
| 635 | } |
| 636 | |
| 637 | static const TypeInfo arm_gicv3_common_type = { |
| 638 | .name = TYPE_ARM_GICV3_COMMON, |
| 639 | .parent = TYPE_SYS_BUS_DEVICE, |
| 640 | .instance_size = sizeof(GICv3State), |
| 641 | .class_size = sizeof(ARMGICv3CommonClass), |
| 642 | .class_init = arm_gicv3_common_class_init, |
| 643 | .abstract = true, |
| 644 | .interfaces = (const InterfaceInfo[]) { |
| 645 | { TYPE_ARM_LINUX_BOOT_IF }, |
| 646 | { }, |
| 647 | }, |
| 648 | }; |
| 649 | |
| 650 | static void register_types(void) |
| 651 | { |
| 652 | type_register_static(&arm_gicv3_common_type); |
| 653 | } |
| 654 | |
| 655 | type_init(register_types) |
| 656 | |
| 657 | const char *gicv3_class_name(void) |
| 658 | { |
| 659 | if (kvm_irqchip_in_kernel()) { |
| 660 | return "kvm-arm-gicv3"; |
| 661 | } else if (whpx_enabled()) { |
| 662 | return TYPE_WHPX_GICV3; |
| 663 | } else if (hvf_enabled() && hvf_irqchip_in_kernel()) { |
| 664 | return TYPE_HVF_GICV3; |
| 665 | } else { |
| 666 | if (kvm_enabled()) { |
| 667 | error_report("Userspace GICv3 is not supported with KVM"); |
| 668 | exit(1); |
| 669 | } |
| 670 | return "arm-gicv3"; |
| 671 | } |
| 672 | } |