| 1 | /* |
| 2 | * ARM GICv3 emulation: Distributor |
| 3 | * |
| 4 | * Copyright (c) 2015 Huawei. |
| 5 | * Copyright (c) 2016 Linaro Limited. |
| 6 | * Written by Shlomo Pongratz, Peter Maydell |
| 7 | * |
| 8 | * This code is licensed under the GPL, version 2 or (at your option) |
| 9 | * any later version. |
| 10 | */ |
| 11 | |
| 12 | #include "qemu/osdep.h" |
| 13 | #include "qemu/log.h" |
| 14 | #include "trace.h" |
| 15 | #include "gicv3_internal.h" |
| 16 | |
| 17 | /* The GICD_NSACR registers contain a two bit field for each interrupt which |
| 18 | * allows the guest to give NonSecure code access to registers controlling |
| 19 | * Secure interrupts: |
| 20 | * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI) |
| 21 | * 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR |
| 22 | * 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER, |
| 23 | * and w/o to CLRSPI_NSR |
| 24 | * 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR |
| 25 | * |
| 26 | * Given a (multiple-of-32) interrupt number, these mask functions return |
| 27 | * a mask word where each bit is 1 if the NSACR settings permit access |
| 28 | * to the interrupt. The mask returned can then be ORed with the GICD_GROUP |
| 29 | * word for this set of interrupts to give an overall mask. |
| 30 | */ |
| 31 | |
| 32 | typedef uint32_t maskfn(GICv3State *s, int irq); |
| 33 | |
| 34 | static uint32_t mask_nsacr_ge1(GICv3State *s, int irq) |
| 35 | { |
| 36 | /* Return a mask where each bit is set if the NSACR field is >= 1 */ |
| 37 | uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; |
| 38 | |
| 39 | raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; |
| 40 | raw_nsacr = (raw_nsacr >> 1) | raw_nsacr; |
| 41 | return half_unshuffle64(raw_nsacr); |
| 42 | } |
| 43 | |
| 44 | static uint32_t mask_nsacr_ge2(GICv3State *s, int irq) |
| 45 | { |
| 46 | /* Return a mask where each bit is set if the NSACR field is >= 2 */ |
| 47 | uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; |
| 48 | |
| 49 | raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; |
| 50 | raw_nsacr = raw_nsacr >> 1; |
| 51 | return half_unshuffle64(raw_nsacr); |
| 52 | } |
| 53 | |
| 54 | /* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register, |
| 55 | * but it would be implemented using: |
| 56 | * raw_nsacr = (raw_nsacr >> 1) & raw_nsacr; |
| 57 | */ |
| 58 | |
| 59 | static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs, |
| 60 | maskfn *maskfn, int irq) |
| 61 | { |
| 62 | /* Return a 32-bit mask which should be applied for this set of 32 |
| 63 | * interrupts; each bit is 1 if access is permitted by the |
| 64 | * combination of attrs.secure, GICD_GROUPR and GICD_NSACR. |
| 65 | */ |
| 66 | uint32_t mask; |
| 67 | |
| 68 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 69 | /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI |
| 70 | * unless the NSACR bits permit access. |
| 71 | */ |
| 72 | mask = *gic_bmp_ptr32(s->group, irq); |
| 73 | if (maskfn) { |
| 74 | mask |= maskfn(s, irq); |
| 75 | } |
| 76 | return mask; |
| 77 | } |
| 78 | return 0xFFFFFFFFU; |
| 79 | } |
| 80 | |
| 81 | static int gicd_ns_access(GICv3State *s, int irq) |
| 82 | { |
| 83 | /* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the |
| 84 | * specified interrupt. |
| 85 | */ |
| 86 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 87 | return 0; |
| 88 | } |
| 89 | return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); |
| 90 | } |
| 91 | |
| 92 | static void gicd_write_bitmap_reg(GICv3State *s, MemTxAttrs attrs, |
| 93 | uint32_t *bmp, maskfn *maskfn, |
| 94 | int offset, uint32_t val) |
| 95 | { |
| 96 | /* |
| 97 | * Helper routine to implement writing to a "set" register |
| 98 | * (GICD_INMIR, etc). |
| 99 | * Semantics implemented here: |
| 100 | * RAZ/WI for SGIs, PPIs, unimplemented IRQs |
| 101 | * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. |
| 102 | * offset should be the offset in bytes of the register from the start |
| 103 | * of its group. |
| 104 | */ |
| 105 | int irq = offset * 8; |
| 106 | |
| 107 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 108 | return; |
| 109 | } |
| 110 | val &= mask_group_and_nsacr(s, attrs, maskfn, irq); |
| 111 | *gic_bmp_ptr32(bmp, irq) = val; |
| 112 | gicv3_update(s, irq, 32); |
| 113 | } |
| 114 | |
| 115 | static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, |
| 116 | uint32_t *bmp, |
| 117 | maskfn *maskfn, |
| 118 | int offset, uint32_t val) |
| 119 | { |
| 120 | /* Helper routine to implement writing to a "set-bitmap" register |
| 121 | * (GICD_ISENABLER, GICD_ISPENDR, etc). |
| 122 | * Semantics implemented here: |
| 123 | * RAZ/WI for SGIs, PPIs, unimplemented IRQs |
| 124 | * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. |
| 125 | * Writing 1 means "set bit in bitmap"; writing 0 is ignored. |
| 126 | * offset should be the offset in bytes of the register from the start |
| 127 | * of its group. |
| 128 | */ |
| 129 | int irq = offset * 8; |
| 130 | |
| 131 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 132 | return; |
| 133 | } |
| 134 | val &= mask_group_and_nsacr(s, attrs, maskfn, irq); |
| 135 | *gic_bmp_ptr32(bmp, irq) |= val; |
| 136 | gicv3_update(s, irq, 32); |
| 137 | } |
| 138 | |
| 139 | static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs, |
| 140 | uint32_t *bmp, |
| 141 | maskfn *maskfn, |
| 142 | int offset, uint32_t val) |
| 143 | { |
| 144 | /* Helper routine to implement writing to a "clear-bitmap" register |
| 145 | * (GICD_ICENABLER, GICD_ICPENDR, etc). |
| 146 | * Semantics implemented here: |
| 147 | * RAZ/WI for SGIs, PPIs, unimplemented IRQs |
| 148 | * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. |
| 149 | * Writing 1 means "clear bit in bitmap"; writing 0 is ignored. |
| 150 | * offset should be the offset in bytes of the register from the start |
| 151 | * of its group. |
| 152 | */ |
| 153 | int irq = offset * 8; |
| 154 | |
| 155 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 156 | return; |
| 157 | } |
| 158 | val &= mask_group_and_nsacr(s, attrs, maskfn, irq); |
| 159 | *gic_bmp_ptr32(bmp, irq) &= ~val; |
| 160 | gicv3_update(s, irq, 32); |
| 161 | } |
| 162 | |
| 163 | static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs, |
| 164 | uint32_t *bmp, |
| 165 | maskfn *maskfn, |
| 166 | int offset) |
| 167 | { |
| 168 | /* Helper routine to implement reading a "set/clear-bitmap" register |
| 169 | * (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc). |
| 170 | * Semantics implemented here: |
| 171 | * RAZ/WI for SGIs, PPIs, unimplemented IRQs |
| 172 | * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. |
| 173 | * offset should be the offset in bytes of the register from the start |
| 174 | * of its group. |
| 175 | */ |
| 176 | int irq = offset * 8; |
| 177 | uint32_t val; |
| 178 | |
| 179 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 180 | return 0; |
| 181 | } |
| 182 | val = *gic_bmp_ptr32(bmp, irq); |
| 183 | if (bmp == s->pending) { |
| 184 | /* The PENDING register is a special case -- for level triggered |
| 185 | * interrupts, the PENDING state is the logical OR of the state of |
| 186 | * the PENDING latch with the input line level. |
| 187 | */ |
| 188 | uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq); |
| 189 | uint32_t level = *gic_bmp_ptr32(s->level, irq); |
| 190 | val |= (~edge & level); |
| 191 | } |
| 192 | val &= mask_group_and_nsacr(s, attrs, maskfn, irq); |
| 193 | return val; |
| 194 | } |
| 195 | |
| 196 | static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq) |
| 197 | { |
| 198 | /* Read the value of GICD_IPRIORITYR<n> for the specified interrupt, |
| 199 | * honouring security state (these are RAZ/WI for Group 0 or Secure |
| 200 | * Group 1 interrupts). |
| 201 | */ |
| 202 | uint32_t prio; |
| 203 | |
| 204 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 205 | return 0; |
| 206 | } |
| 207 | |
| 208 | prio = s->gicd_ipriority[irq]; |
| 209 | |
| 210 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 211 | if (!gicv3_gicd_group_test(s, irq)) { |
| 212 | /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ |
| 213 | return 0; |
| 214 | } |
| 215 | /* NS view of the interrupt priority */ |
| 216 | prio = (prio << 1) & 0xff; |
| 217 | } |
| 218 | return prio; |
| 219 | } |
| 220 | |
| 221 | static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq, |
| 222 | uint8_t value) |
| 223 | { |
| 224 | /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt, |
| 225 | * honouring security state (these are RAZ/WI for Group 0 or Secure |
| 226 | * Group 1 interrupts). |
| 227 | */ |
| 228 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 229 | return; |
| 230 | } |
| 231 | |
| 232 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 233 | if (!gicv3_gicd_group_test(s, irq)) { |
| 234 | /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ |
| 235 | return; |
| 236 | } |
| 237 | /* NS view of the interrupt priority */ |
| 238 | value = 0x80 | (value >> 1); |
| 239 | } |
| 240 | s->gicd_ipriority[irq] = value; |
| 241 | } |
| 242 | |
| 243 | static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq) |
| 244 | { |
| 245 | /* Read the value of GICD_IROUTER<n> for the specified interrupt, |
| 246 | * honouring security state. |
| 247 | */ |
| 248 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 253 | /* RAZ/WI for NS accesses to secure interrupts */ |
| 254 | if (!gicv3_gicd_group_test(s, irq)) { |
| 255 | if (gicd_ns_access(s, irq) != 3) { |
| 256 | return 0; |
| 257 | } |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | return s->gicd_irouter[irq]; |
| 262 | } |
| 263 | |
| 264 | static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq, |
| 265 | uint64_t val) |
| 266 | { |
| 267 | /* Write the value of GICD_IROUTER<n> for the specified interrupt, |
| 268 | * honouring security state. |
| 269 | */ |
| 270 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 271 | return; |
| 272 | } |
| 273 | |
| 274 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 275 | /* RAZ/WI for NS accesses to secure interrupts */ |
| 276 | if (!gicv3_gicd_group_test(s, irq)) { |
| 277 | if (gicd_ns_access(s, irq) != 3) { |
| 278 | return; |
| 279 | } |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | s->gicd_irouter[irq] = val; |
| 284 | gicv3_cache_target_cpustate(s, irq); |
| 285 | gicv3_update(s, irq, 1); |
| 286 | } |
| 287 | |
| 288 | /** |
| 289 | * gicd_readb |
| 290 | * gicd_readw |
| 291 | * gicd_readl |
| 292 | * gicd_readq |
| 293 | * gicd_writeb |
| 294 | * gicd_writew |
| 295 | * gicd_writel |
| 296 | * gicd_writeq |
| 297 | * |
| 298 | * Return %true if the operation succeeded, %false otherwise. |
| 299 | */ |
| 300 | |
| 301 | static bool gicd_readb(GICv3State *s, hwaddr offset, |
| 302 | uint64_t *data, MemTxAttrs attrs) |
| 303 | { |
| 304 | /* Most GICv3 distributor registers do not support byte accesses. */ |
| 305 | switch (offset) { |
| 306 | case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: |
| 307 | case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: |
| 308 | case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: |
| 309 | /* This GIC implementation always has affinity routing enabled, |
| 310 | * so these registers are all RAZ/WI. |
| 311 | */ |
| 312 | return true; |
| 313 | case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: |
| 314 | *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); |
| 315 | return true; |
| 316 | default: |
| 317 | return false; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static bool gicd_writeb(GICv3State *s, hwaddr offset, |
| 322 | uint64_t value, MemTxAttrs attrs) |
| 323 | { |
| 324 | /* Most GICv3 distributor registers do not support byte accesses. */ |
| 325 | switch (offset) { |
| 326 | case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: |
| 327 | case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: |
| 328 | case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: |
| 329 | /* This GIC implementation always has affinity routing enabled, |
| 330 | * so these registers are all RAZ/WI. |
| 331 | */ |
| 332 | return true; |
| 333 | case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: |
| 334 | { |
| 335 | int irq = offset - GICD_IPRIORITYR; |
| 336 | |
| 337 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 338 | return true; |
| 339 | } |
| 340 | gicd_write_ipriorityr(s, attrs, irq, value); |
| 341 | gicv3_update(s, irq, 1); |
| 342 | return true; |
| 343 | } |
| 344 | default: |
| 345 | return false; |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | static bool gicd_readw(GICv3State *s, hwaddr offset, |
| 350 | uint64_t *data, MemTxAttrs attrs) |
| 351 | { |
| 352 | /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR |
| 353 | * support 16 bit accesses, and those registers are all part of the |
| 354 | * optional message-based SPI feature which this GIC does not currently |
| 355 | * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are |
| 356 | * reserved. |
| 357 | */ |
| 358 | return false; |
| 359 | } |
| 360 | |
| 361 | static bool gicd_writew(GICv3State *s, hwaddr offset, |
| 362 | uint64_t value, MemTxAttrs attrs) |
| 363 | { |
| 364 | /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR |
| 365 | * support 16 bit accesses, and those registers are all part of the |
| 366 | * optional message-based SPI feature which this GIC does not currently |
| 367 | * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are |
| 368 | * reserved. |
| 369 | */ |
| 370 | return false; |
| 371 | } |
| 372 | |
| 373 | static bool gicd_readl(GICv3State *s, hwaddr offset, |
| 374 | uint64_t *data, MemTxAttrs attrs) |
| 375 | { |
| 376 | /* Almost all GICv3 distributor registers are 32-bit. |
| 377 | * Note that WO registers must return an UNKNOWN value on reads, |
| 378 | * not an abort. |
| 379 | */ |
| 380 | |
| 381 | switch (offset) { |
| 382 | case GICD_CTLR: |
| 383 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 384 | /* The NS view of the GICD_CTLR sees only certain bits: |
| 385 | * + bit [31] (RWP) is an alias of the Secure bit [31] |
| 386 | * + bit [4] (ARE_NS) is an alias of Secure bit [5] |
| 387 | * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if |
| 388 | * NS affinity routing is enabled, otherwise RES0 |
| 389 | * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if |
| 390 | * NS affinity routing is not enabled, otherwise RES0 |
| 391 | * Since for QEMU affinity routing is always enabled |
| 392 | * for both S and NS this means that bits [4] and [5] are |
| 393 | * both always 1, and we can simply make the NS view |
| 394 | * be bits 31, 4 and 1 of the S view. |
| 395 | */ |
| 396 | *data = s->gicd_ctlr & (GICD_CTLR_ARE_S | |
| 397 | GICD_CTLR_EN_GRP1NS | |
| 398 | GICD_CTLR_RWP); |
| 399 | } else { |
| 400 | *data = s->gicd_ctlr; |
| 401 | } |
| 402 | return true; |
| 403 | case GICD_TYPER: |
| 404 | { |
| 405 | /* For this implementation: |
| 406 | * No1N == 1 (1-of-N SPI interrupts not supported) |
| 407 | * A3V == 1 (non-zero values of Affinity level 3 supported) |
| 408 | * IDbits == 0xf (we support 16-bit interrupt identifiers) |
| 409 | * DVIS == 1 (Direct virtual LPI injection supported) if GICv4 |
| 410 | * LPIS == 1 (LPIs are supported if affinity routing is enabled) |
| 411 | * num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated |
| 412 | * by GICD_TYPER.IDbits) |
| 413 | * MBIS == 0 (message-based SPIs not supported) |
| 414 | * SecurityExtn == 1 if security extns supported |
| 415 | * NMI = 1 if Non-maskable interrupt property is supported |
| 416 | * CPUNumber == 0 since for us ARE is always 1 |
| 417 | * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1) |
| 418 | */ |
| 419 | int itlinesnumber = (s->num_irq / 32) - 1; |
| 420 | /* |
| 421 | * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and |
| 422 | * "security extensions not supported" always implies DS == 1, |
| 423 | * so we only need to check the DS bit. |
| 424 | */ |
| 425 | bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); |
| 426 | bool dvis = s->revision >= 4; |
| 427 | |
| 428 | *data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) | |
| 429 | (s->nmi_support << GICD_TYPER_NMI_SHIFT) | |
| 430 | (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | |
| 431 | (0xf << 19) | itlinesnumber; |
| 432 | return true; |
| 433 | } |
| 434 | case GICD_TYPER2: |
| 435 | /* |
| 436 | * This register only exists for GICv4.1, which QEMU doesn't |
| 437 | * currently emulate. On GICv3 and GICv4 it's defined to be RES0. |
| 438 | * We implement as read-zero here to avoid tracing a bad-register-read |
| 439 | * if GICv4.1-aware software reads this ID register. |
| 440 | */ |
| 441 | *data = 0; |
| 442 | return true; |
| 443 | case GICD_IIDR: |
| 444 | /* We claim to be an ARM r0p0 with a zero ProductID. |
| 445 | * This is the same as an r0p0 GIC-500. |
| 446 | */ |
| 447 | *data = gicv3_iidr(); |
| 448 | return true; |
| 449 | case GICD_STATUSR: |
| 450 | /* RAZ/WI for us (this is an optional register and our implementation |
| 451 | * does not track RO/WO/reserved violations to report them to the guest) |
| 452 | */ |
| 453 | *data = 0; |
| 454 | return true; |
| 455 | case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: |
| 456 | { |
| 457 | int irq; |
| 458 | |
| 459 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 460 | *data = 0; |
| 461 | return true; |
| 462 | } |
| 463 | /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ |
| 464 | irq = (offset - GICD_IGROUPR) * 8; |
| 465 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 466 | *data = 0; |
| 467 | return true; |
| 468 | } |
| 469 | *data = *gic_bmp_ptr32(s->group, irq); |
| 470 | return true; |
| 471 | } |
| 472 | case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: |
| 473 | *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, |
| 474 | offset - GICD_ISENABLER); |
| 475 | return true; |
| 476 | case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: |
| 477 | *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, |
| 478 | offset - GICD_ICENABLER); |
| 479 | return true; |
| 480 | case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: |
| 481 | *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, |
| 482 | offset - GICD_ISPENDR); |
| 483 | return true; |
| 484 | case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: |
| 485 | *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, |
| 486 | offset - GICD_ICPENDR); |
| 487 | return true; |
| 488 | case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: |
| 489 | *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, |
| 490 | offset - GICD_ISACTIVER); |
| 491 | return true; |
| 492 | case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: |
| 493 | *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, |
| 494 | offset - GICD_ICACTIVER); |
| 495 | return true; |
| 496 | case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: |
| 497 | { |
| 498 | int i, irq = offset - GICD_IPRIORITYR; |
| 499 | uint32_t value = 0; |
| 500 | |
| 501 | for (i = irq + 3; i >= irq; i--) { |
| 502 | value <<= 8; |
| 503 | value |= gicd_read_ipriorityr(s, attrs, i); |
| 504 | } |
| 505 | *data = value; |
| 506 | return true; |
| 507 | } |
| 508 | case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: |
| 509 | /* RAZ/WI since affinity routing is always enabled */ |
| 510 | *data = 0; |
| 511 | return true; |
| 512 | case GICD_ICFGR ... GICD_ICFGR + 0xff: |
| 513 | { |
| 514 | /* Here only the even bits are used; odd bits are RES0 */ |
| 515 | int irq = (offset - GICD_ICFGR) * 4; |
| 516 | uint32_t value = 0; |
| 517 | |
| 518 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 519 | *data = 0; |
| 520 | return true; |
| 521 | } |
| 522 | |
| 523 | /* Since our edge_trigger bitmap is one bit per irq, we only need |
| 524 | * half of the 32-bit word, which we can then spread out |
| 525 | * into the odd bits. |
| 526 | */ |
| 527 | value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f); |
| 528 | value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); |
| 529 | value = extract32(value, (irq & 0x1f) ? 16 : 0, 16); |
| 530 | value = half_shuffle32(value) << 1; |
| 531 | *data = value; |
| 532 | return true; |
| 533 | } |
| 534 | case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: |
| 535 | { |
| 536 | int irq; |
| 537 | |
| 538 | if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { |
| 539 | /* RAZ/WI if security disabled, or if |
| 540 | * security enabled and this is an NS access |
| 541 | */ |
| 542 | *data = 0; |
| 543 | return true; |
| 544 | } |
| 545 | /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ |
| 546 | irq = (offset - GICD_IGRPMODR) * 8; |
| 547 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 548 | *data = 0; |
| 549 | return true; |
| 550 | } |
| 551 | *data = *gic_bmp_ptr32(s->grpmod, irq); |
| 552 | return true; |
| 553 | } |
| 554 | case GICD_NSACR ... GICD_NSACR + 0xff: |
| 555 | { |
| 556 | /* Two bits per interrupt */ |
| 557 | int irq = (offset - GICD_NSACR) * 4; |
| 558 | |
| 559 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 560 | *data = 0; |
| 561 | return true; |
| 562 | } |
| 563 | |
| 564 | if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { |
| 565 | /* RAZ/WI if security disabled, or if |
| 566 | * security enabled and this is an NS access |
| 567 | */ |
| 568 | *data = 0; |
| 569 | return true; |
| 570 | } |
| 571 | |
| 572 | *data = s->gicd_nsacr[irq / 16]; |
| 573 | return true; |
| 574 | } |
| 575 | case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: |
| 576 | case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: |
| 577 | /* RAZ/WI since affinity routing is always enabled */ |
| 578 | *data = 0; |
| 579 | return true; |
| 580 | case GICD_INMIR ... GICD_INMIR + 0x7f: |
| 581 | *data = (!s->nmi_support) ? 0 : |
| 582 | gicd_read_bitmap_reg(s, attrs, s->nmi, NULL, |
| 583 | offset - GICD_INMIR); |
| 584 | return true; |
| 585 | case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: |
| 586 | { |
| 587 | uint64_t r; |
| 588 | int irq = (offset - GICD_IROUTER) / 8; |
| 589 | |
| 590 | r = gicd_read_irouter(s, attrs, irq); |
| 591 | if (offset & 7) { |
| 592 | *data = r >> 32; |
| 593 | } else { |
| 594 | *data = (uint32_t)r; |
| 595 | } |
| 596 | return true; |
| 597 | } |
| 598 | case GICD_IDREGS ... GICD_IDREGS + 0x2f: |
| 599 | /* ID registers */ |
| 600 | *data = gicv3_idreg(s, offset - GICD_IDREGS, GICV3_PIDR0_DIST); |
| 601 | return true; |
| 602 | case GICD_SGIR: |
| 603 | /* WO registers, return unknown value */ |
| 604 | qemu_log_mask(LOG_GUEST_ERROR, |
| 605 | "%s: invalid guest read from WO register at offset " |
| 606 | HWADDR_FMT_plx "\n", __func__, offset); |
| 607 | *data = 0; |
| 608 | return true; |
| 609 | default: |
| 610 | return false; |
| 611 | } |
| 612 | } |
| 613 | |
| 614 | static bool gicd_writel(GICv3State *s, hwaddr offset, |
| 615 | uint64_t value, MemTxAttrs attrs) |
| 616 | { |
| 617 | /* Almost all GICv3 distributor registers are 32-bit. Note that |
| 618 | * RO registers must ignore writes, not abort. |
| 619 | */ |
| 620 | |
| 621 | switch (offset) { |
| 622 | case GICD_CTLR: |
| 623 | { |
| 624 | uint32_t mask; |
| 625 | /* GICv3 5.3.20 */ |
| 626 | if (s->gicd_ctlr & GICD_CTLR_DS) { |
| 627 | /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI, |
| 628 | * ARE is RAO/WI (affinity routing always on), and only |
| 629 | * bits 0 and 1 (group enables) are writable. |
| 630 | */ |
| 631 | mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS; |
| 632 | } else { |
| 633 | if (attrs.secure) { |
| 634 | /* for secure access: |
| 635 | * ARE_NS and ARE_S are RAO/WI (affinity routing always on) |
| 636 | * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup) |
| 637 | * |
| 638 | * We can only modify bits[2:0] (the group enables). |
| 639 | */ |
| 640 | mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL; |
| 641 | } else { |
| 642 | /* For non secure access ARE_NS is RAO/WI and EnableGrp1 |
| 643 | * is RES0. The only writable bit is [1] (EnableGrp1A), which |
| 644 | * is an alias of the Secure bit [1]. |
| 645 | */ |
| 646 | mask = GICD_CTLR_EN_GRP1NS; |
| 647 | } |
| 648 | } |
| 649 | s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask); |
| 650 | if (value & mask & GICD_CTLR_DS) { |
| 651 | /* We just set DS, so the ARE_NS and EnG1S bits are now RES0. |
| 652 | * Note that this is a one-way transition because if DS is set |
| 653 | * then it's not writable, so it can only go back to 0 with a |
| 654 | * hardware reset. |
| 655 | */ |
| 656 | s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); |
| 657 | } |
| 658 | gicv3_full_update(s); |
| 659 | return true; |
| 660 | } |
| 661 | case GICD_STATUSR: |
| 662 | /* RAZ/WI for our implementation */ |
| 663 | return true; |
| 664 | case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: |
| 665 | { |
| 666 | int irq; |
| 667 | |
| 668 | if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { |
| 669 | return true; |
| 670 | } |
| 671 | /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ |
| 672 | irq = (offset - GICD_IGROUPR) * 8; |
| 673 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 674 | return true; |
| 675 | } |
| 676 | *gic_bmp_ptr32(s->group, irq) = value; |
| 677 | gicv3_update(s, irq, 32); |
| 678 | return true; |
| 679 | } |
| 680 | case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: |
| 681 | gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, |
| 682 | offset - GICD_ISENABLER, value); |
| 683 | return true; |
| 684 | case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: |
| 685 | gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, |
| 686 | offset - GICD_ICENABLER, value); |
| 687 | return true; |
| 688 | case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: |
| 689 | gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, |
| 690 | offset - GICD_ISPENDR, value); |
| 691 | return true; |
| 692 | case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: |
| 693 | gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, |
| 694 | offset - GICD_ICPENDR, value); |
| 695 | return true; |
| 696 | case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: |
| 697 | gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, |
| 698 | offset - GICD_ISACTIVER, value); |
| 699 | return true; |
| 700 | case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: |
| 701 | gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, |
| 702 | offset - GICD_ICACTIVER, value); |
| 703 | return true; |
| 704 | case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: |
| 705 | { |
| 706 | int i, irq = offset - GICD_IPRIORITYR; |
| 707 | |
| 708 | if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) { |
| 709 | return true; |
| 710 | } |
| 711 | |
| 712 | for (i = irq; i < irq + 4; i++, value >>= 8) { |
| 713 | gicd_write_ipriorityr(s, attrs, i, value); |
| 714 | } |
| 715 | gicv3_update(s, irq, 4); |
| 716 | return true; |
| 717 | } |
| 718 | case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: |
| 719 | /* RAZ/WI since affinity routing is always enabled */ |
| 720 | return true; |
| 721 | case GICD_ICFGR ... GICD_ICFGR + 0xff: |
| 722 | { |
| 723 | /* Here only the odd bits are used; even bits are RES0 */ |
| 724 | int irq = (offset - GICD_ICFGR) * 4; |
| 725 | uint32_t mask, oldval; |
| 726 | |
| 727 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 728 | return true; |
| 729 | } |
| 730 | |
| 731 | /* Since our edge_trigger bitmap is one bit per irq, our input |
| 732 | * 32-bits will compress down into 16 bits which we need |
| 733 | * to write into the bitmap. |
| 734 | */ |
| 735 | value = half_unshuffle32(value >> 1); |
| 736 | mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); |
| 737 | if (irq & 0x1f) { |
| 738 | value <<= 16; |
| 739 | mask &= 0xffff0000U; |
| 740 | } else { |
| 741 | mask &= 0xffff; |
| 742 | } |
| 743 | oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); |
| 744 | value = (oldval & ~mask) | (value & mask); |
| 745 | *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value; |
| 746 | return true; |
| 747 | } |
| 748 | case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: |
| 749 | { |
| 750 | int irq; |
| 751 | |
| 752 | if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { |
| 753 | /* RAZ/WI if security disabled, or if |
| 754 | * security enabled and this is an NS access |
| 755 | */ |
| 756 | return true; |
| 757 | } |
| 758 | /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ |
| 759 | irq = (offset - GICD_IGRPMODR) * 8; |
| 760 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 761 | return true; |
| 762 | } |
| 763 | *gic_bmp_ptr32(s->grpmod, irq) = value; |
| 764 | gicv3_update(s, irq, 32); |
| 765 | return true; |
| 766 | } |
| 767 | case GICD_NSACR ... GICD_NSACR + 0xff: |
| 768 | { |
| 769 | /* Two bits per interrupt */ |
| 770 | int irq = (offset - GICD_NSACR) * 4; |
| 771 | |
| 772 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 773 | return true; |
| 774 | } |
| 775 | |
| 776 | if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { |
| 777 | /* RAZ/WI if security disabled, or if |
| 778 | * security enabled and this is an NS access |
| 779 | */ |
| 780 | return true; |
| 781 | } |
| 782 | |
| 783 | s->gicd_nsacr[irq / 16] = value; |
| 784 | /* No update required as this only affects access permission checks */ |
| 785 | return true; |
| 786 | } |
| 787 | case GICD_SGIR: |
| 788 | /* RES0 if affinity routing is enabled */ |
| 789 | return true; |
| 790 | case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: |
| 791 | case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: |
| 792 | /* RAZ/WI since affinity routing is always enabled */ |
| 793 | return true; |
| 794 | case GICD_INMIR ... GICD_INMIR + 0x7f: |
| 795 | if (s->nmi_support) { |
| 796 | gicd_write_bitmap_reg(s, attrs, s->nmi, NULL, |
| 797 | offset - GICD_INMIR, value); |
| 798 | } |
| 799 | return true; |
| 800 | case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: |
| 801 | { |
| 802 | uint64_t r; |
| 803 | int irq = (offset - GICD_IROUTER) / 8; |
| 804 | |
| 805 | if (irq < GIC_INTERNAL || irq >= s->num_irq) { |
| 806 | return true; |
| 807 | } |
| 808 | |
| 809 | /* Write half of the 64-bit register */ |
| 810 | r = gicd_read_irouter(s, attrs, irq); |
| 811 | r = deposit64(r, (offset & 7) ? 32 : 0, 32, value); |
| 812 | gicd_write_irouter(s, attrs, irq, r); |
| 813 | return true; |
| 814 | } |
| 815 | case GICD_IDREGS ... GICD_IDREGS + 0x2f: |
| 816 | case GICD_TYPER: |
| 817 | case GICD_IIDR: |
| 818 | /* RO registers, ignore the write */ |
| 819 | qemu_log_mask(LOG_GUEST_ERROR, |
| 820 | "%s: invalid guest write to RO register at offset " |
| 821 | HWADDR_FMT_plx "\n", __func__, offset); |
| 822 | return true; |
| 823 | default: |
| 824 | return false; |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | static bool gicd_writeq(GICv3State *s, hwaddr offset, |
| 829 | uint64_t value, MemTxAttrs attrs) |
| 830 | { |
| 831 | /* Our only 64-bit registers are GICD_IROUTER<n> */ |
| 832 | int irq; |
| 833 | |
| 834 | switch (offset) { |
| 835 | case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: |
| 836 | irq = (offset - GICD_IROUTER) / 8; |
| 837 | gicd_write_irouter(s, attrs, irq, value); |
| 838 | return true; |
| 839 | default: |
| 840 | return false; |
| 841 | } |
| 842 | } |
| 843 | |
| 844 | static bool gicd_readq(GICv3State *s, hwaddr offset, |
| 845 | uint64_t *data, MemTxAttrs attrs) |
| 846 | { |
| 847 | /* Our only 64-bit registers are GICD_IROUTER<n> */ |
| 848 | int irq; |
| 849 | |
| 850 | switch (offset) { |
| 851 | case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: |
| 852 | irq = (offset - GICD_IROUTER) / 8; |
| 853 | *data = gicd_read_irouter(s, attrs, irq); |
| 854 | return true; |
| 855 | default: |
| 856 | return false; |
| 857 | } |
| 858 | } |
| 859 | |
| 860 | MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, |
| 861 | unsigned size, MemTxAttrs attrs) |
| 862 | { |
| 863 | GICv3State *s = (GICv3State *)opaque; |
| 864 | bool r; |
| 865 | |
| 866 | switch (size) { |
| 867 | case 1: |
| 868 | r = gicd_readb(s, offset, data, attrs); |
| 869 | break; |
| 870 | case 2: |
| 871 | r = gicd_readw(s, offset, data, attrs); |
| 872 | break; |
| 873 | case 4: |
| 874 | r = gicd_readl(s, offset, data, attrs); |
| 875 | break; |
| 876 | case 8: |
| 877 | r = gicd_readq(s, offset, data, attrs); |
| 878 | break; |
| 879 | default: |
| 880 | r = false; |
| 881 | break; |
| 882 | } |
| 883 | |
| 884 | if (!r) { |
| 885 | qemu_log_mask(LOG_GUEST_ERROR, |
| 886 | "%s: invalid guest read at offset " HWADDR_FMT_plx |
| 887 | " size %u\n", __func__, offset, size); |
| 888 | trace_gicv3_dist_badread(offset, size, attrs.secure); |
| 889 | /* The spec requires that reserved registers are RAZ/WI; |
| 890 | * so use MEMTX_ERROR returns from leaf functions as a way to |
| 891 | * trigger the guest-error logging but don't return it to |
| 892 | * the caller, or we'll cause a spurious guest data abort. |
| 893 | */ |
| 894 | *data = 0; |
| 895 | } else { |
| 896 | trace_gicv3_dist_read(offset, *data, size, attrs.secure); |
| 897 | } |
| 898 | return MEMTX_OK; |
| 899 | } |
| 900 | |
| 901 | MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, |
| 902 | unsigned size, MemTxAttrs attrs) |
| 903 | { |
| 904 | GICv3State *s = (GICv3State *)opaque; |
| 905 | bool r; |
| 906 | |
| 907 | switch (size) { |
| 908 | case 1: |
| 909 | r = gicd_writeb(s, offset, data, attrs); |
| 910 | break; |
| 911 | case 2: |
| 912 | r = gicd_writew(s, offset, data, attrs); |
| 913 | break; |
| 914 | case 4: |
| 915 | r = gicd_writel(s, offset, data, attrs); |
| 916 | break; |
| 917 | case 8: |
| 918 | r = gicd_writeq(s, offset, data, attrs); |
| 919 | break; |
| 920 | default: |
| 921 | r = false; |
| 922 | break; |
| 923 | } |
| 924 | |
| 925 | if (!r) { |
| 926 | qemu_log_mask(LOG_GUEST_ERROR, |
| 927 | "%s: invalid guest write at offset " HWADDR_FMT_plx |
| 928 | " size %u\n", __func__, offset, size); |
| 929 | trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); |
| 930 | /* The spec requires that reserved registers are RAZ/WI; |
| 931 | * so use MEMTX_ERROR returns from leaf functions as a way to |
| 932 | * trigger the guest-error logging but don't return it to |
| 933 | * the caller, or we'll cause a spurious guest data abort. |
| 934 | */ |
| 935 | } else { |
| 936 | trace_gicv3_dist_write(offset, data, size, attrs.secure); |
| 937 | } |
| 938 | return MEMTX_OK; |
| 939 | } |
| 940 | |
| 941 | void gicv3_dist_set_irq(GICv3State *s, int irq, int level) |
| 942 | { |
| 943 | /* Update distributor state for a change in an external SPI input line */ |
| 944 | if (level == gicv3_gicd_level_test(s, irq)) { |
| 945 | return; |
| 946 | } |
| 947 | |
| 948 | trace_gicv3_dist_set_irq(irq, level); |
| 949 | |
| 950 | gicv3_gicd_level_replace(s, irq, level); |
| 951 | |
| 952 | if (level) { |
| 953 | /* 0->1 edges latch the pending bit for edge-triggered interrupts */ |
| 954 | if (gicv3_gicd_edge_trigger_test(s, irq)) { |
| 955 | gicv3_gicd_pending_set(s, irq); |
| 956 | } |
| 957 | } |
| 958 | |
| 959 | gicv3_update(s, irq, 1); |
| 960 | } |