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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * ARM Generic Interrupt Controller using HVF platform support
4 *
5 * Copyright (c) 2025 Mohamed Mediouni
6 * Based on vGICv3 KVM code by Pavel Fedin
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/intc/arm_gicv3_common.h"
13 #include "qemu/error-report.h"
14 #include "qemu/module.h"
15 #include "system/runstate.h"
16 #include "migration/vmstate.h"
17 #include "system/hvf.h"
18 #include "system/hvf_int.h"
19 #include "hvf_arm.h"
20 #include "gicv3_internal.h"
21 #include "vgic_common.h"
22 #include "qom/object.h"
23 #include "target/arm/cpregs.h"
24 #include <Hypervisor/Hypervisor.h>
25
26 /*
27 * For the GIC, override the check outright, as availability is checked
28 * elsewhere
29 */
30 #pragma clang diagnostic push
31 #pragma clang diagnostic ignored "-Wunguarded-availability"
32
33 struct HVFARMGICv3Class {
34 ARMGICv3CommonClass parent_class;
35 DeviceRealize parent_realize;
36 ResettablePhases parent_phases;
37 };
38
39 typedef struct HVFARMGICv3Class HVFARMGICv3Class;
40
41 typedef struct HVFGICv3State {
42 GICv3State parent_obj;
43 uint32_t size;
44 void *state;
45 } HVFGICv3State;
46
47 DECLARE_OBJ_CHECKERS(HVFGICv3State, HVFARMGICv3Class,
48 HVF_GICV3, TYPE_HVF_GICV3);
49
50 /*
51 * Loop through each distributor IRQ related register; since bits
52 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
53 * is enabled, we skip those.
54 */
55 #define for_each_dist_irq_reg(_irq, _max, _field_width) \
56 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
57
58 /*
59 * Wrap calls to the vGIC APIs to assert_hvf_ok()
60 * as a macro to keep the code clean.
61 */
62 #define hv_gic_get_distributor_reg(offset, reg) \
63 assert_hvf_ok(hv_gic_get_distributor_reg(offset, reg))
64
65 #define hv_gic_set_distributor_reg(offset, reg) \
66 assert_hvf_ok(hv_gic_set_distributor_reg(offset, reg))
67
68 #define hv_gic_get_redistributor_reg(vcpu, reg, value) \
69 assert_hvf_ok(hv_gic_get_redistributor_reg(vcpu, reg, value))
70
71 #define hv_gic_set_redistributor_reg(vcpu, reg, value) \
72 assert_hvf_ok(hv_gic_set_redistributor_reg(vcpu, reg, value))
73
74 #define hv_gic_get_icc_reg(vcpu, reg, value) \
75 assert_hvf_ok(hv_gic_get_icc_reg(vcpu, reg, value))
76
77 #define hv_gic_set_icc_reg(vcpu, reg, value) \
78 assert_hvf_ok(hv_gic_set_icc_reg(vcpu, reg, value))
79
80 #define hv_gic_get_ich_reg(vcpu, reg, value) \
81 assert_hvf_ok(hv_gic_get_ich_reg(vcpu, reg, value))
82
83 #define hv_gic_set_ich_reg(vcpu, reg, value) \
84 assert_hvf_ok(hv_gic_set_ich_reg(vcpu, reg, value))
85
86 static void hvf_dist_get_priority(GICv3State *s,
87 hv_gic_distributor_reg_t offset,
88 uint8_t *bmp)
89 {
90 uint64_t reg;
91 uint32_t *field;
92 int irq;
93 field = (uint32_t *)(bmp);
94
95 for_each_dist_irq_reg(irq, s->num_irq, 8) {
96 hv_gic_get_distributor_reg(offset, &reg);
97 *field = reg;
98 offset += 4;
99 field++;
100 }
101 }
102
103 static void hvf_dist_put_priority(GICv3State *s,
104 hv_gic_distributor_reg_t offset,
105 uint8_t *bmp)
106 {
107 uint32_t reg, *field;
108 int irq;
109 field = (uint32_t *)(bmp);
110
111 for_each_dist_irq_reg(irq, s->num_irq, 8) {
112 reg = *field;
113 hv_gic_set_distributor_reg(offset, reg);
114 offset += 4;
115 field++;
116 }
117 }
118
119 static void hvf_dist_get_edge_trigger(GICv3State *s,
120 hv_gic_distributor_reg_t offset,
121 uint32_t *bmp)
122 {
123 uint64_t reg;
124 int irq;
125
126 for_each_dist_irq_reg(irq, s->num_irq, 2) {
127 hv_gic_get_distributor_reg(offset, &reg);
128 reg = half_unshuffle32(reg >> 1);
129 if (irq % 32 != 0) {
130 reg = (reg << 16);
131 }
132 *gic_bmp_ptr32(bmp, irq) |= reg;
133 offset += 4;
134 }
135 }
136
137 static void hvf_dist_put_edge_trigger(GICv3State *s,
138 hv_gic_distributor_reg_t offset,
139 uint32_t *bmp)
140 {
141 uint32_t reg;
142 int irq;
143
144 for_each_dist_irq_reg(irq, s->num_irq, 2) {
145 reg = *gic_bmp_ptr32(bmp, irq);
146 if (irq % 32 != 0) {
147 reg = (reg & 0xffff0000) >> 16;
148 } else {
149 reg = reg & 0xffff;
150 }
151 reg = half_shuffle32(reg) << 1;
152 hv_gic_set_distributor_reg(offset, reg);
153 offset += 4;
154 }
155 }
156
157 /* Read a bitmap register group from the kernel VGIC. */
158 static void hvf_dist_getbmp(GICv3State *s, hv_gic_distributor_reg_t offset,
159 uint32_t *bmp)
160 {
161 uint64_t reg;
162 int irq;
163
164 for_each_dist_irq_reg(irq, s->num_irq, 1) {
165 hv_gic_get_distributor_reg(offset, &reg);
166 *gic_bmp_ptr32(bmp, irq) = reg;
167 offset += 4;
168 }
169 }
170
171 static void hvf_dist_putbmp(GICv3State *s, hv_gic_distributor_reg_t offset,
172 hv_gic_distributor_reg_t clroffset, uint32_t *bmp)
173 {
174 uint32_t reg;
175 int irq;
176
177 for_each_dist_irq_reg(irq, s->num_irq, 1) {
178 /*
179 * If this bitmap is a set/clear register pair, first write to the
180 * clear-reg to clear all bits before using the set-reg to write
181 * the 1 bits.
182 */
183 if (clroffset != 0) {
184 reg = 0;
185 hv_gic_set_distributor_reg(clroffset, reg);
186 clroffset += 4;
187 }
188 reg = *gic_bmp_ptr32(bmp, irq);
189 hv_gic_set_distributor_reg(offset, reg);
190 offset += 4;
191 }
192 }
193
194 static void hvf_gicv3_check(GICv3State *s)
195 {
196 uint64_t reg;
197 uint32_t num_irq;
198
199 /* Sanity checking s->num_irq */
200 hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_TYPER, &reg);
201 num_irq = ((reg & 0x1f) + 1) * 32;
202
203 if (num_irq < s->num_irq) {
204 error_report("Model requests %u IRQs, but HVF supports max %u",
205 s->num_irq, num_irq);
206 abort();
207 }
208 }
209
210 static void hvf_gicv3_put_cpu_el2(CPUState *cpu_state, run_on_cpu_data arg)
211 {
212 int num_pri_bits;
213
214 /* Redistributor state */
215 GICv3CPUState *c = arg.host_ptr;
216 hv_vcpu_t vcpu = c->cpu->accel->fd;
217
218 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, c->ich_vmcr_el2);
219 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, c->ich_hcr_el2);
220
221 for (int i = 0; i < GICV3_LR_MAX; i++) {
222 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, c->ich_lr_el2[i]);
223 }
224
225 num_pri_bits = c->vpribits;
226
227 switch (num_pri_bits) {
228 case 7:
229 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3,
230 c->ich_apr[GICV3_G0][3]);
231 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2,
232 c->ich_apr[GICV3_G0][2]);
233 /* fall through */
234 case 6:
235 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1,
236 c->ich_apr[GICV3_G0][1]);
237 /* fall through */
238 default:
239 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2,
240 c->ich_apr[GICV3_G0][0]);
241 }
242
243 switch (num_pri_bits) {
244 case 7:
245 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3,
246 c->ich_apr[GICV3_G1NS][3]);
247 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2,
248 c->ich_apr[GICV3_G1NS][2]);
249 /* fall through */
250 case 6:
251 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1,
252 c->ich_apr[GICV3_G1NS][1]);
253 /* fall through */
254 default:
255 hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2,
256 c->ich_apr[GICV3_G1NS][0]);
257 }
258 }
259
260 static void hvf_gicv3_put_cpu(CPUState *cpu_state, run_on_cpu_data arg)
261 {
262 uint32_t reg;
263 uint64_t reg64;
264 int i, num_pri_bits;
265
266 /* Redistributor state */
267 GICv3CPUState *c = arg.host_ptr;
268 hv_vcpu_t vcpu = c->cpu->accel->fd;
269
270 reg = c->gicr_waker;
271 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0, reg);
272
273 reg = c->gicr_igroupr0;
274 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0, reg);
275
276 reg = ~0;
277 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICENABLER0, reg);
278 reg = c->gicr_ienabler0;
279 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISENABLER0, reg);
280
281 /* Restore config before pending so we treat level/edge correctly */
282 reg = half_shuffle32(c->edge_trigger >> 16) << 1;
283 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR1, reg);
284
285 reg = ~0;
286 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICPENDR0, reg);
287 reg = c->gicr_ipendr0;
288 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISPENDR0, reg);
289
290 reg = ~0;
291 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0, reg);
292 reg = c->gicr_iactiver0;
293 hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISACTIVER0, reg);
294
295 for (i = 0; i < GIC_INTERNAL; i += 4) {
296 reg = c->gicr_ipriorityr[i] |
297 (c->gicr_ipriorityr[i + 1] << 8) |
298 (c->gicr_ipriorityr[i + 2] << 16) |
299 (c->gicr_ipriorityr[i + 3] << 24);
300 hv_gic_set_redistributor_reg(vcpu,
301 HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, reg);
302 }
303
304 /* CPU interface state */
305 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, c->icc_sre_el1);
306
307 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1,
308 c->icc_ctlr_el1[GICV3_NS]);
309 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1,
310 c->icc_igrpen[GICV3_G0]);
311 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1,
312 c->icc_igrpen[GICV3_G1NS]);
313 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, c->icc_pmr_el1);
314 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, c->icc_bpr[GICV3_G0]);
315 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, c->icc_bpr[GICV3_G1NS]);
316
317 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
318 ICC_CTLR_EL1_PRIBITS_MASK) >>
319 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
320
321 switch (num_pri_bits) {
322 case 7:
323 reg64 = c->icc_apr[GICV3_G0][3];
324 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3, reg64);
325 reg64 = c->icc_apr[GICV3_G0][2];
326 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2, reg64);
327 /* fall through */
328 case 6:
329 reg64 = c->icc_apr[GICV3_G0][1];
330 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1, reg64);
331 /* fall through */
332 default:
333 reg64 = c->icc_apr[GICV3_G0][0];
334 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1, reg64);
335 }
336
337 switch (num_pri_bits) {
338 case 7:
339 reg64 = c->icc_apr[GICV3_G1NS][3];
340 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3, reg64);
341 reg64 = c->icc_apr[GICV3_G1NS][2];
342 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2, reg64);
343 /* fall through */
344 case 6:
345 reg64 = c->icc_apr[GICV3_G1NS][1];
346 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1, reg64);
347 /* fall through */
348 default:
349 reg64 = c->icc_apr[GICV3_G1NS][0];
350 hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64);
351 }
352
353 /* Registers beyond this point are with nested virt only */
354 if (c->gic->maint_irq) {
355 hvf_gicv3_put_cpu_el2(cpu_state, arg);
356 }
357 }
358
359 static void hvf_gicv3_put(GICv3State *s)
360 {
361 uint32_t reg;
362 int ncpu, i;
363
364 hvf_gicv3_check(s);
365
366 reg = s->gicd_ctlr;
367 hv_gic_set_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, reg);
368
369 /* per-CPU state */
370
371 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
372 run_on_cpu_data data;
373 data.host_ptr = &s->cpu[ncpu];
374 run_on_cpu(s->cpu[ncpu].cpu, hvf_gicv3_put_cpu, data);
375 }
376
377 /* s->enable bitmap -> GICD_ISENABLERn */
378 hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0,
379 HV_GIC_DISTRIBUTOR_REG_GICD_ICENABLER0, s->enabled);
380
381 /* s->group bitmap -> GICD_IGROUPRn */
382 hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0,
383 0, s->group);
384
385 /*
386 * Restore targets before pending to ensure the pending state is set on
387 * the appropriate CPU interfaces in the kernel
388 */
389
390 /* s->gicd_irouter[irq] -> GICD_IROUTERn */
391 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
392 uint32_t offset = HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + (8 * i)
393 - (8 * GIC_INTERNAL);
394 hv_gic_set_distributor_reg(offset, s->gicd_irouter[i]);
395 }
396
397 /*
398 * s->trigger bitmap -> GICD_ICFGRn
399 * (restore configuration registers before pending IRQs so we treat
400 * level/edge correctly)
401 */
402 hvf_dist_put_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0, s->edge_trigger);
403
404 /* s->pending bitmap -> GICD_ISPENDRn */
405 hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0,
406 HV_GIC_DISTRIBUTOR_REG_GICD_ICPENDR0, s->pending);
407
408 /* s->active bitmap -> GICD_ISACTIVERn */
409 hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0,
410 HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0, s->active);
411
412 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
413 hvf_dist_put_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0, s->gicd_ipriority);
414 }
415
416 static void hvf_gicv3_get_cpu_el2(CPUState *cpu_state, run_on_cpu_data arg)
417 {
418 int num_pri_bits;
419
420 /* Redistributor state */
421 GICv3CPUState *c = arg.host_ptr;
422 hv_vcpu_t vcpu = c->cpu->accel->fd;
423
424 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, &c->ich_vmcr_el2);
425 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, &c->ich_hcr_el2);
426
427 for (int i = 0; i < GICV3_LR_MAX; i++) {
428 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, &c->ich_lr_el2[i]);
429 }
430
431 num_pri_bits = c->vpribits;
432
433 switch (num_pri_bits) {
434 case 7:
435 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3,
436 &c->ich_apr[GICV3_G0][3]);
437 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2,
438 &c->ich_apr[GICV3_G0][2]);
439 /* fall through */
440 case 6:
441 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1,
442 &c->ich_apr[GICV3_G0][1]);
443 /* fall through */
444 default:
445 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2,
446 &c->ich_apr[GICV3_G0][0]);
447 }
448
449 switch (num_pri_bits) {
450 case 7:
451 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3,
452 &c->ich_apr[GICV3_G1NS][3]);
453 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2,
454 &c->ich_apr[GICV3_G1NS][2]);
455 /* fall through */
456 case 6:
457 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1,
458 &c->ich_apr[GICV3_G1NS][1]);
459 /* fall through */
460 default:
461 hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2,
462 &c->ich_apr[GICV3_G1NS][0]);
463 }
464 }
465
466 static void hvf_gicv3_get_cpu(CPUState *cpu_state, run_on_cpu_data arg)
467 {
468 uint64_t reg;
469 int i, num_pri_bits;
470
471 /* Redistributor state */
472 GICv3CPUState *c = arg.host_ptr;
473 hv_vcpu_t vcpu = c->cpu->accel->fd;
474
475 hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0,
476 &reg);
477 c->gicr_igroupr0 = reg;
478 hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISENABLER0,
479 &reg);
480 c->gicr_ienabler0 = reg;
481 hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR1,
482 &reg);
483 c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
484 hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISPENDR0,
485 &reg);
486 c->gicr_ipendr0 = reg;
487 hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISACTIVER0,
488 &reg);
489 c->gicr_iactiver0 = reg;
490
491 for (i = 0; i < GIC_INTERNAL; i += 4) {
492 hv_gic_get_redistributor_reg(
493 vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, &reg);
494 c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
495 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
496 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
497 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
498 }
499
500 /* CPU interface */
501 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, &c->icc_sre_el1);
502
503 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1,
504 &c->icc_ctlr_el1[GICV3_NS]);
505 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1,
506 &c->icc_igrpen[GICV3_G0]);
507 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1,
508 &c->icc_igrpen[GICV3_G1NS]);
509 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, &c->icc_pmr_el1);
510 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, &c->icc_bpr[GICV3_G0]);
511 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, &c->icc_bpr[GICV3_G1NS]);
512 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_PRIBITS_MASK) >>
513 ICC_CTLR_EL1_PRIBITS_SHIFT) +
514 1;
515
516 switch (num_pri_bits) {
517 case 7:
518 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3,
519 &c->icc_apr[GICV3_G0][3]);
520 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2,
521 &c->icc_apr[GICV3_G0][2]);
522 /* fall through */
523 case 6:
524 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1,
525 &c->icc_apr[GICV3_G0][1]);
526 /* fall through */
527 default:
528 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1,
529 &c->icc_apr[GICV3_G0][0]);
530 }
531
532 switch (num_pri_bits) {
533 case 7:
534 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3,
535 &c->icc_apr[GICV3_G1NS][3]);
536 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2,
537 &c->icc_apr[GICV3_G1NS][2]);
538 /* fall through */
539 case 6:
540 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1,
541 &c->icc_apr[GICV3_G1NS][1]);
542 /* fall through */
543 default:
544 hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1,
545 &c->icc_apr[GICV3_G1NS][0]);
546 }
547
548 /* Registers beyond this point are with nested virt only */
549 if (c->gic->maint_irq) {
550 hvf_gicv3_get_cpu_el2(cpu_state, arg);
551 }
552 }
553
554 static void hvf_gicv3_get(GICv3State *s)
555 {
556 uint64_t reg;
557 int ncpu, i;
558
559 hvf_gicv3_check(s);
560
561 hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, &reg);
562 s->gicd_ctlr = reg;
563
564 /* Redistributor state (one per CPU) */
565
566 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
567 run_on_cpu_data data;
568 data.host_ptr = &s->cpu[ncpu];
569 run_on_cpu(s->cpu[ncpu].cpu, hvf_gicv3_get_cpu, data);
570 }
571
572 /* GICD_IGROUPRn -> s->group bitmap */
573 hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0, s->group);
574
575 /* GICD_ISENABLERn -> s->enabled bitmap */
576 hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0, s->enabled);
577
578 /* GICD_ISPENDRn -> s->pending bitmap */
579 hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, s->pending);
580
581 /* GICD_ISACTIVERn -> s->active bitmap */
582 hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, s->active);
583
584 /* GICD_ICFGRn -> s->trigger bitmap */
585 hvf_dist_get_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0,
586 s->edge_trigger);
587
588 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
589 hvf_dist_get_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0,
590 s->gicd_ipriority);
591
592 /* GICD_IROUTERn -> s->gicd_irouter[irq] */
593 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
594 uint32_t offset = HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32
595 + (8 * i) - (8 * GIC_INTERNAL);
596 hv_gic_get_distributor_reg(offset, &s->gicd_irouter[i]);
597 }
598 }
599
600 static void hvf_gicv3_set_irq(void *opaque, int irq, int level)
601 {
602 GICv3State *s = opaque;
603 if (irq > s->num_irq) {
604 return;
605 }
606 hv_gic_set_spi(GIC_INTERNAL + irq, !!level);
607 }
608
609 static void hvf_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
610 {
611 GICv3CPUState *c;
612
613 c = env->gicv3state;
614 c->icc_pmr_el1 = 0;
615 /*
616 * Architecturally the reset value of the ICC_BPR registers
617 * is UNKNOWN. We set them all to 0 here; when the kernel
618 * uses these values to program the ICH_VMCR_EL2 fields that
619 * determine the guest-visible ICC_BPR register values, the
620 * hardware's "writing a value less than the minimum sets
621 * the field to the minimum value" behaviour will result in
622 * them effectively resetting to the correct minimum value
623 * for the host GIC.
624 */
625 c->icc_bpr[GICV3_G0] = 0;
626 c->icc_bpr[GICV3_G1] = 0;
627 c->icc_bpr[GICV3_G1NS] = 0;
628
629 c->icc_sre_el1 = 0x7;
630 memset(c->icc_apr, 0, sizeof(c->icc_apr));
631 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
632 }
633
634 static void hvf_gicv3_reset_hold(Object *obj, ResetType type)
635 {
636 GICv3State *s = ARM_GICV3_COMMON(obj);
637 HVFARMGICv3Class *kgc = HVF_GICV3_GET_CLASS(s);
638
639 if (kgc->parent_phases.hold) {
640 kgc->parent_phases.hold(obj, type);
641 }
642
643 hvf_gicv3_put(s);
644 }
645
646
647 /*
648 * CPU interface registers of GIC needs to be reset on CPU reset.
649 * For the calling arm_gicv3_icc_reset() on CPU reset, we register
650 * below ARMCPRegInfo. As we reset the whole cpu interface under single
651 * register reset, we define only one register of CPU interface instead
652 * of defining all the registers.
653 */
654 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
655 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
656 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
657 /*
658 * If ARM_CP_NOP is used, resetfn is not called,
659 * So ARM_CP_NO_RAW is appropriate type.
660 */
661 .type = ARM_CP_NO_RAW,
662 .access = PL1_RW,
663 .readfn = arm_cp_read_zero,
664 .writefn = arm_cp_write_ignore,
665 /*
666 * We hang the whole cpu interface reset routine off here
667 * rather than parcelling it out into one little function
668 * per register
669 */
670 .resetfn = hvf_gicv3_icc_reset,
671 },
672 };
673
674 static void hvf_gicv3_realize(DeviceState *dev, Error **errp)
675 {
676 ERRP_GUARD();
677 GICv3State *s = (GICv3State *)HVF_GICV3(dev);
678 HVFARMGICv3Class *kgc = HVF_GICV3_GET_CLASS(s);
679 int i;
680
681 kgc->parent_realize(dev, errp);
682 if (*errp) {
683 return;
684 }
685
686 if (s->revision != 3) {
687 error_setg(errp, "unsupported GIC revision %d for platform GIC",
688 s->revision);
689 }
690
691 if (s->security_extn) {
692 error_setg(errp, "the platform vGICv3 does not implement the "
693 "security extensions");
694 return;
695 }
696
697 if (s->nmi_support) {
698 error_setg(errp, "NMI is not supported with the platform GIC");
699 return;
700 }
701
702 if (s->nb_redist_regions > 1) {
703 error_setg(errp, "Multiple VGICv3 redistributor regions are not "
704 "supported by HVF");
705 error_append_hint(errp, "A maximum of %d VCPUs can be used",
706 s->redist_region_count[0]);
707 return;
708 }
709
710 gicv3_init_irqs_and_mmio(s, hvf_gicv3_set_irq, NULL);
711
712 for (i = 0; i < s->num_cpu; i++) {
713 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
714
715 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
716 }
717
718 if (s->maint_irq && s->maint_irq != HV_GIC_INT_MAINTENANCE) {
719 error_setg(errp, "vGIC maintenance IRQ mismatch with the hardcoded one in HVF.");
720 return;
721 }
722 }
723
724 /*
725 * HVF doesn't have a way to save the RDIST pending tables
726 * to guest memory, only to an opaque data structure.
727 */
728 static bool gicv3_is_hvf(void *opaque)
729 {
730 return hvf_enabled() && hvf_irqchip_in_kernel();
731 }
732
733 static int hvf_gic_opaque_state_save(void *opaque)
734 {
735 HVFGICv3State *gic = opaque;
736 hv_gic_state_t gic_state;
737 hv_return_t err;
738 size_t size;
739
740 gic_state = hv_gic_state_create();
741 if (gic_state == NULL) {
742 error_report("hvf: vgic: failed to create hv_gic_state_create.");
743 return 1;
744 }
745 err = hv_gic_state_get_size(gic_state, &size);
746 gic->size = size;
747 if (err != HV_SUCCESS) {
748 error_report("hvf: vgic: failed to get GIC state size.");
749 os_release(gic_state);
750 return 1;
751 }
752 gic->state = g_malloc0(gic->size);
753 err = hv_gic_state_get_data(gic_state, gic->state);
754 if (err != HV_SUCCESS) {
755 error_report("hvf: vgic: failed to get GIC state.");
756 os_release(gic_state);
757 return 1;
758 }
759
760 os_release(gic_state);
761 return 0;
762 }
763
764 static void hvf_gic_opaque_state_free(void *opaque)
765 {
766 HVFGICv3State *gic = opaque;
767 free(gic->state);
768 }
769
770 static int hvf_gic_opaque_state_restore(void *opaque, int version_id)
771 {
772 HVFGICv3State *gic = opaque;
773 hv_return_t err;
774 if (!gic->size) {
775 return 0;
776 }
777 err = hv_gic_set_state(gic->state, gic->size);
778 if (err != HV_SUCCESS) {
779 error_report("hvf: vgic: failed to restore GIC state.");
780 return 1;
781 }
782 return 0;
783 }
784
785 const VMStateDescription vmstate_gicv3_hvf = {
786 .name = "arm_gicv3/hvf_gic_state",
787 .version_id = 1,
788 .minimum_version_id = 1,
789 .needed = gicv3_is_hvf,
790 .pre_save = hvf_gic_opaque_state_save,
791 .post_save = hvf_gic_opaque_state_free,
792 .post_load = hvf_gic_opaque_state_restore,
793 .version_id = 1,
794 .minimum_version_id = 1,
795 .fields = (const VMStateField[]) {
796 VMSTATE_UINT32(size, HVFGICv3State),
797 VMSTATE_VBUFFER_ALLOC_UINT32(state,
798 HVFGICv3State, 0, 0,
799 size),
800 VMSTATE_END_OF_LIST()
801 },
802 };
803
804 static void hvf_gicv3_class_init(ObjectClass *klass, const void *data)
805 {
806 DeviceClass *dc = DEVICE_CLASS(klass);
807 ResettableClass *rc = RESETTABLE_CLASS(klass);
808 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
809 HVFARMGICv3Class *kgc = HVF_GICV3_CLASS(klass);
810
811 agcc->pre_save = hvf_gicv3_get;
812 agcc->post_load = hvf_gicv3_put;
813
814 device_class_set_parent_realize(dc, hvf_gicv3_realize,
815 &kgc->parent_realize);
816 resettable_class_set_parent_phases(rc, NULL, hvf_gicv3_reset_hold, NULL,
817 &kgc->parent_phases);
818 }
819
820 static const TypeInfo hvf_arm_gicv3_info = {
821 .name = TYPE_HVF_GICV3,
822 .parent = TYPE_ARM_GICV3_COMMON,
823 .instance_size = sizeof(HVFGICv3State),
824 .class_init = hvf_gicv3_class_init,
825 .class_size = sizeof(HVFARMGICv3Class),
826 };
827
828 static void hvf_gicv3_register_types(void)
829 {
830 type_register_static(&hvf_arm_gicv3_info);
831 }
832
833 type_init(hvf_gicv3_register_types)
834
835 #pragma clang diagnostic pop