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1 /*
2 * ITS base class for a GICv3-based system
3 *
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * Written by Pavel Fedin
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/pci/msi.h"
23 #include "migration/vmstate.h"
24 #include "hw/intc/arm_gicv3_its_common.h"
25 #include "qemu/log.h"
26 #include "qemu/module.h"
27 #include "system/kvm.h"
28
29 static int gicv3_its_pre_save(void *opaque)
30 {
31 GICv3ITSState *s = (GICv3ITSState *)opaque;
32 GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
33
34 if (c->pre_save) {
35 c->pre_save(s);
36 }
37
38 return 0;
39 }
40
41 static int gicv3_its_post_load(void *opaque, int version_id)
42 {
43 GICv3ITSState *s = (GICv3ITSState *)opaque;
44 GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
45
46 if (c->post_load) {
47 c->post_load(s);
48 }
49 return 0;
50 }
51
52 static const VMStateDescription vmstate_its = {
53 .name = "arm_gicv3_its",
54 .pre_save = gicv3_its_pre_save,
55 .post_load = gicv3_its_post_load,
56 .priority = MIG_PRI_GICV3_ITS,
57 .fields = (const VMStateField[]) {
58 VMSTATE_UINT32(ctlr, GICv3ITSState),
59 VMSTATE_UINT32(iidr, GICv3ITSState),
60 VMSTATE_UINT64(cbaser, GICv3ITSState),
61 VMSTATE_UINT64(cwriter, GICv3ITSState),
62 VMSTATE_UINT64(creadr, GICv3ITSState),
63 VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
64 VMSTATE_END_OF_LIST()
65 },
66 };
67
68 static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
69 uint64_t *data, unsigned size,
70 MemTxAttrs attrs)
71 {
72 qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
73 *data = 0;
74 return MEMTX_OK;
75 }
76
77 static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
78 uint64_t value, unsigned size,
79 MemTxAttrs attrs)
80 {
81 if (offset == 0x0040 && ((size == 2) || (size == 4))) {
82 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
83 GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
84 int ret = c->send_msi(s, value, attrs.requester_id);
85
86 if (ret <= 0) {
87 qemu_log_mask(LOG_GUEST_ERROR,
88 "ITS: Error sending MSI: %s\n", strerror(-ret));
89 }
90 } else {
91 qemu_log_mask(LOG_GUEST_ERROR,
92 "ITS write at bad offset 0x%"PRIx64"\n", offset);
93 }
94 return MEMTX_OK;
95 }
96
97 static const MemoryRegionOps gicv3_its_trans_ops = {
98 .read_with_attrs = gicv3_its_trans_read,
99 .write_with_attrs = gicv3_its_trans_write,
100 .endianness = DEVICE_LITTLE_ENDIAN,
101 };
102
103 void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
104 const MemoryRegionOps *tops)
105 {
106 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
107
108 memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
109 "control", ITS_CONTROL_SIZE);
110 memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
111 tops ? tops : &gicv3_its_trans_ops, s,
112 "translation", ITS_TRANS_SIZE);
113
114 /* Our two regions are always adjacent, therefore we now combine them
115 * into a single one in order to make our users' life easier.
116 */
117 memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
118 memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
119 memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
120 &s->iomem_its_translation);
121 sysbus_init_mmio(sbd, &s->iomem_main);
122
123 msi_nonbroken = true;
124 }
125
126 static void gicv3_its_common_reset_hold(Object *obj, ResetType type)
127 {
128 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
129
130 s->ctlr = 0;
131 s->cbaser = 0;
132 s->cwriter = 0;
133 s->creadr = 0;
134 s->iidr = 0;
135 memset(&s->baser, 0, sizeof(s->baser));
136 }
137
138 static void gicv3_its_common_class_init(ObjectClass *klass, const void *data)
139 {
140 DeviceClass *dc = DEVICE_CLASS(klass);
141 ResettableClass *rc = RESETTABLE_CLASS(klass);
142
143 rc->phases.hold = gicv3_its_common_reset_hold;
144 dc->vmsd = &vmstate_its;
145 }
146
147 static const TypeInfo gicv3_its_common_info = {
148 .name = TYPE_ARM_GICV3_ITS_COMMON,
149 .parent = TYPE_SYS_BUS_DEVICE,
150 .instance_size = sizeof(GICv3ITSState),
151 .class_size = sizeof(GICv3ITSCommonClass),
152 .class_init = gicv3_its_common_class_init,
153 .abstract = true,
154 };
155
156 static void gicv3_its_common_register_types(void)
157 {
158 type_register_static(&gicv3_its_common_info);
159 }
160
161 type_init(gicv3_its_common_register_types)
162
163 const char *its_class_name(void)
164 {
165 if (kvm_irqchip_in_kernel()) {
166 return "arm-its-kvm";
167 } else {
168 /* Software emulation based model */
169 return "arm-gicv3-its";
170 }
171 }