| 1 | /* |
| 2 | * ARM GICv5 emulation: Interrupt Routing Service (IRS) |
| 3 | * |
| 4 | * Copyright (c) 2025 Linaro Limited |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | * |
| 8 | * The IRS is defined in IHI 111701 |
| 9 | * (ARM Generic Interrupt Controller Architecture Specification, |
| 10 | * GIC architecture version 5): |
| 11 | * https://developer.arm.com/documentation/111701/latest |
| 12 | */ |
| 13 | |
| 14 | #include "qemu/osdep.h" |
| 15 | #include "hw/core/registerfields.h" |
| 16 | #include "hw/intc/arm_gicv5.h" |
| 17 | #include "hw/intc/arm_gicv5_stream.h" |
| 18 | #include "qapi/error.h" |
| 19 | #include "qemu/log.h" |
| 20 | #include "trace.h" |
| 21 | #include "migration/blocker.h" |
| 22 | |
| 23 | OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON) |
| 24 | |
| 25 | static const char *domain_name[] = { |
| 26 | [GICV5_ID_S] = "Secure", |
| 27 | [GICV5_ID_NS] = "NonSecure", |
| 28 | [GICV5_ID_EL3] = "EL3", |
| 29 | [GICV5_ID_REALM] = "Realm", |
| 30 | }; |
| 31 | |
| 32 | static const char *inttype_name(GICv5IntType t) |
| 33 | { |
| 34 | /* |
| 35 | * We have to be more cautious with getting human readable names |
| 36 | * for a GICv5IntType for trace strings than we do with the domain |
| 37 | * enum, because here the value can come from a guest register |
| 38 | * field. |
| 39 | */ |
| 40 | static const char *names[] = { |
| 41 | [GICV5_PPI] = "PPI", |
| 42 | [GICV5_LPI] = "LPI", |
| 43 | [GICV5_SPI] = "SPI", |
| 44 | }; |
| 45 | if (t >= ARRAY_SIZE(names) || !names[t]) { |
| 46 | return "RESERVED"; |
| 47 | } |
| 48 | return names[t]; |
| 49 | } |
| 50 | |
| 51 | REG32(IRS_IDR0, 0x0) |
| 52 | FIELD(IRS_IDR0, INT_DOM, 0, 2) |
| 53 | FIELD(IRS_IDR0, PA_RANGE, 2, 4) |
| 54 | FIELD(IRS_IDR0, VIRT, 6, 1) |
| 55 | FIELD(IRS_IDR0, ONE_N, 7, 1) |
| 56 | FIELD(IRS_IDR0, VIRT_ONE_N, 8, 1) |
| 57 | FIELD(IRS_IDR0, SETLPI, 9, 1) |
| 58 | FIELD(IRS_IDR0, MEC, 10, 1) |
| 59 | FIELD(IRS_IDR0, MPAM, 11, 1) |
| 60 | FIELD(IRS_IDR0, SWE, 12, 1) |
| 61 | FIELD(IRS_IDR0, IRSID, 16, 16) |
| 62 | |
| 63 | REG32(IRS_IDR1, 0x4) |
| 64 | FIELD(IRS_IDR1, PE_CNT, 0, 16) |
| 65 | FIELD(IRS_IDR1, IAFFID_BITS, 16, 4) |
| 66 | FIELD(IRS_IDR1, PRI_BITS, 20, 3) |
| 67 | |
| 68 | REG32(IRS_IDR2, 0x8) |
| 69 | FIELD(IRS_IDR2, ID_BITS, 0, 5) |
| 70 | FIELD(IRS_IDR2, LPI, 5, 1) |
| 71 | FIELD(IRS_IDR2, MIN_LPI_ID_BITS, 6, 4) |
| 72 | FIELD(IRS_IDR2, IST_LEVELS, 10, 1) |
| 73 | FIELD(IRS_IDR2, IST_L2SZ, 11, 3) |
| 74 | FIELD(IRS_IDR2, IST_MD, 14, 1) |
| 75 | FIELD(IRS_IDR2, ISTMD_SZ, 15, 5) |
| 76 | |
| 77 | REG32(IRS_IDR3, 0xc) |
| 78 | FIELD(IRS_IDR3, VMD, 0, 1) |
| 79 | FIELD(IRS_IDR3, VMD_SZ, 1, 4) |
| 80 | FIELD(IRS_IDR3, VM_ID_BITS, 5, 5) |
| 81 | FIELD(IRS_IDR3, VMT_LEVELS, 10, 1) |
| 82 | |
| 83 | REG32(IRS_IDR4, 0x10) |
| 84 | FIELD(IRS_IDR4, VPED_SZ, 0, 6) |
| 85 | FIELD(IRS_IDR4, VPE_ID_BITS, 6, 4) |
| 86 | |
| 87 | REG32(IRS_IDR5, 0x14) |
| 88 | FIELD(IRS_IDR5, SPI_RANGE, 0, 25) |
| 89 | |
| 90 | REG32(IRS_IDR6, 0x18) |
| 91 | FIELD(IRS_IDR6, SPI_IRS_RANGE, 0, 25) |
| 92 | |
| 93 | REG32(IRS_IDR7, 0x1c) |
| 94 | FIELD(IRS_IDR7, SPI_BASE, 0, 24) |
| 95 | |
| 96 | REG32(IRS_IIDR, 0x40) |
| 97 | FIELD(IRS_IIDR, IMPLEMENTER, 0, 12) |
| 98 | FIELD(IRS_IIDR, REVISION, 12, 4) |
| 99 | FIELD(IRS_IIDR, VARIANT, 16, 4) |
| 100 | FIELD(IRS_IIDR, PRODUCTID, 20, 12) |
| 101 | |
| 102 | REG32(IRS_AIDR, 0x44) |
| 103 | FIELD(IRS_AIDR, ARCHMINORREV, 0, 4) |
| 104 | FIELD(IRS_AIDR, ARCHMAJORREV, 4, 4) |
| 105 | FIELD(IRS_AIDR, COMPONENT, 8, 4) |
| 106 | |
| 107 | REG32(IRS_CR0, 0x80) |
| 108 | FIELD(IRS_CR0, IRSEN, 0, 1) |
| 109 | FIELD(IRS_CR0, IDLE, 1, 1) |
| 110 | |
| 111 | REG32(IRS_CR1, 0x84) |
| 112 | FIELD(IRS_CR1, SH, 0, 2) |
| 113 | FIELD(IRS_CR1, OC, 2, 2) |
| 114 | FIELD(IRS_CR1, IC, 4, 2) |
| 115 | FIELD(IRS_CR1, IST_RA, 6, 1) |
| 116 | FIELD(IRS_CR1, IST_WA, 7, 1) |
| 117 | FIELD(IRS_CR1, VMT_RA, 8, 1) |
| 118 | FIELD(IRS_CR1, VMT_WA, 9, 1) |
| 119 | FIELD(IRS_CR1, VPET_RA, 10, 1) |
| 120 | FIELD(IRS_CR1, VPET_WA, 11, 1) |
| 121 | FIELD(IRS_CR1, VMD_RA, 12, 1) |
| 122 | FIELD(IRS_CR1, VMD_WA, 13, 1) |
| 123 | FIELD(IRS_CR1, VPED_RA, 14, 1) |
| 124 | FIELD(IRS_CR1, VPED_WA, 15, 1) |
| 125 | |
| 126 | REG32(IRS_SYNCR, 0xc0) |
| 127 | FIELD(IRS_SYNCR, SYNC, 31, 1) |
| 128 | |
| 129 | REG32(IRS_SYNC_STATUSR, 0xc4) |
| 130 | FIELD(IRS_SYNC_STATUSR, IDLE, 0, 1) |
| 131 | |
| 132 | REG64(IRS_SPI_VMR, 0x100) |
| 133 | FIELD(IRS_SPI_VMR, VM_ID, 0, 16) |
| 134 | FIELD(IRS_SPI_VMR, VIRT, 63, 1) |
| 135 | |
| 136 | REG32(IRS_SPI_SELR, 0x108) |
| 137 | FIELD(IRS_SPI_SELR, ID, 0, 24) |
| 138 | |
| 139 | REG32(IRS_SPI_DOMAINR, 0x10c) |
| 140 | FIELD(IRS_SPI_DOMAINR, DOMAIN, 0, 2) |
| 141 | |
| 142 | REG32(IRS_SPI_RESAMPLER, 0x110) |
| 143 | FIELD(IRS_SPI_RESAMPLER, SPI_ID, 0, 24) |
| 144 | |
| 145 | REG32(IRS_SPI_CFGR, 0x114) |
| 146 | FIELD(IRS_SPI_CFGR, TM, 0, 1) |
| 147 | |
| 148 | REG32(IRS_SPI_STATUSR, 0x118) |
| 149 | FIELD(IRS_SPI_STATUSR, IDLE, 0, 1) |
| 150 | FIELD(IRS_SPI_STATUSR, V, 1, 1) |
| 151 | |
| 152 | REG32(IRS_PE_SELR, 0x140) |
| 153 | FIELD(IRS_PE_SELR, IAFFID, 0, 16) |
| 154 | |
| 155 | REG32(IRS_PE_STATUSR, 0x144) |
| 156 | FIELD(IRS_PE_STATUSR, IDLE, 0, 1) |
| 157 | FIELD(IRS_PE_STATUSR, V, 1, 1) |
| 158 | FIELD(IRS_PE_STATUSR, ONLINE, 2, 1) |
| 159 | |
| 160 | REG32(IRS_PE_CR0, 0x148) |
| 161 | FIELD(IRS_PE_CR0, DPS, 0, 1) |
| 162 | |
| 163 | REG64(IRS_IST_BASER, 0x180) |
| 164 | FIELD(IRS_IST_BASER, VALID, 0, 1) |
| 165 | FIELD(IRS_IST_BASER, ADDR, 6, 50) |
| 166 | |
| 167 | REG32(IRS_IST_CFGR, 0x190) |
| 168 | FIELD(IRS_IST_CFGR, LPI_ID_BITS, 0, 5) |
| 169 | FIELD(IRS_IST_CFGR, L2SZ, 5, 2) |
| 170 | FIELD(IRS_IST_CFGR, ISTSZ, 7, 2) |
| 171 | FIELD(IRS_IST_CFGR, STRUCTURE, 16, 1) |
| 172 | |
| 173 | REG32(IRS_IST_STATUSR, 0x194) |
| 174 | FIELD(IRS_IST_STATUSR, IDLE, 0, 1) |
| 175 | |
| 176 | REG32(IRS_MAP_L2_ISTR, 0x1c0) |
| 177 | FIELD(IRS_MAP_L2_ISTR, ID, 0, 24) |
| 178 | |
| 179 | REG64(IRS_VMT_BASER, 0x200) |
| 180 | FIELD(IRS_VMT_BASER, VALID, 0, 1) |
| 181 | FIELD(IRS_VMT_BASER, ADDR, 3, 53) |
| 182 | |
| 183 | REG32(IRS_VMT_CFGR, 0x210) |
| 184 | FIELD(IRS_VMT_CFGR, VM_ID_BITS, 0, 5) |
| 185 | FIELD(IRS_VMT_CFGR, STRUCTURE, 16, 1) |
| 186 | |
| 187 | REG32(IRS_VMT_STATUSR, 0x124) |
| 188 | FIELD(IRS_VMT_STATUSR, IDLE, 0, 1) |
| 189 | |
| 190 | REG64(IRS_VPE_SELR, 0x240) |
| 191 | FIELD(IRS_VPE_SELR, VM_ID, 0, 16) |
| 192 | FIELD(IRS_VPE_SELR, VPE_ID, 32, 16) |
| 193 | FIELD(IRS_VPE_SELR, S, 63, 1) |
| 194 | |
| 195 | REG64(IRS_VPE_DBR, 0x248) |
| 196 | FIELD(IRS_VPE_DBR, INTID, 0, 24) |
| 197 | FIELD(IRS_VPE_DBR, DBPM, 32, 5) |
| 198 | FIELD(IRS_VPE_DBR, REQ_DB, 62, 1) |
| 199 | FIELD(IRS_VPE_DBR, DBV, 63, 1) |
| 200 | |
| 201 | REG32(IRS_VPE_HPPIR, 0x250) |
| 202 | FIELD(IRS_VPE_HPPIR, ID, 0, 24) |
| 203 | FIELD(IRS_VPE_HPPIR, TYPE, 29, 3) |
| 204 | FIELD(IRS_VPE_HPPIR, HPPIV, 32, 1) |
| 205 | |
| 206 | REG32(IRS_VPE_CR0, 0x258) |
| 207 | FIELD(IRS_VPE_CR0, DPS, 0, 1) |
| 208 | |
| 209 | REG32(IRS_VPE_STATUSR, 0x25c) |
| 210 | FIELD(IRS_VPE_STATUSR, IDLE, 0, 1) |
| 211 | FIELD(IRS_VPE_STATUSR, V, 1, 1) |
| 212 | |
| 213 | REG64(IRS_VM_DBR, 0x280) |
| 214 | FIELD(IRS_VM_DBR, VPE_ID, 0, 16) |
| 215 | FIELD(IRS_VM_DBR, EN, 63, 1) |
| 216 | |
| 217 | REG32(IRS_VM_SELR, 0x288) |
| 218 | FIELD(IRS_VM_SELR, VM_ID, 0, 16) |
| 219 | |
| 220 | REG32(IRS_VM_STATUSR, 0x28c) |
| 221 | FIELD(IRS_VM_STATUSR, IDLE, 0, 1) |
| 222 | FIELD(IRS_VM_STATUSR, V, 1, 1) |
| 223 | |
| 224 | REG64(IRS_VMAP_L2_VMTR, 0x2c0) |
| 225 | FIELD(IRS_VMAP_L2_VMTR, VM_ID, 0, 16) |
| 226 | FIELD(IRS_VMAP_L2_VMTR, M, 63, 1) |
| 227 | |
| 228 | REG64(IRS_VMAP_VMR, 0x2c8) |
| 229 | FIELD(IRS_VMAP_VMR, VM_ID, 0, 16) |
| 230 | FIELD(IRS_VMAP_VMR, U, 62, 1) |
| 231 | FIELD(IRS_VMAP_VMR, M, 63, 1) |
| 232 | |
| 233 | REG64(IRS_VMAP_VISTR, 0x2d0) |
| 234 | FIELD(IRS_VMAP_VISTR, TYPE, 29, 3) |
| 235 | FIELD(IRS_VMAP_VISTR, VM_ID, 32, 16) |
| 236 | FIELD(IRS_VMAP_VISTR, U, 62, 1) |
| 237 | FIELD(IRS_VMAP_VISTR, M, 63, 1) |
| 238 | |
| 239 | REG64(IRS_VMAP_L2_VISTR, 0x2d8) |
| 240 | FIELD(IRS_VMAP_L2_VISTR, ID, 0, 24) |
| 241 | FIELD(IRS_VMAP_L2_VISTR, TYPE, 29, 3) |
| 242 | FIELD(IRS_VMAP_L2_VISTR, VM_ID, 32, 16) |
| 243 | FIELD(IRS_VMAP_L2_VISTR, M, 63, 1) |
| 244 | |
| 245 | REG64(IRS_VMAP_VPER, 0x2e0) |
| 246 | FIELD(IRS_VMAP_VPER, VPE_ID, 0, 16) |
| 247 | FIELD(IRS_VMAP_VPER, VM_ID, 32, 16) |
| 248 | FIELD(IRS_VMAP_VPER, M, 63, 1) |
| 249 | |
| 250 | REG64(IRS_SAVE_VMR, 0x300) |
| 251 | FIELD(IRS_SAVE_VMR, VM_ID, 0, 16) |
| 252 | FIELD(IRS_SAVE_VMR, Q, 62, 1) |
| 253 | FIELD(IRS_SAVE_VMR, S, 63, 1) |
| 254 | |
| 255 | REG32(IRS_SAVE_VM_STATUSR, 0x308) |
| 256 | FIELD(IRS_SAVE_VM_STATUSR, IDLE, 0, 1) |
| 257 | FIELD(IRS_SAVE_VM_STATUSR, Q, 1, 1) |
| 258 | |
| 259 | REG32(IRS_MEC_IDR, 0x340) |
| 260 | FIELD(IRS_MEC_IDR, MECIDSIZE, 0, 4) |
| 261 | |
| 262 | REG32(IRS_MEC_MECID_R, 0x344) |
| 263 | FIELD(IRS_MEC_MICID_R, MECID, 0, 16) |
| 264 | |
| 265 | REG32(IRS_MPAM_IDR, 0x380) |
| 266 | FIELD(IRS_MPAM_IDR, PARTID_MAX, 0, 16) |
| 267 | FIELD(IRS_MPAM_IDR, PMG_MAX, 16, 8) |
| 268 | FIELD(IRS_MPAM_IDR, HAS_MPAM_SP, 24, 1) |
| 269 | |
| 270 | REG32(IRS_MPAM_PARTID_R, 0x384) |
| 271 | FIELD(IRS_MPAM_IDR, PARTID, 0, 16) |
| 272 | FIELD(IRS_MPAM_IDR, PMG, 16, 8) |
| 273 | FIELD(IRS_MPAM_IDR, MPAM_SP, 24, 2) |
| 274 | FIELD(IRS_MPAM_IDR, IDLE, 31, 1) |
| 275 | |
| 276 | REG64(IRS_SWERR_STATUSR, 0x3c0) |
| 277 | FIELD(IRS_SWERR_STATUSR, V, 0, 1) |
| 278 | FIELD(IRS_SWERR_STATUSR, S0V, 1, 1) |
| 279 | FIELD(IRS_SWERR_STATUSR, S1V, 2, 1) |
| 280 | FIELD(IRS_SWERR_STATUSR, OF, 3, 1) |
| 281 | FIELD(IRS_SWERR_STATUSR, EC, 16, 8) |
| 282 | FIELD(IRS_SWERR_STATUSR, IMP_EC, 24, 8) |
| 283 | |
| 284 | REG64(IRS_SWERR_SYNDROMER0, 0x3c8) |
| 285 | FIELD(IRS_SWERR_SYNDROMER0, VM_ID, 0, 16) |
| 286 | FIELD(IRS_SWERR_SYNDROMER0, ID, 32, 24) |
| 287 | FIELD(IRS_SWERR_SYNDROMER0, TYPE, 60, 3) |
| 288 | FIELD(IRS_SWERR_SYNDROMER0, VIRTUAL, 63, 1) |
| 289 | |
| 290 | REG64(IRS_SWERR_SYNDROMER1, 0x3d0) |
| 291 | FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53) |
| 292 | |
| 293 | REG32(IRS_IDREGS, 0xffd0) |
| 294 | REG32(IRS_DEVARCH, 0xffbc) |
| 295 | |
| 296 | FIELD(L1_ISTE, VALID, 0, 1) |
| 297 | FIELD(L1_ISTE, L2_ADDR, 12, 44) |
| 298 | |
| 299 | FIELD(L2_ISTE, PENDING, 0, 1) |
| 300 | FIELD(L2_ISTE, ACTIVE, 1, 1) |
| 301 | FIELD(L2_ISTE, HM, 2, 1) |
| 302 | FIELD(L2_ISTE, ENABLE, 3, 1) |
| 303 | FIELD(L2_ISTE, IRM, 4, 1) |
| 304 | FIELD(L2_ISTE, HWU, 9, 2) |
| 305 | FIELD(L2_ISTE, PRIORITY, 11, 5) |
| 306 | FIELD(L2_ISTE, IAFFID, 16, 16) |
| 307 | |
| 308 | /* |
| 309 | * Format used for gicv5_request_config() return value, which matches |
| 310 | * the ICC_ICSR_EL1 bit layout. |
| 311 | */ |
| 312 | FIELD(ICSR, F, 0, 1) |
| 313 | FIELD(ICSR, ENABLED, 1, 1) |
| 314 | FIELD(ICSR, PENDING, 2, 1) |
| 315 | FIELD(ICSR, IRM, 3, 1) |
| 316 | FIELD(ICSR, ACTIVE, 4, 1) |
| 317 | FIELD(ICSR, HM, 5, 1) |
| 318 | FIELD(ICSR, PRIORITY, 11, 5) |
| 319 | FIELD(ICSR, IAFFID, 32, 16) |
| 320 | |
| 321 | #define IRS_DEVARCH_VALUE ((0x23b << 31) | (0x1 << 20) | 0x5a19) |
| 322 | |
| 323 | static uint32_t gicv5_idreg(int regoffset) |
| 324 | { |
| 325 | /* |
| 326 | * As with the main IRS_IIDR, we don't identify as a specific |
| 327 | * hardware GICv5 implementation. Arm suggests that the |
| 328 | * Implementer, Product, etc in IRS_IIDR should also be reported |
| 329 | * here, so we do that. |
| 330 | */ |
| 331 | static const uint8_t gic_ids[] = { |
| 332 | QEMU_GICV5_IMPLEMENTER >> 8, 0x00, 0x00, 0x00, /* PIDR4..PIDR7 */ |
| 333 | QEMU_GICV5_PRODUCTID & 0xff, /* PIDR0 */ |
| 334 | ((QEMU_GICV5_PRODUCTID >> 8) | |
| 335 | ((QEMU_GICV5_IMPLEMENTER & 0xf) << 4)), /* PIDR1 */ |
| 336 | ((QEMU_GICV5_REVISION << 4) | (1 << 3) | |
| 337 | ((QEMU_GICV5_IMPLEMENTER & 0x70) >> 4)), /* PIDR2 */ |
| 338 | QEMU_GICV5_VARIANT << 4, /* PIDR3 */ |
| 339 | 0x0D, 0xF0, 0x05, 0xB1, /* CIDR0..CIDR3 */ |
| 340 | }; |
| 341 | |
| 342 | regoffset /= 4; |
| 343 | return gic_ids[regoffset]; |
| 344 | } |
| 345 | |
| 346 | static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain) |
| 347 | { |
| 348 | /* |
| 349 | * If the IRS_SPI_SELR value specifies an SPI that can be managed in |
| 350 | * this domain, return a pointer to its GICv5SPIState; otherwise |
| 351 | * return NULL. |
| 352 | */ |
| 353 | uint32_t id = FIELD_EX32(cs->irs_spi_selr[domain], IRS_SPI_SELR, ID); |
| 354 | GICv5SPIState *spi = gicv5_raw_spi_state(cs, id); |
| 355 | |
| 356 | if (spi && (domain == GICV5_ID_EL3 || domain == spi->domain)) { |
| 357 | return spi; |
| 358 | } |
| 359 | return NULL; |
| 360 | } |
| 361 | |
| 362 | static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain) |
| 363 | { |
| 364 | /* |
| 365 | * Return a MemTxAttrs to use for IRS memory accesses. IRS_CR1 |
| 366 | * has the usual Arm cacheability/shareability attributes, but |
| 367 | * QEMU doesn't care about those. All we need to specify here is |
| 368 | * the correct security attributes, which depend on the interrupt |
| 369 | * domain. Conveniently, our GICv5Domain encoding matches the |
| 370 | * ARMSecuritySpace one (because both follow an architecturally |
| 371 | * specified field). The exception is that the EL3 domain must be |
| 372 | * Secure instead of Root if we don't implement Realm. |
| 373 | */ |
| 374 | if (domain == GICV5_ID_EL3 && |
| 375 | !gicv5_domain_implemented(cs, GICV5_ID_REALM)) { |
| 376 | domain = GICV5_ID_S; |
| 377 | } |
| 378 | return (MemTxAttrs) { |
| 379 | .space = domain, |
| 380 | .secure = domain == GICV5_ID_S || domain == GICV5_ID_EL3, |
| 381 | }; |
| 382 | } |
| 383 | |
| 384 | /* Data we need to pass through to lpi_cache_get_hppi() */ |
| 385 | typedef struct GetHPPIUserData { |
| 386 | GICv5PendingIrq *best; |
| 387 | uint32_t iaffid; |
| 388 | } GetHPPIUserData; |
| 389 | |
| 390 | static void lpi_cache_get_hppi(gpointer key, gpointer value, gpointer user_data) |
| 391 | { |
| 392 | uint64_t id = GPOINTER_TO_INT(key); |
| 393 | uint64_t l2_iste = *(uint64_t *)value; |
| 394 | uint32_t prio, iaffid; |
| 395 | GetHPPIUserData *ud = user_data; |
| 396 | |
| 397 | if ((l2_iste & (R_L2_ISTE_PENDING_MASK | R_L2_ISTE_ACTIVE_MASK | R_L2_ISTE_ENABLE_MASK)) |
| 398 | != (R_L2_ISTE_PENDING_MASK | R_L2_ISTE_ENABLE_MASK)) { |
| 399 | return; |
| 400 | } |
| 401 | prio = FIELD_EX32(l2_iste, L2_ISTE, PRIORITY); |
| 402 | iaffid = FIELD_EX32(l2_iste, L2_ISTE, IAFFID); |
| 403 | if (iaffid == ud->iaffid && prio < ud->best->prio) { |
| 404 | id = FIELD_DP32(id, INTID, TYPE, GICV5_LPI); |
| 405 | ud->best->intid = id; |
| 406 | ud->best->prio = prio; |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | static int irs_cpuidx_from_iaffid(GICv5Common *cs, uint32_t iaffid) |
| 411 | { |
| 412 | for (int i = 0; i < cs->num_cpus; i++) { |
| 413 | if (cs->cpu_iaffids[i] == iaffid) { |
| 414 | return i; |
| 415 | } |
| 416 | } |
| 417 | return -1; |
| 418 | } |
| 419 | |
| 420 | static void irs_recalc_hppi(GICv5 *s, GICv5Domain domain, uint32_t iaffid) |
| 421 | { |
| 422 | /* |
| 423 | * Recalculate the highest priority pending interrupt for the |
| 424 | * specified domain and cpuif. HPPI candidates must be pending, |
| 425 | * inactive and enabled. |
| 426 | */ |
| 427 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 428 | int cpuidx = irs_cpuidx_from_iaffid(cs, iaffid); |
| 429 | ARMCPU *cpu = cpuidx >= 0 ? cs->cpus[cpuidx] : NULL; |
| 430 | GICv5PendingIrq best; |
| 431 | |
| 432 | best = GICV5_PENDING_IRQ_NONE; |
| 433 | |
| 434 | if (!cpu) { |
| 435 | /* Nothing happens for iaffids targeting nonexistent CPUs */ |
| 436 | trace_gicv5_irs_recalc_hppi_fail(domain_name[domain], iaffid, |
| 437 | "IAFFID doesn't match any CPU"); |
| 438 | return; |
| 439 | } |
| 440 | |
| 441 | if (!FIELD_EX32(cs->irs_cr0[domain], IRS_CR0, IRSEN)) { |
| 442 | /* When the IRS is disabled we don't forward HPPIs */ |
| 443 | trace_gicv5_irs_recalc_hppi_fail(domain_name[domain], iaffid, |
| 444 | "IRS_CR0.IRSEN is zero"); |
| 445 | return; |
| 446 | } |
| 447 | |
| 448 | if (s->phys_lpi_config[domain].valid) { |
| 449 | GetHPPIUserData ud; |
| 450 | |
| 451 | ud.best = &best; |
| 452 | ud.iaffid = iaffid; |
| 453 | g_hash_table_foreach(s->phys_lpi_config[domain].lpi_cache, |
| 454 | lpi_cache_get_hppi, &ud); |
| 455 | } |
| 456 | |
| 457 | /* |
| 458 | * OPT: consider also caching the SPI interrupt information, |
| 459 | * similarly to how we handle LPIs, if iterating through the whole |
| 460 | * SPI array every time is too expensive. |
| 461 | */ |
| 462 | for (int i = 0; i < cs->spi_irs_range; i++) { |
| 463 | GICv5SPIState *spi = &cs->spi[i]; |
| 464 | |
| 465 | if (spi->active || !spi->pending || !spi->enabled) { |
| 466 | continue; |
| 467 | } |
| 468 | if (spi->domain != domain || spi->iaffid != iaffid) { |
| 469 | continue; |
| 470 | } |
| 471 | if (spi->priority < best.prio) { |
| 472 | uint32_t intid = 0; |
| 473 | intid = FIELD_DP32(intid, INTID, ID, i); |
| 474 | intid = FIELD_DP32(intid, INTID, TYPE, GICV5_SPI); |
| 475 | best.intid = intid; |
| 476 | best.prio = spi->priority; |
| 477 | } |
| 478 | } |
| 479 | |
| 480 | trace_gicv5_irs_recalc_hppi(domain_name[domain], iaffid, |
| 481 | best.intid, best.prio); |
| 482 | |
| 483 | s->hppi[domain][cpuidx] = best; |
| 484 | /* |
| 485 | * Now present the HPPI to the cpuif. In the real hardware stream |
| 486 | * protocol, the connection between IRS and cpuif is asynchronous, |
| 487 | * and so both ends track their idea of the current HPPI, with a |
| 488 | * back-and-forth sequence so they stay in sync and more |
| 489 | * interaction when the cpuif resets. For QEMU, we are strictly |
| 490 | * synchronous and the cpuif asking the IRS for data is a cheap |
| 491 | * function call, so we simplify this: |
| 492 | * - the IRS knows what the current HPPI is |
| 493 | * - s->hppi[][] is a cache we can recalculate |
| 494 | * - the IRS merely tells the cpuif "something changed", and |
| 495 | * the cpuif asks for the current HPPI when it needs it |
| 496 | * - the cpuif does not cache the HPPI on its end |
| 497 | */ |
| 498 | gicv5_forward_interrupt(cpu, domain); |
| 499 | } |
| 500 | |
| 501 | static void irs_recalc_hppi_all_cpus(GICv5 *s, GICv5Domain domain) |
| 502 | { |
| 503 | /* |
| 504 | * Recalculate the HPPI for every CPU for this domain. This is |
| 505 | * not as efficient as it could be because we will scan through |
| 506 | * the LPI cached hash table and the SPI array for each CPU rather |
| 507 | * than doing a single combined scan, but we only need to do this |
| 508 | * very rarely, when the guest enables or disables the IST, so we |
| 509 | * implement this the simple way. |
| 510 | */ |
| 511 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 512 | for (int i = 0; i < cs->num_cpus; i++) { |
| 513 | irs_recalc_hppi(s, domain, cs->cpu_iaffids[i]); |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | static void irs_recall_hppis(GICv5 *s, GICv5Domain domain) |
| 518 | { |
| 519 | /* |
| 520 | * The IRS was just disabled -- we must recall any pending HPPIs |
| 521 | * we have sent to the CPU interfaces. For us this means that we |
| 522 | * clear our cached HPPI data and tell the cpuif that it has |
| 523 | * changed. |
| 524 | */ |
| 525 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 526 | |
| 527 | for (int i = 0; i < cs->num_cpus; i++) { |
| 528 | s->hppi[domain][i] = GICV5_PENDING_IRQ_NONE; |
| 529 | gicv5_forward_interrupt(cs->cpus[i], domain); |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain, |
| 534 | uint32_t iaffid) |
| 535 | { |
| 536 | GICv5 *s = ARM_GICV5(cs); |
| 537 | int cpuidx = irs_cpuidx_from_iaffid(cs, iaffid); |
| 538 | |
| 539 | assert(cpuidx >= 0); |
| 540 | return s->hppi[domain][cpuidx]; |
| 541 | } |
| 542 | |
| 543 | static hwaddr l1_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 544 | uint32_t id) |
| 545 | { |
| 546 | /* |
| 547 | * In a 2-level IST configuration, return the address of the L1 |
| 548 | * IST entry for this interrupt ID. The bottom l2_idx_bits of the |
| 549 | * ID value are the index into the L2 table, and the higher bits |
| 550 | * of the ID index the L1 table. |
| 551 | */ |
| 552 | uint32_t l1_index = id >> cfg->l2_idx_bits; |
| 553 | return cfg->base + (l1_index * 8); |
| 554 | } |
| 555 | |
| 556 | static bool get_l2_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 557 | uint32_t id, hwaddr *l2_iste_addr) |
| 558 | { |
| 559 | /* |
| 560 | * Get the address of the L2 interrupt state table entry for this |
| 561 | * interrupt. On success, fill in l2_iste_addr and return true. |
| 562 | * On failure, return false. |
| 563 | */ |
| 564 | hwaddr l2_base; |
| 565 | |
| 566 | if (!cfg->valid) { |
| 567 | return false; |
| 568 | } |
| 569 | |
| 570 | if (id >= (1 << cfg->id_bits)) { |
| 571 | return false; |
| 572 | } |
| 573 | |
| 574 | if (cfg->structure) { |
| 575 | /* |
| 576 | * 2-level table: read the L1 IST. The bottom l2_idx_bits of |
| 577 | * the ID value are the index into the L2 table, and the |
| 578 | * higher bits of the ID index the L1 table. There is always |
| 579 | * at least one L1 table entry. |
| 580 | */ |
| 581 | hwaddr l1_addr = l1_iste_addr(cs, cfg, id); |
| 582 | uint64_t l1_iste; |
| 583 | MemTxResult res; |
| 584 | |
| 585 | l1_iste = address_space_ldq_le(&cs->dma_as, l1_addr, |
| 586 | cfg->txattrs, &res); |
| 587 | if (res != MEMTX_OK) { |
| 588 | /* Reportable with EC=0x01 if sw error reporting implemented */ |
| 589 | qemu_log_mask(LOG_GUEST_ERROR, "L1 ISTE lookup failed for ID 0x%x" |
| 590 | " at physical address 0x" HWADDR_FMT_plx "\n", |
| 591 | id, l1_addr); |
| 592 | return false; |
| 593 | } |
| 594 | if (!FIELD_EX64(l1_iste, L1_ISTE, VALID)) { |
| 595 | return false; |
| 596 | } |
| 597 | l2_base = l1_iste & R_L1_ISTE_L2_ADDR_MASK; |
| 598 | id = extract32(id, 0, cfg->l2_idx_bits); |
| 599 | } else { |
| 600 | /* 1-level table */ |
| 601 | l2_base = cfg->base; |
| 602 | } |
| 603 | |
| 604 | *l2_iste_addr = l2_base + (id * cfg->istsz); |
| 605 | return true; |
| 606 | } |
| 607 | |
| 608 | static bool read_l2_iste_mem(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 609 | hwaddr addr, uint32_t *l2_iste) |
| 610 | { |
| 611 | MemTxResult res; |
| 612 | |
| 613 | *l2_iste = address_space_ldl_le(&cs->dma_as, addr, cfg->txattrs, &res); |
| 614 | if (res != MEMTX_OK) { |
| 615 | /* Reportable with EC=0x02 if sw error reporting implemented */ |
| 616 | qemu_log_mask(LOG_GUEST_ERROR, "L2 ISTE read failed at physical " |
| 617 | "address 0x" HWADDR_FMT_plx "\n", addr); |
| 618 | } |
| 619 | return res == MEMTX_OK; |
| 620 | } |
| 621 | |
| 622 | static bool write_l2_iste_mem(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 623 | hwaddr addr, uint32_t l2_iste) |
| 624 | { |
| 625 | MemTxResult res; |
| 626 | |
| 627 | address_space_stl_le(&cs->dma_as, addr, l2_iste, cfg->txattrs, &res); |
| 628 | if (res != MEMTX_OK) { |
| 629 | /* Reportable with EC=0x02 if sw error reporting implemented */ |
| 630 | qemu_log_mask(LOG_GUEST_ERROR, "L2 ISTE write failed at physical " |
| 631 | "address 0x" HWADDR_FMT_plx "\n", addr); |
| 632 | } |
| 633 | return res == MEMTX_OK; |
| 634 | } |
| 635 | |
| 636 | /* |
| 637 | * This is returned by get_l2_iste() and has everything we need to do |
| 638 | * the writeback of the L2 ISTE word in put_l2_iste(). Not all these |
| 639 | * fields are always valid; they are private to the implementation of |
| 640 | * get_l2_iste() and put_l2_iste(). |
| 641 | */ |
| 642 | typedef struct L2_ISTE_Handle { |
| 643 | /* Guest memory address of the L2 ISTE; valid only if !hashed */ |
| 644 | hwaddr l2_iste_addr; |
| 645 | union { |
| 646 | /* Actual L2_ISTE word; valid only if !hashed */ |
| 647 | uint32_t l2_iste; |
| 648 | /* Pointer to L2 ISTE word; valid only if hashed */ |
| 649 | uint32_t *l2_iste_p; |
| 650 | }; |
| 651 | uint32_t id; |
| 652 | /* True if this ISTE is currently in the cache */ |
| 653 | bool hashed; |
| 654 | } L2_ISTE_Handle; |
| 655 | |
| 656 | static uint32_t *get_l2_iste(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 657 | uint32_t id, L2_ISTE_Handle *h) |
| 658 | { |
| 659 | /* |
| 660 | * Find the L2 ISTE for the interrupt @id. |
| 661 | * |
| 662 | * We return a pointer to the ISTE: the caller can freely read and |
| 663 | * modify the uint64_t pointed to to update the ISTE. If the |
| 664 | * caller modifies the L2 ISTE word, it must call put_l2_iste(), |
| 665 | * passing it @h, to write back the ISTE. If the caller is only |
| 666 | * reading the L2 ISTE, it does not need to call put_l2_iste(). |
| 667 | * |
| 668 | * We fill in @h with information needed for put_l2_iste(). |
| 669 | * |
| 670 | * If the ISTE could not be read (typically because of a memory |
| 671 | * error), return NULL. |
| 672 | */ |
| 673 | uint32_t *hashvalue; |
| 674 | |
| 675 | if (!cfg->valid) { |
| 676 | /* Catch invalid config early, it has no lpi_cache */ |
| 677 | return NULL; |
| 678 | } |
| 679 | |
| 680 | hashvalue = g_hash_table_lookup(cfg->lpi_cache, |
| 681 | GINT_TO_POINTER(id)); |
| 682 | |
| 683 | h->id = id; |
| 684 | |
| 685 | if (hashvalue) { |
| 686 | h->hashed = true; |
| 687 | h->l2_iste_p = hashvalue; |
| 688 | return hashvalue; |
| 689 | } |
| 690 | |
| 691 | h->hashed = false; |
| 692 | if (!get_l2_iste_addr(cs, cfg, id, &h->l2_iste_addr) || |
| 693 | !read_l2_iste_mem(cs, cfg, h->l2_iste_addr, &h->l2_iste)) { |
| 694 | return NULL; |
| 695 | } |
| 696 | return &h->l2_iste; |
| 697 | } |
| 698 | |
| 699 | static void put_l2_iste(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 700 | L2_ISTE_Handle *h) |
| 701 | { |
| 702 | /* |
| 703 | * Write back the modified L2_ISTE word found with get_l2_iste(). |
| 704 | * Once this has been called the L2_ISTE_Handle @h and the pointer |
| 705 | * to the L2 ISTE word are no longer valid. |
| 706 | */ |
| 707 | if (h->hashed) { |
| 708 | uint32_t l2_iste = *h->l2_iste_p; |
| 709 | if (!FIELD_EX32(l2_iste, L2_ISTE, PENDING)) { |
| 710 | /* |
| 711 | * We just made this not pending: remove from hash table |
| 712 | * and write back to memory. |
| 713 | */ |
| 714 | hwaddr l2_iste_addr; |
| 715 | |
| 716 | g_hash_table_remove(cfg->lpi_cache, GINT_TO_POINTER(h->id)); |
| 717 | if (get_l2_iste_addr(cs, cfg, h->id, &l2_iste_addr)) { |
| 718 | write_l2_iste_mem(cs, cfg, l2_iste_addr, l2_iste); |
| 719 | /* Writeback errors are ignored. */ |
| 720 | } |
| 721 | } |
| 722 | return; |
| 723 | } |
| 724 | |
| 725 | if (FIELD_EX32(h->l2_iste, L2_ISTE, PENDING)) { |
| 726 | /* |
| 727 | * We just made this pending: add it to the hash table, and |
| 728 | * don't bother writing it back to memory. |
| 729 | */ |
| 730 | uint32_t *hashvalue = g_new(uint32_t, 1); |
| 731 | *hashvalue = h->l2_iste; |
| 732 | g_hash_table_insert(cfg->lpi_cache, GINT_TO_POINTER(h->id), hashvalue); |
| 733 | return; |
| 734 | } |
| 735 | write_l2_iste_mem(cs, cfg, h->l2_iste_addr, h->l2_iste); |
| 736 | } |
| 737 | |
| 738 | void gicv5_set_priority(GICv5Common *cs, uint32_t id, uint8_t priority, |
| 739 | GICv5Domain domain, GICv5IntType type, bool virtual) |
| 740 | { |
| 741 | GICv5 *s = ARM_GICV5(cs); |
| 742 | uint32_t iaffid; |
| 743 | |
| 744 | trace_gicv5_set_priority(domain_name[domain], inttype_name(type), virtual, |
| 745 | id, priority); |
| 746 | /* We must ignore unimplemented low-order priority bits */ |
| 747 | priority &= MAKE_64BIT_MASK(5 - QEMU_GICV5_PRI_BITS, QEMU_GICV5_PRI_BITS); |
| 748 | |
| 749 | if (virtual) { |
| 750 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " |
| 751 | "priority of a virtual interrupt\n"); |
| 752 | return; |
| 753 | } |
| 754 | |
| 755 | switch (type) { |
| 756 | case GICV5_LPI: |
| 757 | { |
| 758 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 759 | L2_ISTE_Handle h; |
| 760 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 761 | |
| 762 | if (!l2_iste_p) { |
| 763 | return; |
| 764 | } |
| 765 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, PRIORITY, priority); |
| 766 | iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); |
| 767 | put_l2_iste(cs, cfg, &h); |
| 768 | break; |
| 769 | } |
| 770 | case GICV5_SPI: |
| 771 | { |
| 772 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 773 | |
| 774 | if (!spi) { |
| 775 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " |
| 776 | "priority of unreachable SPI %d\n", id); |
| 777 | return; |
| 778 | } |
| 779 | |
| 780 | spi->priority = priority; |
| 781 | iaffid = spi->iaffid; |
| 782 | break; |
| 783 | } |
| 784 | default: |
| 785 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " |
| 786 | "priority of bad interrupt type %d\n", type); |
| 787 | return; |
| 788 | } |
| 789 | |
| 790 | irs_recalc_hppi(s, domain, iaffid); |
| 791 | } |
| 792 | |
| 793 | void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bool enabled, |
| 794 | GICv5Domain domain, GICv5IntType type, bool virtual) |
| 795 | { |
| 796 | GICv5 *s = ARM_GICV5(cs); |
| 797 | uint32_t iaffid; |
| 798 | |
| 799 | trace_gicv5_set_enabled(domain_name[domain], inttype_name(type), virtual, |
| 800 | id, enabled); |
| 801 | if (virtual) { |
| 802 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " |
| 803 | "enable state of a virtual interrupt\n"); |
| 804 | return; |
| 805 | } |
| 806 | |
| 807 | switch (type) { |
| 808 | case GICV5_LPI: |
| 809 | { |
| 810 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 811 | L2_ISTE_Handle h; |
| 812 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 813 | |
| 814 | if (!l2_iste_p) { |
| 815 | return; |
| 816 | } |
| 817 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, ENABLE, enabled); |
| 818 | iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); |
| 819 | put_l2_iste(cs, cfg, &h); |
| 820 | break; |
| 821 | } |
| 822 | case GICV5_SPI: |
| 823 | { |
| 824 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 825 | |
| 826 | if (!spi) { |
| 827 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " |
| 828 | "enable state of unreachable SPI %d\n", id); |
| 829 | return; |
| 830 | } |
| 831 | |
| 832 | spi->enabled = true; |
| 833 | iaffid = spi->iaffid; |
| 834 | break; |
| 835 | } |
| 836 | default: |
| 837 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " |
| 838 | "enable state of bad interrupt type %d\n", type); |
| 839 | return; |
| 840 | } |
| 841 | |
| 842 | irs_recalc_hppi(s, domain, iaffid); |
| 843 | } |
| 844 | |
| 845 | void gicv5_set_pending(GICv5Common *cs, uint32_t id, bool pending, |
| 846 | GICv5Domain domain, GICv5IntType type, bool virtual) |
| 847 | { |
| 848 | GICv5 *s = ARM_GICV5(cs); |
| 849 | uint32_t iaffid; |
| 850 | |
| 851 | trace_gicv5_set_pending(domain_name[domain], inttype_name(type), virtual, |
| 852 | id, pending); |
| 853 | if (virtual) { |
| 854 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " |
| 855 | "pending state of a virtual interrupt\n"); |
| 856 | return; |
| 857 | } |
| 858 | |
| 859 | switch (type) { |
| 860 | case GICV5_LPI: |
| 861 | { |
| 862 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 863 | L2_ISTE_Handle h; |
| 864 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 865 | |
| 866 | if (!l2_iste_p) { |
| 867 | return; |
| 868 | } |
| 869 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, pending); |
| 870 | iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); |
| 871 | put_l2_iste(cs, cfg, &h); |
| 872 | break; |
| 873 | } |
| 874 | case GICV5_SPI: |
| 875 | { |
| 876 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 877 | |
| 878 | if (!spi) { |
| 879 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " |
| 880 | "pending state of unreachable SPI %d\n", id); |
| 881 | return; |
| 882 | } |
| 883 | |
| 884 | spi->pending = true; |
| 885 | iaffid = spi->iaffid; |
| 886 | break; |
| 887 | } |
| 888 | default: |
| 889 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " |
| 890 | "pending state of bad interrupt type %d\n", type); |
| 891 | return; |
| 892 | } |
| 893 | |
| 894 | irs_recalc_hppi(s, domain, iaffid); |
| 895 | } |
| 896 | |
| 897 | void gicv5_set_handling(GICv5Common *cs, uint32_t id, |
| 898 | GICv5HandlingMode handling, GICv5Domain domain, |
| 899 | GICv5IntType type, bool virtual) |
| 900 | { |
| 901 | GICv5 *s = ARM_GICV5(cs); |
| 902 | |
| 903 | trace_gicv5_set_handling(domain_name[domain], inttype_name(type), virtual, |
| 904 | id, handling); |
| 905 | if (virtual) { |
| 906 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " |
| 907 | "handling mode of a virtual interrupt\n"); |
| 908 | return; |
| 909 | } |
| 910 | |
| 911 | switch (type) { |
| 912 | case GICV5_LPI: |
| 913 | { |
| 914 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 915 | L2_ISTE_Handle h; |
| 916 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 917 | |
| 918 | if (!l2_iste_p) { |
| 919 | return; |
| 920 | } |
| 921 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, HM, handling); |
| 922 | put_l2_iste(cs, cfg, &h); |
| 923 | break; |
| 924 | } |
| 925 | case GICV5_SPI: |
| 926 | { |
| 927 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 928 | |
| 929 | if (!spi) { |
| 930 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " |
| 931 | "priority of unreachable SPI %d\n", id); |
| 932 | return; |
| 933 | } |
| 934 | |
| 935 | spi->hm = handling; |
| 936 | break; |
| 937 | } |
| 938 | default: |
| 939 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " |
| 940 | "handling mode of bad interrupt type %d\n", type); |
| 941 | return; |
| 942 | } |
| 943 | } |
| 944 | |
| 945 | void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid, |
| 946 | GICv5RoutingMode irm, GICv5Domain domain, |
| 947 | GICv5IntType type, bool virtual) |
| 948 | { |
| 949 | GICv5 *s = ARM_GICV5(cs); |
| 950 | uint32_t old_iaffid; |
| 951 | |
| 952 | trace_gicv5_set_target(domain_name[domain], inttype_name(type), virtual, |
| 953 | id, iaffid, irm); |
| 954 | if (virtual) { |
| 955 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " |
| 956 | "target of a virtual interrupt\n"); |
| 957 | return; |
| 958 | } |
| 959 | if (irm != GICV5_TARGETED) { |
| 960 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " |
| 961 | "1-of-N routing\n"); |
| 962 | /* |
| 963 | * In the cpuif insn "GIC CDAFF", IRM is RES0 for a GIC which |
| 964 | * does not support 1-of-N routing. So warn, and fall through |
| 965 | * to treat IRM=1 the same as IRM=0. |
| 966 | */ |
| 967 | } |
| 968 | |
| 969 | switch (type) { |
| 970 | case GICV5_LPI: |
| 971 | { |
| 972 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 973 | L2_ISTE_Handle h; |
| 974 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 975 | |
| 976 | if (!l2_iste_p) { |
| 977 | return; |
| 978 | } |
| 979 | /* |
| 980 | * For QEMU we do not implement 1-of-N routing, and so |
| 981 | * L2_ISTE.IRM is RES0. We never read it, and we can skip |
| 982 | * explicitly writing it to zero here. |
| 983 | */ |
| 984 | old_iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); |
| 985 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, IAFFID, iaffid); |
| 986 | put_l2_iste(cs, cfg, &h); |
| 987 | break; |
| 988 | } |
| 989 | case GICV5_SPI: |
| 990 | { |
| 991 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 992 | |
| 993 | if (!spi) { |
| 994 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " |
| 995 | "target of unreachable SPI %d\n", id); |
| 996 | return; |
| 997 | } |
| 998 | |
| 999 | old_iaffid = spi->iaffid; |
| 1000 | spi->iaffid = iaffid; |
| 1001 | break; |
| 1002 | } |
| 1003 | default: |
| 1004 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " |
| 1005 | "target of bad interrupt type %d\n", type); |
| 1006 | return; |
| 1007 | } |
| 1008 | |
| 1009 | irs_recalc_hppi(s, domain, old_iaffid); |
| 1010 | irs_recalc_hppi(s, domain, iaffid); |
| 1011 | } |
| 1012 | |
| 1013 | static uint64_t l2_iste_to_icsr(GICv5Common *cs, const GICv5ISTConfig *cfg, |
| 1014 | uint32_t id) |
| 1015 | { |
| 1016 | uint64_t icsr = 0; |
| 1017 | const uint32_t *l2_iste_p; |
| 1018 | L2_ISTE_Handle h; |
| 1019 | |
| 1020 | l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 1021 | if (!l2_iste_p) { |
| 1022 | return R_ICSR_F_MASK; |
| 1023 | } |
| 1024 | |
| 1025 | /* |
| 1026 | * The field locations in the L2 ISTE do not line up with the |
| 1027 | * corresponding fields in the ICC_ICSR_EL1 register, so we need |
| 1028 | * to extract and deposit them individually. |
| 1029 | */ |
| 1030 | icsr = FIELD_DP64(icsr, ICSR, F, 0); |
| 1031 | icsr = FIELD_DP64(icsr, ICSR, ENABLED, FIELD_EX32(*l2_iste_p, L2_ISTE, ENABLE)); |
| 1032 | icsr = FIELD_DP64(icsr, ICSR, PENDING, FIELD_EX32(*l2_iste_p, L2_ISTE, PENDING)); |
| 1033 | icsr = FIELD_DP64(icsr, ICSR, IRM, FIELD_EX32(*l2_iste_p, L2_ISTE, IRM)); |
| 1034 | icsr = FIELD_DP64(icsr, ICSR, ACTIVE, FIELD_EX32(*l2_iste_p, L2_ISTE, ACTIVE)); |
| 1035 | icsr = FIELD_DP64(icsr, ICSR, HM, FIELD_EX32(*l2_iste_p, L2_ISTE, HM)); |
| 1036 | icsr = FIELD_DP64(icsr, ICSR, PRIORITY, FIELD_EX32(*l2_iste_p, L2_ISTE, PRIORITY)); |
| 1037 | icsr = FIELD_DP64(icsr, ICSR, IAFFID, FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID)); |
| 1038 | |
| 1039 | return icsr; |
| 1040 | } |
| 1041 | |
| 1042 | static uint64_t spi_state_to_icsr(GICv5SPIState *spi) |
| 1043 | { |
| 1044 | uint64_t icsr = 0; |
| 1045 | |
| 1046 | icsr = FIELD_DP64(icsr, ICSR, F, 0); |
| 1047 | icsr = FIELD_DP64(icsr, ICSR, ENABLED, spi->enabled); |
| 1048 | icsr = FIELD_DP64(icsr, ICSR, PENDING, spi->pending); |
| 1049 | icsr = FIELD_DP64(icsr, ICSR, IRM, spi->irm); |
| 1050 | icsr = FIELD_DP64(icsr, ICSR, ACTIVE, spi->active); |
| 1051 | icsr = FIELD_DP64(icsr, ICSR, HM, spi->hm); |
| 1052 | icsr = FIELD_DP64(icsr, ICSR, PRIORITY, spi->priority); |
| 1053 | icsr = FIELD_DP64(icsr, ICSR, IAFFID, spi->iaffid); |
| 1054 | |
| 1055 | return icsr; |
| 1056 | } |
| 1057 | |
| 1058 | uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain, |
| 1059 | GICv5IntType type, bool virtual) |
| 1060 | { |
| 1061 | GICv5 *s = ARM_GICV5(cs); |
| 1062 | uint64_t icsr; |
| 1063 | |
| 1064 | if (virtual) { |
| 1065 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to " |
| 1066 | "read config of a virtual interrupt\n"); |
| 1067 | return R_ICSR_F_MASK; |
| 1068 | } |
| 1069 | |
| 1070 | switch (type) { |
| 1071 | case GICV5_LPI: |
| 1072 | { |
| 1073 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 1074 | |
| 1075 | icsr = l2_iste_to_icsr(cs, cfg, id); |
| 1076 | trace_gicv5_request_config(domain_name[domain], inttype_name(type), |
| 1077 | virtual, id, icsr); |
| 1078 | return icsr; |
| 1079 | } |
| 1080 | case GICV5_SPI: |
| 1081 | { |
| 1082 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 1083 | |
| 1084 | if (!spi) { |
| 1085 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to " |
| 1086 | "read config of unreachable SPI %d\n", id); |
| 1087 | return R_ICSR_F_MASK; |
| 1088 | } |
| 1089 | |
| 1090 | icsr = spi_state_to_icsr(spi); |
| 1091 | trace_gicv5_request_config(domain_name[domain], inttype_name(type), |
| 1092 | virtual, id, icsr); |
| 1093 | return icsr; |
| 1094 | } |
| 1095 | default: |
| 1096 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to " |
| 1097 | "read config of bad interrupt type %d\n", type); |
| 1098 | return R_ICSR_F_MASK; |
| 1099 | } |
| 1100 | } |
| 1101 | |
| 1102 | void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain, |
| 1103 | GICv5IntType type, bool virtual) |
| 1104 | { |
| 1105 | GICv5 *s = ARM_GICV5(cs); |
| 1106 | uint32_t iaffid; |
| 1107 | |
| 1108 | trace_gicv5_activate(domain_name[domain], inttype_name(type), virtual, id); |
| 1109 | |
| 1110 | if (virtual) { |
| 1111 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " |
| 1112 | "activate a virtual interrupt\n"); |
| 1113 | return; |
| 1114 | } |
| 1115 | |
| 1116 | switch (type) { |
| 1117 | case GICV5_LPI: |
| 1118 | { |
| 1119 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 1120 | L2_ISTE_Handle h; |
| 1121 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 1122 | |
| 1123 | if (!l2_iste_p) { |
| 1124 | return; |
| 1125 | } |
| 1126 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, true); |
| 1127 | if (FIELD_EX32(*l2_iste_p, L2_ISTE, HM) == GICV5_EDGE) { |
| 1128 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, false); |
| 1129 | } |
| 1130 | iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); |
| 1131 | put_l2_iste(cs, cfg, &h); |
| 1132 | break; |
| 1133 | } |
| 1134 | case GICV5_SPI: |
| 1135 | { |
| 1136 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 1137 | |
| 1138 | if (!spi) { |
| 1139 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " |
| 1140 | "activate unreachable SPI %d\n", id); |
| 1141 | return; |
| 1142 | } |
| 1143 | |
| 1144 | spi->active = true; |
| 1145 | if (spi->hm == GICV5_EDGE) { |
| 1146 | spi->pending = false; |
| 1147 | } |
| 1148 | iaffid = spi->iaffid; |
| 1149 | break; |
| 1150 | } |
| 1151 | default: |
| 1152 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " |
| 1153 | "activate bad interrupt type %d\n", type); |
| 1154 | return; |
| 1155 | } |
| 1156 | |
| 1157 | irs_recalc_hppi(s, domain, iaffid); |
| 1158 | } |
| 1159 | |
| 1160 | void gicv5_deactivate(GICv5Common *cs, uint32_t id, GICv5Domain domain, |
| 1161 | GICv5IntType type, bool virtual) |
| 1162 | { |
| 1163 | GICv5 *s = ARM_GICV5(cs); |
| 1164 | uint32_t iaffid; |
| 1165 | |
| 1166 | trace_gicv5_deactivate(domain_name[domain], inttype_name(type), virtual, id); |
| 1167 | |
| 1168 | if (virtual) { |
| 1169 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to " |
| 1170 | "deactivate a virtual interrupt\n"); |
| 1171 | return; |
| 1172 | } |
| 1173 | |
| 1174 | switch (type) { |
| 1175 | case GICV5_LPI: |
| 1176 | { |
| 1177 | const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 1178 | L2_ISTE_Handle h; |
| 1179 | uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h); |
| 1180 | |
| 1181 | if (!l2_iste_p) { |
| 1182 | return; |
| 1183 | } |
| 1184 | *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, false); |
| 1185 | iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); |
| 1186 | put_l2_iste(cs, cfg, &h); |
| 1187 | break; |
| 1188 | } |
| 1189 | case GICV5_SPI: |
| 1190 | { |
| 1191 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 1192 | |
| 1193 | if (!spi) { |
| 1194 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to " |
| 1195 | "deactivate unreachable SPI %d\n", id); |
| 1196 | return; |
| 1197 | } |
| 1198 | |
| 1199 | spi->active = false; |
| 1200 | iaffid = spi->iaffid; |
| 1201 | break; |
| 1202 | } |
| 1203 | default: |
| 1204 | qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to " |
| 1205 | "deactivate bad interrupt type %d\n", type); |
| 1206 | return; |
| 1207 | } |
| 1208 | |
| 1209 | irs_recalc_hppi(s, domain, iaffid); |
| 1210 | } |
| 1211 | |
| 1212 | static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value) |
| 1213 | { |
| 1214 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 1215 | GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 1216 | uint32_t intid = FIELD_EX32(value, IRS_MAP_L2_ISTR, ID); |
| 1217 | hwaddr l1_addr; |
| 1218 | uint64_t l1_iste; |
| 1219 | MemTxResult res; |
| 1220 | |
| 1221 | if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || |
| 1222 | !cfg->structure) { |
| 1223 | /* WI if no IST set up or it is not 2-level */ |
| 1224 | return; |
| 1225 | } |
| 1226 | |
| 1227 | /* Find the relevant L1 ISTE and set its VALID bit */ |
| 1228 | l1_addr = l1_iste_addr(cs, cfg, intid); |
| 1229 | |
| 1230 | l1_iste = address_space_ldq_le(&cs->dma_as, l1_addr, cfg->txattrs, &res); |
| 1231 | if (res != MEMTX_OK) { |
| 1232 | goto txfail; |
| 1233 | } |
| 1234 | |
| 1235 | l1_iste = FIELD_DP64(l1_iste, L1_ISTE, VALID, 1); |
| 1236 | |
| 1237 | address_space_stq_le(&cs->dma_as, l1_addr, l1_iste, cfg->txattrs, &res); |
| 1238 | if (res != MEMTX_OK) { |
| 1239 | goto txfail; |
| 1240 | } |
| 1241 | /* |
| 1242 | * It's CONSTRAINED UNPREDICTABLE to make an L2 IST valid when |
| 1243 | * some of its entries have Pending already set, so we don't need |
| 1244 | * to go through looking for Pending bits and pulling them into |
| 1245 | * the cache, and we don't need to recalc our HPPI. |
| 1246 | */ |
| 1247 | return; |
| 1248 | |
| 1249 | txfail: |
| 1250 | /* Reportable with EC=0x0 if sw error reporting implemented */ |
| 1251 | qemu_log_mask(LOG_GUEST_ERROR, "L1 ISTE update failed for ID 0x%x at " |
| 1252 | "physical address 0x" HWADDR_FMT_plx "\n", intid, l1_addr); |
| 1253 | } |
| 1254 | |
| 1255 | /* Data we need to pass through to irs_clean_lpi_cache_entry() */ |
| 1256 | typedef struct CleanLPICacheUserData { |
| 1257 | GICv5Common *cs; |
| 1258 | GICv5ISTConfig *cfg; |
| 1259 | } CleanLPICacheUserData; |
| 1260 | |
| 1261 | static gboolean irs_clean_lpi_cache_entry(gpointer key, gpointer value, |
| 1262 | gpointer user_data) |
| 1263 | { |
| 1264 | /* Drop this entry from the LPI cache, writing it back to guest memory. */ |
| 1265 | CleanLPICacheUserData *ud = user_data; |
| 1266 | hwaddr l2_iste_addr; |
| 1267 | uint64_t id = GPOINTER_TO_INT(key); |
| 1268 | uint32_t l2_iste = *(uint32_t *)value; |
| 1269 | |
| 1270 | if (!get_l2_iste_addr(ud->cs, ud->cfg, id, &l2_iste_addr) || |
| 1271 | !write_l2_iste_mem(ud->cs, ud->cfg, l2_iste_addr, l2_iste)) { |
| 1272 | /* We drop the cached entry regardless of writeback errors */ |
| 1273 | return true; |
| 1274 | } |
| 1275 | return true; |
| 1276 | } |
| 1277 | |
| 1278 | static void irs_clean_lpi_cache(GICv5Common *cs, GICv5ISTConfig *cfg) |
| 1279 | { |
| 1280 | /* Write everything in the LPI cache out to guest memory */ |
| 1281 | CleanLPICacheUserData ud; |
| 1282 | ud.cs = cs; |
| 1283 | ud.cfg = cfg; |
| 1284 | |
| 1285 | g_hash_table_foreach_remove(cfg->lpi_cache, irs_clean_lpi_cache_entry, &ud); |
| 1286 | } |
| 1287 | |
| 1288 | static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value) |
| 1289 | { |
| 1290 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 1291 | |
| 1292 | if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { |
| 1293 | /* If VALID is set, ADDR is RO and we can only update VALID */ |
| 1294 | bool valid = FIELD_EX64(value, IRS_IST_BASER, VALID); |
| 1295 | if (valid) { |
| 1296 | /* Ignore 1->1 transition */ |
| 1297 | return; |
| 1298 | } |
| 1299 | irs_clean_lpi_cache(cs, &s->phys_lpi_config[domain]); |
| 1300 | cs->irs_ist_baser[domain] = FIELD_DP64(cs->irs_ist_baser[domain], |
| 1301 | IRS_IST_BASER, VALID, valid); |
| 1302 | s->phys_lpi_config[domain].valid = false; |
| 1303 | trace_gicv5_ist_invalid(domain_name[domain]); |
| 1304 | irs_recalc_hppi_all_cpus(s, domain); |
| 1305 | return; |
| 1306 | } |
| 1307 | cs->irs_ist_baser[domain] = value; |
| 1308 | |
| 1309 | if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { |
| 1310 | /* |
| 1311 | * If the guest just set VALID then capture data into config struct, |
| 1312 | * sanitize the reserved values, and expand fields out into byte counts. |
| 1313 | */ |
| 1314 | GICv5ISTConfig *cfg = &s->phys_lpi_config[domain]; |
| 1315 | uint8_t istbits, l2bits, l2_idx_bits; |
| 1316 | uint8_t id_bits = FIELD_EX64(cs->irs_ist_cfgr[domain], |
| 1317 | IRS_IST_CFGR, LPI_ID_BITS); |
| 1318 | id_bits = MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GICV5_ID_BITS); |
| 1319 | |
| 1320 | switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, ISTSZ)) { |
| 1321 | case 0: |
| 1322 | case 3: /* reserved: acts like the minimum required size */ |
| 1323 | istbits = 2; |
| 1324 | break; |
| 1325 | case 1: |
| 1326 | istbits = 3; |
| 1327 | break; |
| 1328 | case 2: |
| 1329 | istbits = 4; |
| 1330 | break; |
| 1331 | default: |
| 1332 | g_assert_not_reached(); |
| 1333 | } |
| 1334 | switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, L2SZ)) { |
| 1335 | case 0: |
| 1336 | case 3: /* reserved; CONSTRAINED UNPREDICTABLE */ |
| 1337 | l2bits = 12; /* 4K: 12 bits */ |
| 1338 | break; |
| 1339 | case 1: |
| 1340 | l2bits = 14; /* 16K: 14 bits */ |
| 1341 | break; |
| 1342 | case 2: |
| 1343 | l2bits = 16; /* 64K: 16 bits */ |
| 1344 | break; |
| 1345 | default: |
| 1346 | g_assert_not_reached(); |
| 1347 | } |
| 1348 | /* |
| 1349 | * Calculate how many bits of an ID index the L2 table |
| 1350 | * (e.g. if we need 14 bits to index each byte in a 16K L2 table, |
| 1351 | * but each entry is 4 bytes wide then we need 14 - 2 = 12 bits |
| 1352 | * to index an entry in the table). |
| 1353 | */ |
| 1354 | l2_idx_bits = l2bits - istbits; |
| 1355 | cfg->base = cs->irs_ist_baser[domain] & R_IRS_IST_BASER_ADDR_MASK; |
| 1356 | cfg->txattrs = irs_txattrs(cs, domain), |
| 1357 | cfg->id_bits = id_bits; |
| 1358 | cfg->istsz = 1 << istbits; |
| 1359 | cfg->l2_idx_bits = l2_idx_bits; |
| 1360 | cfg->structure = FIELD_EX64(cs->irs_ist_cfgr[domain], |
| 1361 | IRS_IST_CFGR, STRUCTURE); |
| 1362 | if (!cfg->lpi_cache) { |
| 1363 | /* |
| 1364 | * Keys are GINT_TO_POINTER(intid), so we want the g_direct_hash |
| 1365 | * and g_direct_equal hash and equality functions. We don't |
| 1366 | * want to free the keys, but we do want to free the values |
| 1367 | * (which are pointer-to-uint32_t). |
| 1368 | */ |
| 1369 | cfg->lpi_cache = g_hash_table_new_full(NULL, NULL, NULL, g_free); |
| 1370 | } |
| 1371 | cfg->valid = true; |
| 1372 | trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits, |
| 1373 | cfg->l2_idx_bits, cfg->istsz, cfg->structure); |
| 1374 | irs_recalc_hppi_all_cpus(s, domain); |
| 1375 | } |
| 1376 | } |
| 1377 | |
| 1378 | static void spi_sample(GICv5SPIState *spi) |
| 1379 | { |
| 1380 | /* |
| 1381 | * Sample the state of the SPI input line; this generates |
| 1382 | * SET_EDGE, SET_LEVEL or CLEAR events which update the SPI's |
| 1383 | * pending state and handling mode per R_HHKMN. The logic is the |
| 1384 | * same for "the input line changed" (R_QBXXV) and "software asked |
| 1385 | * us to resample" (R_DMTFM). |
| 1386 | */ |
| 1387 | if (spi->level) { |
| 1388 | /* |
| 1389 | * SET_LEVEL or SET_EDGE: interrupt becomes pending, and the |
| 1390 | * handling mode is updated to match the trigger mode. |
| 1391 | */ |
| 1392 | spi->pending = true; |
| 1393 | spi->hm = spi->tm == GICV5_TRIGGER_EDGE ? GICV5_EDGE : GICV5_LEVEL; |
| 1394 | } else if (spi->tm == GICV5_TRIGGER_LEVEL) { |
| 1395 | /* falling edges only trigger a CLEAR event for level-triggered */ |
| 1396 | spi->pending = false; |
| 1397 | } |
| 1398 | } |
| 1399 | |
| 1400 | static bool irs_pe_selr_valid(GICv5Common *cs, GICv5Domain domain) |
| 1401 | { |
| 1402 | /* |
| 1403 | * Return true if IRS_PE_SELR has a valid AFFID in it. We don't |
| 1404 | * expect the guest to do this except perhaps once at startup, so |
| 1405 | * do a simple linear scan through the cpu_iaffids array. |
| 1406 | */ |
| 1407 | for (int i = 0; i < cs->num_cpu_iaffids; i++) { |
| 1408 | if (cs->irs_pe_selr[domain] == cs->cpu_iaffids[i]) { |
| 1409 | return true; |
| 1410 | } |
| 1411 | } |
| 1412 | return false; |
| 1413 | } |
| 1414 | |
| 1415 | static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, |
| 1416 | uint64_t *data, MemTxAttrs attrs) |
| 1417 | { |
| 1418 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 1419 | uint32_t v = 0; |
| 1420 | |
| 1421 | switch (offset) { |
| 1422 | case A_IRS_IDR0: |
| 1423 | v = cs->irs_idr0; |
| 1424 | /* INT_DOM reports the domain this register is for */ |
| 1425 | v = FIELD_DP32(v, IRS_IDR0, INT_DOM, domain); |
| 1426 | if (domain != GICV5_ID_REALM) { |
| 1427 | /* MEC field RES0 except for the Realm domain */ |
| 1428 | v &= ~R_IRS_IDR0_MEC_MASK; |
| 1429 | } |
| 1430 | if (domain == GICV5_ID_EL3) { |
| 1431 | /* VIRT is RES0 for EL3 domain */ |
| 1432 | v &= ~R_IRS_IDR0_VIRT_MASK; |
| 1433 | /* ...which means VIRT_ONE_N is also RES0 */ |
| 1434 | v &= ~R_IRS_IDR0_VIRT_ONE_N_MASK; |
| 1435 | } |
| 1436 | return true; |
| 1437 | |
| 1438 | case A_IRS_IDR1: |
| 1439 | *data = cs->irs_idr1; |
| 1440 | return true; |
| 1441 | |
| 1442 | case A_IRS_IDR2: |
| 1443 | *data = cs->irs_idr2; |
| 1444 | return true; |
| 1445 | |
| 1446 | case A_IRS_IDR3: |
| 1447 | /* In EL3 IDR0.VIRT is 0 so this is RES0 */ |
| 1448 | *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr3; |
| 1449 | return true; |
| 1450 | |
| 1451 | case A_IRS_IDR4: |
| 1452 | /* In EL3 IDR0.VIRT is 0 so this is RES0 */ |
| 1453 | *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr4; |
| 1454 | return true; |
| 1455 | |
| 1456 | case A_IRS_IDR5: |
| 1457 | *data = cs->irs_idr5; |
| 1458 | return true; |
| 1459 | |
| 1460 | case A_IRS_IDR6: |
| 1461 | *data = cs->irs_idr6; |
| 1462 | return true; |
| 1463 | |
| 1464 | case A_IRS_IDR7: |
| 1465 | *data = cs->irs_idr7; |
| 1466 | return true; |
| 1467 | |
| 1468 | case A_IRS_IIDR: |
| 1469 | *data = cs->irs_iidr; |
| 1470 | return true; |
| 1471 | |
| 1472 | case A_IRS_AIDR: |
| 1473 | *data = cs->irs_aidr; |
| 1474 | return true; |
| 1475 | |
| 1476 | case A_IRS_IST_BASER: |
| 1477 | *data = extract64(cs->irs_ist_baser[domain], 0, 32); |
| 1478 | return true; |
| 1479 | |
| 1480 | case A_IRS_IST_BASER + 4: |
| 1481 | *data = extract64(cs->irs_ist_baser[domain], 32, 32); |
| 1482 | return true; |
| 1483 | |
| 1484 | case A_IRS_IST_STATUSR: |
| 1485 | /* |
| 1486 | * For QEMU writes to IRS_IST_BASER and IRS_MAP_L2_ISTR take effect |
| 1487 | * instantaneously, and the guest can never see the IDLE bit as 0. |
| 1488 | */ |
| 1489 | *data = R_IRS_IST_STATUSR_IDLE_MASK; |
| 1490 | return true; |
| 1491 | |
| 1492 | case A_IRS_IST_CFGR: |
| 1493 | *data = cs->irs_ist_cfgr[domain]; |
| 1494 | return true; |
| 1495 | |
| 1496 | case A_IRS_SPI_STATUSR: |
| 1497 | /* |
| 1498 | * QEMU writes to IRS_SPI_{CFGR,DOMAINR,SELR,VMR} take effect |
| 1499 | * instantaneously, so the guest can never see the IDLE bit as 0. |
| 1500 | */ |
| 1501 | v = FIELD_DP32(v, IRS_SPI_STATUSR, V, |
| 1502 | spi_for_selr(cs, domain) != NULL); |
| 1503 | v = FIELD_DP32(v, IRS_SPI_STATUSR, IDLE, 1); |
| 1504 | *data = v; |
| 1505 | return true; |
| 1506 | |
| 1507 | case A_IRS_SPI_CFGR: |
| 1508 | { |
| 1509 | GICv5SPIState *spi = spi_for_selr(cs, domain); |
| 1510 | |
| 1511 | if (spi) { |
| 1512 | v = FIELD_DP32(v, IRS_SPI_CFGR, TM, spi->tm); |
| 1513 | } |
| 1514 | *data = v; |
| 1515 | return true; |
| 1516 | } |
| 1517 | case A_IRS_SPI_DOMAINR: |
| 1518 | if (domain == GICV5_ID_EL3) { |
| 1519 | /* This is RAZ/WI except for the EL3 domain */ |
| 1520 | GICv5SPIState *spi = spi_for_selr(cs, domain); |
| 1521 | if (spi) { |
| 1522 | v = FIELD_DP32(v, IRS_SPI_DOMAINR, DOMAIN, spi->domain); |
| 1523 | } |
| 1524 | } |
| 1525 | *data = v; |
| 1526 | return true; |
| 1527 | case A_IRS_CR0: |
| 1528 | /* Enabling is instantaneous for us so IDLE is always 1 */ |
| 1529 | *data = cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK; |
| 1530 | if (FIELD_EX32(cs->irs_cr0[domain], IRS_CR0, IRSEN)) { |
| 1531 | irs_recalc_hppi_all_cpus(s, domain); |
| 1532 | } else { |
| 1533 | irs_recall_hppis(s, domain); |
| 1534 | } |
| 1535 | return true; |
| 1536 | case A_IRS_CR1: |
| 1537 | *data = cs->irs_cr1[domain]; |
| 1538 | return true; |
| 1539 | case A_IRS_SYNC_STATUSR: |
| 1540 | /* Sync is a no-op for QEMU: we are always IDLE */ |
| 1541 | *data = R_IRS_SYNC_STATUSR_IDLE_MASK; |
| 1542 | return true; |
| 1543 | case A_IRS_PE_SELR: |
| 1544 | *data = cs->irs_pe_selr[domain]; |
| 1545 | return true; |
| 1546 | case A_IRS_PE_CR0: |
| 1547 | /* We don't implement 1ofN, so this is RAZ/WI for us */ |
| 1548 | *data = 0; |
| 1549 | return true; |
| 1550 | case A_IRS_PE_STATUSR: |
| 1551 | /* |
| 1552 | * Our CPUs are always online, so we're really just reporting |
| 1553 | * whether the guest wrote a valid AFFID to IRS_PE_SELR |
| 1554 | */ |
| 1555 | v = R_IRS_PE_STATUSR_IDLE_MASK; |
| 1556 | if (irs_pe_selr_valid(cs, domain)) { |
| 1557 | v |= R_IRS_PE_STATUSR_V_MASK | R_IRS_PE_STATUSR_ONLINE_MASK; |
| 1558 | } |
| 1559 | *data = v; |
| 1560 | return true; |
| 1561 | case A_IRS_DEVARCH: |
| 1562 | *data = IRS_DEVARCH_VALUE; |
| 1563 | return true; |
| 1564 | case A_IRS_IDREGS ... A_IRS_IDREGS + 0x2f: |
| 1565 | /* CoreSight ID registers */ |
| 1566 | *data = gicv5_idreg(offset - A_IRS_IDREGS); |
| 1567 | return true; |
| 1568 | } |
| 1569 | |
| 1570 | return false; |
| 1571 | } |
| 1572 | |
| 1573 | static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, |
| 1574 | uint64_t data, MemTxAttrs attrs) |
| 1575 | { |
| 1576 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 1577 | |
| 1578 | switch (offset) { |
| 1579 | case A_IRS_IST_BASER: |
| 1580 | irs_ist_baser_write(s, domain, |
| 1581 | deposit64(cs->irs_ist_baser[domain], 0, 32, data)); |
| 1582 | return true; |
| 1583 | case A_IRS_IST_BASER + 4: |
| 1584 | irs_ist_baser_write(s, domain, |
| 1585 | deposit64(cs->irs_ist_baser[domain], 32, 32, data)); |
| 1586 | return true; |
| 1587 | case A_IRS_IST_CFGR: |
| 1588 | if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { |
| 1589 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1590 | "guest tried to write IRS_IST_CFGR for %s config frame " |
| 1591 | "while IST_BASER.VALID set\n", domain_name[domain]); |
| 1592 | } else { |
| 1593 | cs->irs_ist_cfgr[domain] = data; |
| 1594 | } |
| 1595 | return true; |
| 1596 | case A_IRS_MAP_L2_ISTR: |
| 1597 | irs_map_l2_istr_write(s, domain, data); |
| 1598 | return true; |
| 1599 | case A_IRS_SPI_SELR: |
| 1600 | cs->irs_spi_selr[domain] = data; |
| 1601 | return true; |
| 1602 | case A_IRS_SPI_CFGR: |
| 1603 | { |
| 1604 | GICv5SPIState *spi = spi_for_selr(cs, domain); |
| 1605 | if (spi) { |
| 1606 | GICv5TriggerMode old_tm = spi->tm; |
| 1607 | spi->tm = FIELD_EX32(data, IRS_SPI_CFGR, TM); |
| 1608 | if (spi->tm != old_tm) { |
| 1609 | /* |
| 1610 | * R_KBPXL: updates to SPI trigger mode can generate CLEAR or |
| 1611 | * SET_LEVEL events. This is not the same logic as spi_sample(). |
| 1612 | */ |
| 1613 | if (spi->tm == GICV5_TRIGGER_LEVEL) { |
| 1614 | if (spi->level) { |
| 1615 | spi->pending = true; |
| 1616 | spi->hm = GICV5_LEVEL; |
| 1617 | } else { |
| 1618 | spi->pending = false; |
| 1619 | } |
| 1620 | } else if (spi->level) { |
| 1621 | spi->pending = false; |
| 1622 | } |
| 1623 | irs_recalc_hppi(s, spi->domain, spi->iaffid); |
| 1624 | } |
| 1625 | } |
| 1626 | return true; |
| 1627 | } |
| 1628 | case A_IRS_SPI_DOMAINR: |
| 1629 | if (domain == GICV5_ID_EL3) { |
| 1630 | /* this is RAZ/WI except for the EL3 domain */ |
| 1631 | GICv5SPIState *spi = spi_for_selr(cs, domain); |
| 1632 | if (spi) { |
| 1633 | GICv5Domain old_domain = spi->domain; |
| 1634 | spi->domain = FIELD_EX32(data, IRS_SPI_DOMAINR, DOMAIN); |
| 1635 | if (spi->domain != old_domain) { |
| 1636 | irs_recalc_hppi(s, old_domain, spi->iaffid); |
| 1637 | irs_recalc_hppi(s, spi->domain, spi->iaffid); |
| 1638 | } |
| 1639 | } |
| 1640 | } |
| 1641 | return true; |
| 1642 | case A_IRS_SPI_RESAMPLER: |
| 1643 | { |
| 1644 | uint32_t id = FIELD_EX32(data, IRS_SPI_RESAMPLER, SPI_ID); |
| 1645 | GICv5SPIState *spi = gicv5_spi_state(cs, id, domain); |
| 1646 | |
| 1647 | if (spi) { |
| 1648 | spi_sample(spi); |
| 1649 | irs_recalc_hppi(s, spi->domain, spi->iaffid); |
| 1650 | trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active); |
| 1651 | } |
| 1652 | return true; |
| 1653 | } |
| 1654 | case A_IRS_CR0: |
| 1655 | cs->irs_cr0[domain] = data & R_IRS_CR0_IRSEN_MASK; |
| 1656 | return true; |
| 1657 | case A_IRS_CR1: |
| 1658 | cs->irs_cr1[domain] = data; |
| 1659 | return true; |
| 1660 | case A_IRS_SYNCR: |
| 1661 | /* Sync is a no-op for QEMU: ignore write */ |
| 1662 | return true; |
| 1663 | case A_IRS_PE_SELR: |
| 1664 | cs->irs_pe_selr[domain] = data; |
| 1665 | return true; |
| 1666 | case A_IRS_PE_CR0: |
| 1667 | /* We don't implement 1ofN, so this is RAZ/WI for us */ |
| 1668 | return true; |
| 1669 | } |
| 1670 | |
| 1671 | return false; |
| 1672 | } |
| 1673 | |
| 1674 | static bool config_readll(GICv5 *s, GICv5Domain domain, hwaddr offset, |
| 1675 | uint64_t *data, MemTxAttrs attrs) |
| 1676 | { |
| 1677 | GICv5Common *cs = ARM_GICV5_COMMON(s); |
| 1678 | |
| 1679 | switch (offset) { |
| 1680 | case A_IRS_IST_BASER: |
| 1681 | *data = cs->irs_ist_baser[domain]; |
| 1682 | return true; |
| 1683 | } |
| 1684 | |
| 1685 | return false; |
| 1686 | } |
| 1687 | |
| 1688 | static bool config_writell(GICv5 *s, GICv5Domain domain, hwaddr offset, |
| 1689 | uint64_t data, MemTxAttrs attrs) |
| 1690 | { |
| 1691 | switch (offset) { |
| 1692 | case A_IRS_IST_BASER: |
| 1693 | irs_ist_baser_write(s, domain, data); |
| 1694 | return true; |
| 1695 | } |
| 1696 | |
| 1697 | return false; |
| 1698 | } |
| 1699 | |
| 1700 | static MemTxResult config_read(void *opaque, GICv5Domain domain, hwaddr offset, |
| 1701 | uint64_t *data, unsigned size, |
| 1702 | MemTxAttrs attrs) |
| 1703 | { |
| 1704 | GICv5 *s = ARM_GICV5(opaque); |
| 1705 | bool result; |
| 1706 | |
| 1707 | switch (size) { |
| 1708 | case 4: |
| 1709 | result = config_readl(s, domain, offset, data, attrs); |
| 1710 | break; |
| 1711 | case 8: |
| 1712 | result = config_readll(s, domain, offset, data, attrs); |
| 1713 | break; |
| 1714 | default: |
| 1715 | result = false; |
| 1716 | break; |
| 1717 | } |
| 1718 | |
| 1719 | if (!result) { |
| 1720 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1721 | "%s: invalid guest read for IRS %s config frame " |
| 1722 | "at offset " HWADDR_FMT_plx |
| 1723 | " size %u\n", __func__, domain_name[domain], |
| 1724 | offset, size); |
| 1725 | trace_gicv5_badread(domain_name[domain], offset, size); |
| 1726 | /* |
| 1727 | * The spec requires that reserved registers are RAZ/WI; so we |
| 1728 | * log the error but return MEMTX_OK so we don't cause a |
| 1729 | * spurious data abort. |
| 1730 | */ |
| 1731 | *data = 0; |
| 1732 | } else { |
| 1733 | trace_gicv5_read(domain_name[domain], offset, *data, size); |
| 1734 | } |
| 1735 | |
| 1736 | return MEMTX_OK; |
| 1737 | } |
| 1738 | |
| 1739 | static MemTxResult config_write(void *opaque, GICv5Domain domain, |
| 1740 | hwaddr offset, uint64_t data, unsigned size, |
| 1741 | MemTxAttrs attrs) |
| 1742 | { |
| 1743 | GICv5 *s = ARM_GICV5(opaque); |
| 1744 | bool result; |
| 1745 | |
| 1746 | switch (size) { |
| 1747 | case 4: |
| 1748 | result = config_writel(s, domain, offset, data, attrs); |
| 1749 | break; |
| 1750 | case 8: |
| 1751 | result = config_writell(s, domain, offset, data, attrs); |
| 1752 | break; |
| 1753 | default: |
| 1754 | result = false; |
| 1755 | break; |
| 1756 | } |
| 1757 | |
| 1758 | if (!result) { |
| 1759 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1760 | "%s: invalid guest write for IRS %s config frame " |
| 1761 | "at offset " HWADDR_FMT_plx |
| 1762 | " size %u\n", __func__, domain_name[domain], |
| 1763 | offset, size); |
| 1764 | trace_gicv5_badwrite(domain_name[domain], offset, data, size); |
| 1765 | /* |
| 1766 | * The spec requires that reserved registers are RAZ/WI; so we |
| 1767 | * log the error but return MEMTX_OK so we don't cause a |
| 1768 | * spurious data abort. |
| 1769 | */ |
| 1770 | } else { |
| 1771 | trace_gicv5_write(domain_name[domain], offset, data, size); |
| 1772 | } |
| 1773 | |
| 1774 | return MEMTX_OK; |
| 1775 | } |
| 1776 | |
| 1777 | #define DEFINE_READ_WRITE_WRAPPERS(NAME, DOMAIN) \ |
| 1778 | static MemTxResult config_##NAME##_read(void *opaque, hwaddr offset, \ |
| 1779 | uint64_t *data, unsigned size, \ |
| 1780 | MemTxAttrs attrs) \ |
| 1781 | { \ |
| 1782 | return config_read(opaque, DOMAIN, offset, data, size, attrs); \ |
| 1783 | } \ |
| 1784 | static MemTxResult config_##NAME##_write(void *opaque, hwaddr offset, \ |
| 1785 | uint64_t data, unsigned size, \ |
| 1786 | MemTxAttrs attrs) \ |
| 1787 | { \ |
| 1788 | return config_write(opaque, DOMAIN, offset, data, size, attrs); \ |
| 1789 | } |
| 1790 | |
| 1791 | DEFINE_READ_WRITE_WRAPPERS(ns, GICV5_ID_NS) |
| 1792 | DEFINE_READ_WRITE_WRAPPERS(realm, GICV5_ID_REALM) |
| 1793 | DEFINE_READ_WRITE_WRAPPERS(secure, GICV5_ID_S) |
| 1794 | DEFINE_READ_WRITE_WRAPPERS(el3, GICV5_ID_EL3) |
| 1795 | |
| 1796 | #define FRAME_OP_ENTRY(NAME, DOMAIN) \ |
| 1797 | [DOMAIN] = { \ |
| 1798 | .read_with_attrs = config_##NAME##_read, \ |
| 1799 | .write_with_attrs = config_##NAME##_write, \ |
| 1800 | .endianness = DEVICE_LITTLE_ENDIAN, \ |
| 1801 | .valid.min_access_size = 4, \ |
| 1802 | .valid.max_access_size = 8, \ |
| 1803 | .impl.min_access_size = 4, \ |
| 1804 | .impl.max_access_size = 8, \ |
| 1805 | } |
| 1806 | |
| 1807 | static const MemoryRegionOps config_frame_ops[NUM_GICV5_DOMAINS] = { |
| 1808 | FRAME_OP_ENTRY(ns, GICV5_ID_NS), |
| 1809 | FRAME_OP_ENTRY(realm, GICV5_ID_REALM), |
| 1810 | FRAME_OP_ENTRY(secure, GICV5_ID_S), |
| 1811 | FRAME_OP_ENTRY(el3, GICV5_ID_EL3), |
| 1812 | }; |
| 1813 | |
| 1814 | static void gicv5_set_spi(void *opaque, int irq, int level) |
| 1815 | { |
| 1816 | /* These irqs are all SPIs; the INTID is irq + s->spi_base */ |
| 1817 | GICv5Common *cs = ARM_GICV5_COMMON(opaque); |
| 1818 | GICv5 *s = ARM_GICV5(cs); |
| 1819 | uint32_t spi_id = irq + cs->spi_base; |
| 1820 | GICv5SPIState *spi = gicv5_raw_spi_state(cs, spi_id); |
| 1821 | |
| 1822 | if (!spi || spi->level == level) { |
| 1823 | return; |
| 1824 | } |
| 1825 | |
| 1826 | trace_gicv5_spi(spi_id, level); |
| 1827 | |
| 1828 | spi->level = level; |
| 1829 | spi_sample(spi); |
| 1830 | trace_gicv5_spi_state(spi_id, spi->level, spi->pending, spi->active); |
| 1831 | |
| 1832 | irs_recalc_hppi(s, spi->domain, spi->iaffid); |
| 1833 | } |
| 1834 | |
| 1835 | static void gicv5_reset_hold(Object *obj, ResetType type) |
| 1836 | { |
| 1837 | GICv5 *s = ARM_GICV5(obj); |
| 1838 | GICv5Class *c = ARM_GICV5_GET_CLASS(s); |
| 1839 | |
| 1840 | if (c->parent_phases.hold) { |
| 1841 | c->parent_phases.hold(obj, type); |
| 1842 | } |
| 1843 | |
| 1844 | /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */ |
| 1845 | for (int i = 0; i < NUM_GICV5_DOMAINS; i++) { |
| 1846 | s->phys_lpi_config[i].valid = false; |
| 1847 | /* |
| 1848 | * If we got reset (power-cycled) with data in the cache, don't |
| 1849 | * write it out to guest memory; just return to "empty cache". |
| 1850 | */ |
| 1851 | if (s->phys_lpi_config[i].lpi_cache) { |
| 1852 | g_hash_table_remove_all(s->phys_lpi_config[i].lpi_cache); |
| 1853 | } |
| 1854 | } |
| 1855 | } |
| 1856 | |
| 1857 | static void gicv5_set_idregs(GICv5Common *cs) |
| 1858 | { |
| 1859 | /* Set the ID register value fields */ |
| 1860 | uint32_t v; |
| 1861 | |
| 1862 | /* |
| 1863 | * Fields in IDR0 for optional parts of the spec that we don't |
| 1864 | * implement are 0. |
| 1865 | */ |
| 1866 | v = 0; |
| 1867 | /* |
| 1868 | * We can handle physical addresses of any size, so report support |
| 1869 | * for 56 bits of physical address space. |
| 1870 | */ |
| 1871 | v = FIELD_DP32(v, IRS_IDR0, PA_RANGE, 7); |
| 1872 | v = FIELD_DP32(v, IRS_IDR0, IRSID, cs->irsid); |
| 1873 | cs->irs_idr0 = v; |
| 1874 | |
| 1875 | v = 0; |
| 1876 | v = FIELD_DP32(v, IRS_IDR1, PE_CNT, cs->num_cpus); |
| 1877 | v = FIELD_DP32(v, IRS_IDR1, IAFFID_BITS, QEMU_GICV5_IAFFID_BITS - 1); |
| 1878 | v = FIELD_DP32(v, IRS_IDR1, PRI_BITS, QEMU_GICV5_PRI_BITS - 1); |
| 1879 | cs->irs_idr1 = v; |
| 1880 | |
| 1881 | v = 0; |
| 1882 | /* We always support physical LPIs with 2-level ISTs of all sizes */ |
| 1883 | v = FIELD_DP32(v, IRS_IDR2, ID_BITS, QEMU_GICV5_ID_BITS); |
| 1884 | v = FIELD_DP32(v, IRS_IDR2, LPI, 1); |
| 1885 | v = FIELD_DP32(v, IRS_IDR2, MIN_LPI_ID_BITS, QEMU_GICV5_MIN_LPI_ID_BITS); |
| 1886 | v = FIELD_DP32(v, IRS_IDR2, IST_LEVELS, 1); |
| 1887 | v = FIELD_DP32(v, IRS_IDR2, IST_L2SZ, 7); |
| 1888 | /* Our impl does not need IST metadata, so ISTMD and ISTMD_SZ are 0 */ |
| 1889 | cs->irs_idr2 = v; |
| 1890 | |
| 1891 | /* We don't implement virtualization yet, so these are zero */ |
| 1892 | cs->irs_idr3 = 0; |
| 1893 | cs->irs_idr4 = 0; |
| 1894 | |
| 1895 | /* These three have just one field each */ |
| 1896 | cs->irs_idr5 = FIELD_DP32(0, IRS_IDR5, SPI_RANGE, cs->spi_range); |
| 1897 | cs->irs_idr6 = FIELD_DP32(0, IRS_IDR6, SPI_IRS_RANGE, cs->spi_irs_range); |
| 1898 | cs->irs_idr7 = FIELD_DP32(0, IRS_IDR7, SPI_BASE, cs->spi_base); |
| 1899 | |
| 1900 | v = 0; |
| 1901 | v = FIELD_DP32(v, IRS_IIDR, IMPLEMENTER, QEMU_GICV5_IMPLEMENTER); |
| 1902 | v = FIELD_DP32(v, IRS_IIDR, REVISION, QEMU_GICV5_REVISION); |
| 1903 | v = FIELD_DP32(v, IRS_IIDR, VARIANT, QEMU_GICV5_VARIANT); |
| 1904 | v = FIELD_DP32(v, IRS_IIDR, PRODUCTID, QEMU_GICV5_PRODUCTID); |
| 1905 | cs->irs_iidr = v; |
| 1906 | |
| 1907 | /* This is a GICv5.0 IRS, so all fields are zero */ |
| 1908 | cs->irs_aidr = 0; |
| 1909 | } |
| 1910 | |
| 1911 | static void gicv5_realize(DeviceState *dev, Error **errp) |
| 1912 | { |
| 1913 | GICv5 *s = ARM_GICV5(dev); |
| 1914 | GICv5Common *cs = ARM_GICV5_COMMON(dev); |
| 1915 | GICv5Class *gc = ARM_GICV5_GET_CLASS(dev); |
| 1916 | Error *migration_blocker = NULL; |
| 1917 | |
| 1918 | ERRP_GUARD(); |
| 1919 | |
| 1920 | gc->parent_realize(dev, errp); |
| 1921 | if (*errp) { |
| 1922 | return; |
| 1923 | } |
| 1924 | |
| 1925 | error_setg(&migration_blocker, |
| 1926 | "Live migration disabled: not yet supported by GICv5"); |
| 1927 | if (migrate_add_blocker(&migration_blocker, errp)) { |
| 1928 | return; |
| 1929 | } |
| 1930 | |
| 1931 | /* |
| 1932 | * When we implement support for more than one interrupt domain, |
| 1933 | * we will provide some QOM properties so the board can configure |
| 1934 | * which domains are implemented. For now, we only implement the |
| 1935 | * NS domain. |
| 1936 | */ |
| 1937 | cs->implemented_domains = (1 << GICV5_ID_NS); |
| 1938 | |
| 1939 | gicv5_set_idregs(cs); |
| 1940 | gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops); |
| 1941 | |
| 1942 | for (int i = 0; i < NUM_GICV5_DOMAINS; i++) { |
| 1943 | if (gicv5_domain_implemented(cs, i)) { |
| 1944 | s->hppi[i] = g_new0(GICv5PendingIrq, cs->num_cpus); |
| 1945 | } |
| 1946 | } |
| 1947 | } |
| 1948 | |
| 1949 | static void gicv5_init(Object *obj) |
| 1950 | { |
| 1951 | } |
| 1952 | |
| 1953 | static void gicv5_finalize(Object *obj) |
| 1954 | { |
| 1955 | } |
| 1956 | |
| 1957 | static void gicv5_class_init(ObjectClass *oc, const void *data) |
| 1958 | { |
| 1959 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 1960 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 1961 | GICv5Class *gc = ARM_GICV5_CLASS(oc); |
| 1962 | |
| 1963 | device_class_set_parent_realize(dc, gicv5_realize, &gc->parent_realize); |
| 1964 | resettable_class_set_parent_phases(rc, NULL, gicv5_reset_hold, NULL, |
| 1965 | &gc->parent_phases); |
| 1966 | } |