| 1 | /* |
| 2 | * Samsung exynos4210 Interrupt Combiner |
| 3 | * |
| 4 | * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Evgeny Voevodin <e.voevodin@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| 17 | * See the GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Exynos4210 Combiner represents an OR gate for SOC's IRQ lines. It combines |
| 25 | * IRQ sources into groups and provides signal output to GIC from each group. It |
| 26 | * is driven by common mask and enable/disable logic. Take a note that not all |
| 27 | * IRQs are passed to GIC through Combiner. |
| 28 | */ |
| 29 | |
| 30 | #include "qemu/osdep.h" |
| 31 | #include "qemu/log.h" |
| 32 | #include "hw/core/sysbus.h" |
| 33 | #include "migration/vmstate.h" |
| 34 | #include "qemu/module.h" |
| 35 | #include "hw/intc/exynos4210_combiner.h" |
| 36 | #include "hw/arm/exynos4210.h" |
| 37 | #include "hw/core/irq.h" |
| 38 | #include "hw/core/qdev-properties.h" |
| 39 | #include "qom/object.h" |
| 40 | |
| 41 | //#define DEBUG_COMBINER |
| 42 | |
| 43 | #ifdef DEBUG_COMBINER |
| 44 | #define DPRINTF(fmt, ...) \ |
| 45 | do { fprintf(stdout, "COMBINER: [%s:%d] " fmt, __func__ , __LINE__, \ |
| 46 | ## __VA_ARGS__); } while (0) |
| 47 | #else |
| 48 | #define DPRINTF(fmt, ...) do {} while (0) |
| 49 | #endif |
| 50 | |
| 51 | #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */ |
| 52 | |
| 53 | static const VMStateDescription vmstate_exynos4210_combiner_group_state = { |
| 54 | .name = "exynos4210.combiner.groupstate", |
| 55 | .version_id = 1, |
| 56 | .minimum_version_id = 1, |
| 57 | .fields = (const VMStateField[]) { |
| 58 | VMSTATE_UINT8(src_mask, CombinerGroupState), |
| 59 | VMSTATE_UINT8(src_pending, CombinerGroupState), |
| 60 | VMSTATE_END_OF_LIST() |
| 61 | } |
| 62 | }; |
| 63 | |
| 64 | static const VMStateDescription vmstate_exynos4210_combiner = { |
| 65 | .name = "exynos4210.combiner", |
| 66 | .version_id = 1, |
| 67 | .minimum_version_id = 1, |
| 68 | .fields = (const VMStateField[]) { |
| 69 | VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0, |
| 70 | vmstate_exynos4210_combiner_group_state, CombinerGroupState), |
| 71 | VMSTATE_UINT32_ARRAY(reg_set, Exynos4210CombinerState, |
| 72 | IIC_REGSET_SIZE), |
| 73 | VMSTATE_UINT32_ARRAY(icipsr, Exynos4210CombinerState, 2), |
| 74 | VMSTATE_UINT32(external, Exynos4210CombinerState), |
| 75 | VMSTATE_END_OF_LIST() |
| 76 | } |
| 77 | }; |
| 78 | |
| 79 | static uint64_t |
| 80 | exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) |
| 81 | { |
| 82 | struct Exynos4210CombinerState *s = |
| 83 | (struct Exynos4210CombinerState *)opaque; |
| 84 | uint32_t req_quad_base_n; /* Base of registers quad. Multiply it by 4 and |
| 85 | get a start of corresponding group quad */ |
| 86 | uint32_t grp_quad_base_n; /* Base of group quad */ |
| 87 | uint32_t reg_n; /* Register number inside the quad */ |
| 88 | uint32_t val; |
| 89 | |
| 90 | req_quad_base_n = offset >> 4; |
| 91 | grp_quad_base_n = req_quad_base_n << 2; |
| 92 | reg_n = (offset - (req_quad_base_n << 4)) >> 2; |
| 93 | |
| 94 | if (req_quad_base_n >= IIC_NGRP) { |
| 95 | /* Read of ICIPSR register */ |
| 96 | return s->icipsr[reg_n]; |
| 97 | } |
| 98 | |
| 99 | val = 0; |
| 100 | |
| 101 | switch (reg_n) { |
| 102 | /* IISTR */ |
| 103 | case 2: |
| 104 | val |= s->group[grp_quad_base_n].src_pending; |
| 105 | val |= s->group[grp_quad_base_n + 1].src_pending << 8; |
| 106 | val |= s->group[grp_quad_base_n + 2].src_pending << 16; |
| 107 | val |= s->group[grp_quad_base_n + 3].src_pending << 24; |
| 108 | break; |
| 109 | /* IIMSR */ |
| 110 | case 3: |
| 111 | val |= s->group[grp_quad_base_n].src_mask & |
| 112 | s->group[grp_quad_base_n].src_pending; |
| 113 | val |= (s->group[grp_quad_base_n + 1].src_mask & |
| 114 | s->group[grp_quad_base_n + 1].src_pending) << 8; |
| 115 | val |= (s->group[grp_quad_base_n + 2].src_mask & |
| 116 | s->group[grp_quad_base_n + 2].src_pending) << 16; |
| 117 | val |= (s->group[grp_quad_base_n + 3].src_mask & |
| 118 | s->group[grp_quad_base_n + 3].src_pending) << 24; |
| 119 | break; |
| 120 | default: |
| 121 | if (offset >> 2 >= IIC_REGSET_SIZE) { |
| 122 | qemu_log_mask(LOG_GUEST_ERROR, |
| 123 | "exynos4210.combiner: overflow of reg_set by 0x" |
| 124 | HWADDR_FMT_plx "offset\n", offset); |
| 125 | return 0; |
| 126 | } |
| 127 | val = s->reg_set[offset >> 2]; |
| 128 | } |
| 129 | return val; |
| 130 | } |
| 131 | |
| 132 | static void exynos4210_combiner_update(void *opaque, uint8_t group_n) |
| 133 | { |
| 134 | struct Exynos4210CombinerState *s = |
| 135 | (struct Exynos4210CombinerState *)opaque; |
| 136 | |
| 137 | /* Send interrupt if needed */ |
| 138 | if (s->group[group_n].src_mask & s->group[group_n].src_pending) { |
| 139 | #ifdef DEBUG_COMBINER |
| 140 | if (group_n != 26) { |
| 141 | /* skip uart */ |
| 142 | DPRINTF("%s raise IRQ[%d]\n", s->external ? "EXT" : "INT", group_n); |
| 143 | } |
| 144 | #endif |
| 145 | |
| 146 | /* Set Combiner interrupt pending status after masking */ |
| 147 | if (group_n >= 32) { |
| 148 | s->icipsr[1] |= 1 << (group_n - 32); |
| 149 | } else { |
| 150 | s->icipsr[0] |= 1 << group_n; |
| 151 | } |
| 152 | |
| 153 | qemu_irq_raise(s->output_irq[group_n]); |
| 154 | } else { |
| 155 | #ifdef DEBUG_COMBINER |
| 156 | if (group_n != 26) { |
| 157 | /* skip uart */ |
| 158 | DPRINTF("%s lower IRQ[%d]\n", s->external ? "EXT" : "INT", group_n); |
| 159 | } |
| 160 | #endif |
| 161 | |
| 162 | /* Set Combiner interrupt pending status after masking */ |
| 163 | if (group_n >= 32) { |
| 164 | s->icipsr[1] &= ~(1 << (group_n - 32)); |
| 165 | } else { |
| 166 | s->icipsr[0] &= ~(1 << group_n); |
| 167 | } |
| 168 | |
| 169 | qemu_irq_lower(s->output_irq[group_n]); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | static void exynos4210_combiner_write(void *opaque, hwaddr offset, |
| 174 | uint64_t val, unsigned size) |
| 175 | { |
| 176 | struct Exynos4210CombinerState *s = |
| 177 | (struct Exynos4210CombinerState *)opaque; |
| 178 | uint32_t req_quad_base_n; /* Base of registers quad. Multiply it by 4 and |
| 179 | get a start of corresponding group quad */ |
| 180 | uint32_t grp_quad_base_n; /* Base of group quad */ |
| 181 | uint32_t reg_n; /* Register number inside the quad */ |
| 182 | |
| 183 | req_quad_base_n = offset >> 4; |
| 184 | grp_quad_base_n = req_quad_base_n << 2; |
| 185 | reg_n = (offset - (req_quad_base_n << 4)) >> 2; |
| 186 | |
| 187 | if (req_quad_base_n >= IIC_NGRP) { |
| 188 | qemu_log_mask(LOG_GUEST_ERROR, |
| 189 | "exynos4210.combiner: unallowed write access at offset 0x" |
| 190 | HWADDR_FMT_plx "\n", offset); |
| 191 | return; |
| 192 | } |
| 193 | |
| 194 | if (reg_n > 1) { |
| 195 | qemu_log_mask(LOG_GUEST_ERROR, |
| 196 | "exynos4210.combiner: unallowed write access at offset 0x" |
| 197 | HWADDR_FMT_plx "\n", offset); |
| 198 | return; |
| 199 | } |
| 200 | |
| 201 | if (offset >> 2 >= IIC_REGSET_SIZE) { |
| 202 | qemu_log_mask(LOG_GUEST_ERROR, |
| 203 | "exynos4210.combiner: overflow of reg_set by 0x" |
| 204 | HWADDR_FMT_plx "offset\n", offset); |
| 205 | return; |
| 206 | } |
| 207 | s->reg_set[offset >> 2] = val; |
| 208 | |
| 209 | switch (reg_n) { |
| 210 | /* IIESR */ |
| 211 | case 0: |
| 212 | /* FIXME: what if irq is pending, allowed by mask, and we allow it |
| 213 | * again. Interrupt will rise again! */ |
| 214 | |
| 215 | DPRINTF("%s enable IRQ for groups %d, %d, %d, %d\n", |
| 216 | s->external ? "EXT" : "INT", |
| 217 | grp_quad_base_n, |
| 218 | grp_quad_base_n + 1, |
| 219 | grp_quad_base_n + 2, |
| 220 | grp_quad_base_n + 3); |
| 221 | |
| 222 | /* Enable interrupt sources */ |
| 223 | s->group[grp_quad_base_n].src_mask |= val & 0xFF; |
| 224 | s->group[grp_quad_base_n + 1].src_mask |= (val & 0xFF00) >> 8; |
| 225 | s->group[grp_quad_base_n + 2].src_mask |= (val & 0xFF0000) >> 16; |
| 226 | s->group[grp_quad_base_n + 3].src_mask |= (val & 0xFF000000) >> 24; |
| 227 | |
| 228 | exynos4210_combiner_update(s, grp_quad_base_n); |
| 229 | exynos4210_combiner_update(s, grp_quad_base_n + 1); |
| 230 | exynos4210_combiner_update(s, grp_quad_base_n + 2); |
| 231 | exynos4210_combiner_update(s, grp_quad_base_n + 3); |
| 232 | break; |
| 233 | /* IIECR */ |
| 234 | case 1: |
| 235 | DPRINTF("%s disable IRQ for groups %d, %d, %d, %d\n", |
| 236 | s->external ? "EXT" : "INT", |
| 237 | grp_quad_base_n, |
| 238 | grp_quad_base_n + 1, |
| 239 | grp_quad_base_n + 2, |
| 240 | grp_quad_base_n + 3); |
| 241 | |
| 242 | /* Disable interrupt sources */ |
| 243 | s->group[grp_quad_base_n].src_mask &= ~(val & 0xFF); |
| 244 | s->group[grp_quad_base_n + 1].src_mask &= ~((val & 0xFF00) >> 8); |
| 245 | s->group[grp_quad_base_n + 2].src_mask &= ~((val & 0xFF0000) >> 16); |
| 246 | s->group[grp_quad_base_n + 3].src_mask &= ~((val & 0xFF000000) >> 24); |
| 247 | |
| 248 | exynos4210_combiner_update(s, grp_quad_base_n); |
| 249 | exynos4210_combiner_update(s, grp_quad_base_n + 1); |
| 250 | exynos4210_combiner_update(s, grp_quad_base_n + 2); |
| 251 | exynos4210_combiner_update(s, grp_quad_base_n + 3); |
| 252 | break; |
| 253 | default: |
| 254 | qemu_log_mask(LOG_GUEST_ERROR, |
| 255 | "exynos4210.combiner: unallowed write access at offset 0x" |
| 256 | HWADDR_FMT_plx "\n", offset); |
| 257 | break; |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | /* Get combiner group and bit from irq number */ |
| 262 | static uint8_t get_combiner_group_and_bit(int irq, uint8_t *bit) |
| 263 | { |
| 264 | *bit = irq - ((irq >> 3) << 3); |
| 265 | return irq >> 3; |
| 266 | } |
| 267 | |
| 268 | /* Process a change in an external IRQ input. */ |
| 269 | static void exynos4210_combiner_handler(void *opaque, int irq, int level) |
| 270 | { |
| 271 | struct Exynos4210CombinerState *s = |
| 272 | (struct Exynos4210CombinerState *)opaque; |
| 273 | uint8_t bit_n, group_n; |
| 274 | |
| 275 | group_n = get_combiner_group_and_bit(irq, &bit_n); |
| 276 | |
| 277 | if (s->external && group_n >= EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ) { |
| 278 | DPRINTF("%s unallowed IRQ group 0x%x\n", s->external ? "EXT" : "INT" |
| 279 | , group_n); |
| 280 | return; |
| 281 | } |
| 282 | |
| 283 | if (level) { |
| 284 | s->group[group_n].src_pending |= 1 << bit_n; |
| 285 | } else { |
| 286 | s->group[group_n].src_pending &= ~(1 << bit_n); |
| 287 | } |
| 288 | |
| 289 | exynos4210_combiner_update(s, group_n); |
| 290 | } |
| 291 | |
| 292 | static void exynos4210_combiner_reset(DeviceState *d) |
| 293 | { |
| 294 | struct Exynos4210CombinerState *s = (struct Exynos4210CombinerState *)d; |
| 295 | |
| 296 | memset(&s->group, 0, sizeof(s->group)); |
| 297 | memset(&s->reg_set, 0, sizeof(s->reg_set)); |
| 298 | |
| 299 | s->reg_set[0xC0 >> 2] = 0x01010101; |
| 300 | s->reg_set[0xC4 >> 2] = 0x01010101; |
| 301 | s->reg_set[0xD0 >> 2] = 0x01010101; |
| 302 | s->reg_set[0xD4 >> 2] = 0x01010101; |
| 303 | } |
| 304 | |
| 305 | static const MemoryRegionOps exynos4210_combiner_ops = { |
| 306 | .read = exynos4210_combiner_read, |
| 307 | .write = exynos4210_combiner_write, |
| 308 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 309 | }; |
| 310 | |
| 311 | /* |
| 312 | * Internal Combiner initialization. |
| 313 | */ |
| 314 | static void exynos4210_combiner_init(Object *obj) |
| 315 | { |
| 316 | DeviceState *dev = DEVICE(obj); |
| 317 | Exynos4210CombinerState *s = EXYNOS4210_COMBINER(obj); |
| 318 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 319 | unsigned int i; |
| 320 | |
| 321 | /* Allocate general purpose input signals and connect a handler to each of |
| 322 | * them */ |
| 323 | qdev_init_gpio_in(dev, exynos4210_combiner_handler, IIC_NIRQ); |
| 324 | |
| 325 | /* Connect SysBusDev irqs to device specific irqs */ |
| 326 | for (i = 0; i < IIC_NGRP; i++) { |
| 327 | sysbus_init_irq(sbd, &s->output_irq[i]); |
| 328 | } |
| 329 | |
| 330 | memory_region_init_io(&s->iomem, obj, &exynos4210_combiner_ops, s, |
| 331 | "exynos4210-combiner", IIC_REGION_SIZE); |
| 332 | sysbus_init_mmio(sbd, &s->iomem); |
| 333 | } |
| 334 | |
| 335 | static const Property exynos4210_combiner_properties[] = { |
| 336 | DEFINE_PROP_UINT32("external", Exynos4210CombinerState, external, 0), |
| 337 | }; |
| 338 | |
| 339 | static void exynos4210_combiner_class_init(ObjectClass *klass, const void *data) |
| 340 | { |
| 341 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 342 | |
| 343 | device_class_set_legacy_reset(dc, exynos4210_combiner_reset); |
| 344 | device_class_set_props(dc, exynos4210_combiner_properties); |
| 345 | dc->vmsd = &vmstate_exynos4210_combiner; |
| 346 | } |
| 347 | |
| 348 | static const TypeInfo exynos4210_combiner_info = { |
| 349 | .name = TYPE_EXYNOS4210_COMBINER, |
| 350 | .parent = TYPE_SYS_BUS_DEVICE, |
| 351 | .instance_size = sizeof(Exynos4210CombinerState), |
| 352 | .instance_init = exynos4210_combiner_init, |
| 353 | .class_init = exynos4210_combiner_class_init, |
| 354 | }; |
| 355 | |
| 356 | static void exynos4210_combiner_register_types(void) |
| 357 | { |
| 358 | type_register_static(&exynos4210_combiner_info); |
| 359 | } |
| 360 | |
| 361 | type_init(exynos4210_combiner_register_types) |