| 1 | /* |
| 2 | * ioapic.c IOAPIC emulation logic |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Fabrice Bellard |
| 5 | * |
| 6 | * Split the ioapic logic from apic.c |
| 7 | * Xiantao Zhang <xiantao.zhang@intel.com> |
| 8 | * |
| 9 | * This library is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU Lesser General Public |
| 11 | * License as published by the Free Software Foundation; either |
| 12 | * version 2.1 of the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This library is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * Lesser General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU Lesser General Public |
| 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #include "qemu/osdep.h" |
| 24 | #include "qapi/error.h" |
| 25 | #include "monitor/monitor.h" |
| 26 | #include "hw/i386/apic.h" |
| 27 | #include "hw/i386/x86.h" |
| 28 | #include "hw/intc/i8259.h" |
| 29 | #include "hw/intc/ioapic.h" |
| 30 | #include "hw/intc/ioapic_internal.h" |
| 31 | #include "hw/pci/msi.h" |
| 32 | #include "hw/core/qdev-properties.h" |
| 33 | #include "system/accel-irq.h" |
| 34 | #include "system/kvm.h" |
| 35 | #include "system/system.h" |
| 36 | #include "hw/i386/apic-msidef.h" |
| 37 | #include "hw/i386/x86-iommu.h" |
| 38 | #include "trace.h" |
| 39 | |
| 40 | |
| 41 | #if defined(CONFIG_KVM) || defined(CONFIG_MSHV) |
| 42 | #define ACCEL_GSI_IRQFD_POSSIBLE |
| 43 | #endif |
| 44 | |
| 45 | #define APIC_DELIVERY_MODE_SHIFT 8 |
| 46 | #define APIC_POLARITY_SHIFT 14 |
| 47 | #define APIC_TRIG_MODE_SHIFT 15 |
| 48 | |
| 49 | static IOAPICCommonState *ioapics[MAX_IOAPICS]; |
| 50 | |
| 51 | /* global variable from ioapic_common.c */ |
| 52 | extern int ioapic_no; |
| 53 | |
| 54 | struct ioapic_entry_info { |
| 55 | /* fields parsed from IOAPIC entries */ |
| 56 | uint8_t masked; |
| 57 | uint8_t trig_mode; |
| 58 | uint16_t dest_idx; |
| 59 | uint8_t dest_mode; |
| 60 | uint8_t delivery_mode; |
| 61 | uint8_t vector; |
| 62 | |
| 63 | /* MSI message generated from above parsed fields */ |
| 64 | uint32_t addr; |
| 65 | uint32_t data; |
| 66 | }; |
| 67 | |
| 68 | static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) |
| 69 | { |
| 70 | memset(info, 0, sizeof(*info)); |
| 71 | info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; |
| 72 | info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; |
| 73 | /* |
| 74 | * By default, this would be dest_id[8] + reserved[8]. When IR |
| 75 | * is enabled, this would be interrupt_index[15] + |
| 76 | * interrupt_format[1]. This field never means anything, but |
| 77 | * only used to generate corresponding MSI. |
| 78 | */ |
| 79 | info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; |
| 80 | info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; |
| 81 | info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ |
| 82 | & IOAPIC_DM_MASK; |
| 83 | if (info->delivery_mode == IOAPIC_DM_EXTINT) { |
| 84 | info->vector = pic_read_irq(isa_pic); |
| 85 | } else { |
| 86 | info->vector = entry & IOAPIC_VECTOR_MASK; |
| 87 | } |
| 88 | |
| 89 | info->addr = APIC_DEFAULT_ADDRESS | \ |
| 90 | (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ |
| 91 | (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); |
| 92 | info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ |
| 93 | (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ |
| 94 | (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); |
| 95 | } |
| 96 | |
| 97 | static void ioapic_service(IOAPICCommonState *s) |
| 98 | { |
| 99 | AddressSpace *ioapic_as = X86_MACHINE(qdev_get_machine())->ioapic_as; |
| 100 | struct ioapic_entry_info info; |
| 101 | uint8_t i; |
| 102 | uint32_t mask; |
| 103 | uint64_t entry; |
| 104 | |
| 105 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
| 106 | mask = 1 << i; |
| 107 | if (s->irr & mask) { |
| 108 | int coalesce = 0; |
| 109 | |
| 110 | entry = s->ioredtbl[i]; |
| 111 | ioapic_entry_parse(entry, &info); |
| 112 | if (!info.masked) { |
| 113 | if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { |
| 114 | s->irr &= ~mask; |
| 115 | } else { |
| 116 | coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; |
| 117 | trace_ioapic_set_remote_irr(i); |
| 118 | s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; |
| 119 | } |
| 120 | |
| 121 | if (coalesce) { |
| 122 | /* We are level triggered interrupts, and the |
| 123 | * guest should be still working on previous one, |
| 124 | * so skip it. */ |
| 125 | continue; |
| 126 | } |
| 127 | |
| 128 | #ifdef CONFIG_KVM |
| 129 | if (kvm_irqchip_is_split()) { |
| 130 | if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { |
| 131 | kvm_set_irq(kvm_state, i, 1); |
| 132 | kvm_set_irq(kvm_state, i, 0); |
| 133 | } else { |
| 134 | kvm_set_irq(kvm_state, i, 1); |
| 135 | } |
| 136 | continue; |
| 137 | } |
| 138 | #endif |
| 139 | |
| 140 | /* No matter whether IR is enabled, we translate |
| 141 | * the IOAPIC message into a MSI one, and its |
| 142 | * address space will decide whether we need a |
| 143 | * translation. */ |
| 144 | address_space_stl_le(ioapic_as, info.addr, info.data, |
| 145 | MEMTXATTRS_UNSPECIFIED, NULL); |
| 146 | } |
| 147 | } |
| 148 | } |
| 149 | } |
| 150 | |
| 151 | #define SUCCESSIVE_IRQ_MAX_COUNT 10000 |
| 152 | |
| 153 | static void delayed_ioapic_service_cb(void *opaque) |
| 154 | { |
| 155 | IOAPICCommonState *s = opaque; |
| 156 | |
| 157 | ioapic_service(s); |
| 158 | } |
| 159 | |
| 160 | static void ioapic_set_irq(void *opaque, int vector, int level) |
| 161 | { |
| 162 | IOAPICCommonState *s = opaque; |
| 163 | |
| 164 | /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps |
| 165 | * to GSI 2. GSI maps to ioapic 1-1. This is not |
| 166 | * the cleanest way of doing it but it should work. */ |
| 167 | |
| 168 | trace_ioapic_set_irq(vector, level); |
| 169 | ioapic_stat_update_irq(s, vector, level); |
| 170 | if (vector == 0) { |
| 171 | vector = 2; |
| 172 | } |
| 173 | if (vector < IOAPIC_NUM_PINS) { |
| 174 | uint32_t mask = 1 << vector; |
| 175 | uint64_t entry = s->ioredtbl[vector]; |
| 176 | |
| 177 | if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == |
| 178 | IOAPIC_TRIGGER_LEVEL) { |
| 179 | /* level triggered */ |
| 180 | if (level) { |
| 181 | s->irr |= mask; |
| 182 | if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { |
| 183 | ioapic_service(s); |
| 184 | } |
| 185 | } else { |
| 186 | s->irr &= ~mask; |
| 187 | } |
| 188 | } else { |
| 189 | /* According to the 82093AA manual, we must ignore edge requests |
| 190 | * if the input pin is masked. */ |
| 191 | if (level && !(entry & IOAPIC_LVT_MASKED)) { |
| 192 | s->irr |= mask; |
| 193 | ioapic_service(s); |
| 194 | } |
| 195 | } |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | static void ioapic_update_kvm_routes(IOAPICCommonState *s) |
| 200 | { |
| 201 | #ifdef ACCEL_GSI_IRQFD_POSSIBLE |
| 202 | int i; |
| 203 | |
| 204 | if (accel_irqchip_is_split()) { |
| 205 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
| 206 | MSIMessage msg; |
| 207 | struct ioapic_entry_info info; |
| 208 | ioapic_entry_parse(s->ioredtbl[i], &info); |
| 209 | if (!info.masked) { |
| 210 | msg.address = info.addr; |
| 211 | msg.data = info.data; |
| 212 | accel_irqchip_update_msi_route(i, msg, NULL); |
| 213 | } |
| 214 | } |
| 215 | accel_irqchip_commit_routes(); |
| 216 | } |
| 217 | #endif |
| 218 | } |
| 219 | |
| 220 | #ifdef ACCEL_GSI_IRQFD_POSSIBLE |
| 221 | static void ioapic_iec_notifier(void *private, bool global, |
| 222 | uint32_t index, uint32_t mask) |
| 223 | { |
| 224 | IOAPICCommonState *s = (IOAPICCommonState *)private; |
| 225 | /* For simplicity, we just update all the routes */ |
| 226 | ioapic_update_kvm_routes(s); |
| 227 | } |
| 228 | #endif |
| 229 | |
| 230 | void ioapic_eoi_broadcast(int vector) |
| 231 | { |
| 232 | IOAPICCommonState *s; |
| 233 | uint64_t entry; |
| 234 | int i, n; |
| 235 | |
| 236 | trace_ioapic_eoi_broadcast(vector); |
| 237 | |
| 238 | for (i = 0; i < MAX_IOAPICS; i++) { |
| 239 | s = ioapics[i]; |
| 240 | if (!s) { |
| 241 | continue; |
| 242 | } |
| 243 | for (n = 0; n < IOAPIC_NUM_PINS; n++) { |
| 244 | entry = s->ioredtbl[n]; |
| 245 | |
| 246 | if ((entry & IOAPIC_VECTOR_MASK) != vector || |
| 247 | ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) != IOAPIC_TRIGGER_LEVEL) { |
| 248 | continue; |
| 249 | } |
| 250 | |
| 251 | #ifdef CONFIG_KVM |
| 252 | /* |
| 253 | * When IOAPIC is in the userspace while APIC is still in |
| 254 | * the kernel (i.e., split irqchip), we have a trick to |
| 255 | * kick the resamplefd logic for registered irqfds from |
| 256 | * userspace to deactivate the IRQ. When that happens, it |
| 257 | * means the irq bypassed userspace IOAPIC (so the irr and |
| 258 | * remote-irr of the table entry should be bypassed too |
| 259 | * even if interrupt come). Still kick the resamplefds if |
| 260 | * they're bound to the IRQ, to make sure to EOI the |
| 261 | * interrupt for the hardware correctly. |
| 262 | * |
| 263 | * Note: We still need to go through the irr & remote-irr |
| 264 | * operations below because we don't know whether there're |
| 265 | * emulated devices that are using/sharing the same IRQ. |
| 266 | */ |
| 267 | kvm_resample_fd_notify(n); |
| 268 | #endif |
| 269 | |
| 270 | if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { |
| 271 | continue; |
| 272 | } |
| 273 | |
| 274 | trace_ioapic_clear_remote_irr(n, vector); |
| 275 | s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; |
| 276 | |
| 277 | if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { |
| 278 | ++s->irq_eoi[n]; |
| 279 | if (s->irq_eoi[n] >= SUCCESSIVE_IRQ_MAX_COUNT) { |
| 280 | /* |
| 281 | * Real hardware does not deliver the interrupt immediately |
| 282 | * during eoi broadcast, and this lets a buggy guest make |
| 283 | * slow progress even if it does not correctly handle a |
| 284 | * level-triggered interrupt. Emulate this behavior if we |
| 285 | * detect an interrupt storm. |
| 286 | */ |
| 287 | s->irq_eoi[n] = 0; |
| 288 | timer_mod_anticipate(s->delayed_ioapic_service_timer, |
| 289 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
| 290 | NANOSECONDS_PER_SECOND / 100); |
| 291 | trace_ioapic_eoi_delayed_reassert(n); |
| 292 | } else { |
| 293 | ioapic_service(s); |
| 294 | } |
| 295 | } else { |
| 296 | s->irq_eoi[n] = 0; |
| 297 | } |
| 298 | } |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | static uint64_t |
| 303 | ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) |
| 304 | { |
| 305 | IOAPICCommonState *s = opaque; |
| 306 | int index; |
| 307 | uint32_t val = 0; |
| 308 | |
| 309 | addr &= 0xff; |
| 310 | |
| 311 | switch (addr) { |
| 312 | case IOAPIC_IOREGSEL: |
| 313 | val = s->ioregsel; |
| 314 | break; |
| 315 | case IOAPIC_IOWIN: |
| 316 | if (size != 4) { |
| 317 | break; |
| 318 | } |
| 319 | switch (s->ioregsel) { |
| 320 | case IOAPIC_REG_ID: |
| 321 | case IOAPIC_REG_ARB: |
| 322 | val = s->id << IOAPIC_ID_SHIFT; |
| 323 | break; |
| 324 | case IOAPIC_REG_VER: |
| 325 | val = s->version | |
| 326 | ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); |
| 327 | break; |
| 328 | default: |
| 329 | index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; |
| 330 | if (index >= 0 && index < IOAPIC_NUM_PINS) { |
| 331 | if (s->ioregsel & 1) { |
| 332 | val = s->ioredtbl[index] >> 32; |
| 333 | } else { |
| 334 | val = s->ioredtbl[index] & 0xffffffff; |
| 335 | } |
| 336 | } |
| 337 | } |
| 338 | break; |
| 339 | } |
| 340 | |
| 341 | trace_ioapic_mem_read(addr, s->ioregsel, size, val); |
| 342 | |
| 343 | return val; |
| 344 | } |
| 345 | |
| 346 | /* |
| 347 | * This is to satisfy the hack in Linux kernel. One hack of it is to |
| 348 | * simulate clearing the Remote IRR bit of IOAPIC entry using the |
| 349 | * following: |
| 350 | * |
| 351 | * "For IO-APIC's with EOI register, we use that to do an explicit EOI. |
| 352 | * Otherwise, we simulate the EOI message manually by changing the trigger |
| 353 | * mode to edge and then back to level, with RTE being masked during |
| 354 | * this." |
| 355 | * |
| 356 | * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) |
| 357 | * |
| 358 | * This is based on the assumption that, Remote IRR bit will be |
| 359 | * cleared by IOAPIC hardware when configured as edge-triggered |
| 360 | * interrupts. |
| 361 | * |
| 362 | * Without this, level-triggered interrupts in IR mode might fail to |
| 363 | * work correctly. |
| 364 | */ |
| 365 | static inline void |
| 366 | ioapic_fix_edge_remote_irr(uint64_t *entry) |
| 367 | { |
| 368 | if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { |
| 369 | /* Edge-triggered interrupts, make sure remote IRR is zero */ |
| 370 | *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | static void |
| 375 | ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, |
| 376 | unsigned int size) |
| 377 | { |
| 378 | IOAPICCommonState *s = opaque; |
| 379 | int index; |
| 380 | |
| 381 | addr &= 0xff; |
| 382 | trace_ioapic_mem_write(addr, s->ioregsel, size, val); |
| 383 | |
| 384 | switch (addr) { |
| 385 | case IOAPIC_IOREGSEL: |
| 386 | s->ioregsel = val; |
| 387 | break; |
| 388 | case IOAPIC_IOWIN: |
| 389 | if (size != 4) { |
| 390 | break; |
| 391 | } |
| 392 | switch (s->ioregsel) { |
| 393 | case IOAPIC_REG_ID: |
| 394 | s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; |
| 395 | break; |
| 396 | case IOAPIC_REG_VER: |
| 397 | case IOAPIC_REG_ARB: |
| 398 | break; |
| 399 | default: |
| 400 | index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; |
| 401 | if (index >= 0 && index < IOAPIC_NUM_PINS) { |
| 402 | uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; |
| 403 | if (s->ioregsel & 1) { |
| 404 | s->ioredtbl[index] &= 0xffffffff; |
| 405 | s->ioredtbl[index] |= (uint64_t)val << 32; |
| 406 | } else { |
| 407 | s->ioredtbl[index] &= ~0xffffffffULL; |
| 408 | s->ioredtbl[index] |= val; |
| 409 | } |
| 410 | /* restore RO bits */ |
| 411 | s->ioredtbl[index] &= IOAPIC_RW_BITS; |
| 412 | s->ioredtbl[index] |= ro_bits; |
| 413 | s->irq_eoi[index] = 0; |
| 414 | ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); |
| 415 | ioapic_update_kvm_routes(s); |
| 416 | ioapic_service(s); |
| 417 | } |
| 418 | } |
| 419 | break; |
| 420 | case IOAPIC_EOI: |
| 421 | /* Explicit EOI is only supported for IOAPIC version 0x20 */ |
| 422 | if (size != 4 || s->version != 0x20) { |
| 423 | break; |
| 424 | } |
| 425 | ioapic_eoi_broadcast(val); |
| 426 | break; |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | static const MemoryRegionOps ioapic_io_ops = { |
| 431 | .read = ioapic_mem_read, |
| 432 | .write = ioapic_mem_write, |
| 433 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 434 | }; |
| 435 | |
| 436 | static void ioapic_machine_done_notify(Notifier *notifier, void *data) |
| 437 | { |
| 438 | #ifdef ACCEL_GSI_IRQFD_POSSIBLE |
| 439 | IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, |
| 440 | machine_done); |
| 441 | |
| 442 | if (accel_irqchip_is_split()) { |
| 443 | X86IOMMUState *iommu = x86_iommu_get_default(); |
| 444 | if (iommu) { |
| 445 | /* Register this IOAPIC with IOMMU IEC notifier, so that |
| 446 | * when there are IR invalidates, we can be notified to |
| 447 | * update kernel IR cache. */ |
| 448 | x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s); |
| 449 | } |
| 450 | } |
| 451 | #endif |
| 452 | } |
| 453 | |
| 454 | #define IOAPIC_VER_DEF 0x20 |
| 455 | |
| 456 | static void ioapic_realize(DeviceState *dev, Error **errp) |
| 457 | { |
| 458 | IOAPICCommonState *s = IOAPIC_COMMON(dev); |
| 459 | |
| 460 | if (s->version != 0x11 && s->version != 0x20) { |
| 461 | error_setg(errp, "IOAPIC only supports version 0x11 or 0x20 " |
| 462 | "(default: 0x%x).", IOAPIC_VER_DEF); |
| 463 | return; |
| 464 | } |
| 465 | |
| 466 | memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, |
| 467 | "ioapic", 0x1000); |
| 468 | |
| 469 | s->delayed_ioapic_service_timer = |
| 470 | timer_new_ns(QEMU_CLOCK_VIRTUAL, delayed_ioapic_service_cb, s); |
| 471 | |
| 472 | qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); |
| 473 | |
| 474 | ioapics[ioapic_no] = s; |
| 475 | s->machine_done.notify = ioapic_machine_done_notify; |
| 476 | qemu_add_machine_init_done_notifier(&s->machine_done); |
| 477 | } |
| 478 | |
| 479 | static void ioapic_unrealize(DeviceState *dev) |
| 480 | { |
| 481 | IOAPICCommonState *s = IOAPIC_COMMON(dev); |
| 482 | |
| 483 | timer_free(s->delayed_ioapic_service_timer); |
| 484 | } |
| 485 | |
| 486 | static const Property ioapic_properties[] = { |
| 487 | DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF), |
| 488 | }; |
| 489 | |
| 490 | static void ioapic_class_init(ObjectClass *klass, const void *data) |
| 491 | { |
| 492 | IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); |
| 493 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 494 | |
| 495 | k->realize = ioapic_realize; |
| 496 | k->unrealize = ioapic_unrealize; |
| 497 | /* |
| 498 | * If APIC is in kernel, we need to update the kernel cache after |
| 499 | * migration, otherwise first 24 gsi routes will be invalid. |
| 500 | */ |
| 501 | k->post_load = ioapic_update_kvm_routes; |
| 502 | device_class_set_legacy_reset(dc, ioapic_reset_common); |
| 503 | device_class_set_props(dc, ioapic_properties); |
| 504 | } |
| 505 | |
| 506 | static const TypeInfo ioapic_info = { |
| 507 | .name = TYPE_IOAPIC, |
| 508 | .parent = TYPE_IOAPIC_COMMON, |
| 509 | .instance_size = sizeof(IOAPICCommonState), |
| 510 | .class_init = ioapic_class_init, |
| 511 | }; |
| 512 | |
| 513 | static void ioapic_register_types(void) |
| 514 | { |
| 515 | type_register_static(&ioapic_info); |
| 516 | } |
| 517 | |
| 518 | type_init(ioapic_register_types) |