| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * QEMU LoongArch direct interrupt controller. |
| 4 | * |
| 5 | * Copyright (C) 2025 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | |
| 8 | #include "qemu/osdep.h" |
| 9 | #include "hw/core/sysbus.h" |
| 10 | #include "hw/core/irq.h" |
| 11 | #include "hw/intc/loongarch_pch_msi.h" |
| 12 | #include "hw/intc/loongarch_pch_pic.h" |
| 13 | #include "hw/intc/loongarch_dintc.h" |
| 14 | #include "hw/pci/msi.h" |
| 15 | #include "hw/misc/unimp.h" |
| 16 | #include "migration/vmstate.h" |
| 17 | #include "trace.h" |
| 18 | #include "hw/core/qdev-properties.h" |
| 19 | #include "target/loongarch/cpu.h" |
| 20 | #include "qemu/error-report.h" |
| 21 | #include "system/hw_accel.h" |
| 22 | #include "qemu/log.h" |
| 23 | |
| 24 | /* msg addr field */ |
| 25 | FIELD(MSG_ADDR, IRQ_NUM, 4, 8) |
| 26 | FIELD(MSG_ADDR, CPU_NUM, 12, 8) |
| 27 | FIELD(MSG_ADDR, FIX, 28, 12) |
| 28 | |
| 29 | static uint64_t loongarch_dintc_mem_read(void *opaque, |
| 30 | hwaddr addr, unsigned size) |
| 31 | { |
| 32 | return 0; |
| 33 | } |
| 34 | |
| 35 | static void do_set_vcpu_dintc_irq(CPUState *cs, run_on_cpu_data data) |
| 36 | { |
| 37 | int irq = data.host_int; |
| 38 | CPULoongArchState *env; |
| 39 | CPUSysState *sys; |
| 40 | |
| 41 | env = &LOONGARCH_CPU(cs)->env; |
| 42 | sys = env_sys(env); |
| 43 | cpu_synchronize_state(cs); |
| 44 | set_bit(irq, (unsigned long *)&sys->CSR_MSGIS); |
| 45 | } |
| 46 | |
| 47 | static void loongarch_dintc_mem_write(void *opaque, hwaddr addr, |
| 48 | uint64_t val, unsigned size) |
| 49 | { |
| 50 | int irq_num, cpu_num = 0; |
| 51 | LoongArchDINTCState *s = LOONGARCH_DINTC(opaque); |
| 52 | uint64_t msg_addr = addr + VIRT_DINTC_BASE; |
| 53 | CPUState *cs; |
| 54 | |
| 55 | cpu_num = FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); |
| 56 | |
| 57 | /* Validate cpu_num against the configured number of CPUs */ |
| 58 | if (cpu_num >= s->num_cpu) { |
| 59 | qemu_log_mask(LOG_GUEST_ERROR, |
| 60 | "loongarch-dintc: invalid cpu number%d\n", cpu_num); |
| 61 | return; |
| 62 | } |
| 63 | cs = cpu_by_arch_id(cpu_num); |
| 64 | if (!cs) { |
| 65 | qemu_log_mask(LOG_GUEST_ERROR, |
| 66 | "loongarch-dintc: no CPU for arch_id %d\n", cpu_num); |
| 67 | return; |
| 68 | } |
| 69 | irq_num = FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM); |
| 70 | |
| 71 | if (kvm_irqchip_in_kernel()) { |
| 72 | MSIMessage msg; |
| 73 | |
| 74 | msg.address = msg_addr; |
| 75 | msg.data = val; |
| 76 | kvm_irqchip_send_msi(kvm_state, msg); |
| 77 | return; |
| 78 | } |
| 79 | |
| 80 | async_run_on_cpu(cs, do_set_vcpu_dintc_irq, |
| 81 | RUN_ON_CPU_HOST_INT(irq_num)); |
| 82 | qemu_set_irq(s->cpu[cpu_num].parent_irq, 1); |
| 83 | } |
| 84 | |
| 85 | static const MemoryRegionOps loongarch_dintc_ops = { |
| 86 | .read = loongarch_dintc_mem_read, |
| 87 | .write = loongarch_dintc_mem_write, |
| 88 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 89 | }; |
| 90 | |
| 91 | static void loongarch_dintc_realize(DeviceState *dev, Error **errp) |
| 92 | { |
| 93 | LoongArchDINTCState *s = LOONGARCH_DINTC(dev); |
| 94 | LoongArchDINTCClass *lac = LOONGARCH_DINTC_GET_CLASS(dev); |
| 95 | MachineState *machine = MACHINE(qdev_get_machine()); |
| 96 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 97 | const CPUArchIdList *id_list; |
| 98 | int i; |
| 99 | |
| 100 | Error *local_err = NULL; |
| 101 | lac->parent_realize(dev, &local_err); |
| 102 | if (local_err) { |
| 103 | error_propagate(errp, local_err); |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | assert(mc->possible_cpu_arch_ids); |
| 108 | id_list = mc->possible_cpu_arch_ids(machine); |
| 109 | s->num_cpu = id_list->len; |
| 110 | s->cpu = g_new(DINTCCore, s->num_cpu); |
| 111 | if (s->cpu == NULL) { |
| 112 | error_setg(errp, "Memory allocation for DINTCCore fail"); |
| 113 | return; |
| 114 | } |
| 115 | |
| 116 | for (i = 0; i < s->num_cpu; i++) { |
| 117 | s->cpu[i].arch_id = id_list->cpus[i].arch_id; |
| 118 | s->cpu[i].cpu = CPU(id_list->cpus[i].cpu); |
| 119 | qdev_init_gpio_out(dev, &s->cpu[i].parent_irq, 1); |
| 120 | } |
| 121 | |
| 122 | if (kvm_irqchip_in_kernel()) { |
| 123 | kvm_dintc_realize(dev, errp); |
| 124 | } |
| 125 | |
| 126 | return; |
| 127 | } |
| 128 | |
| 129 | static void loongarch_dintc_unrealize(DeviceState *dev) |
| 130 | { |
| 131 | LoongArchDINTCState *s = LOONGARCH_DINTC(dev); |
| 132 | g_free(s->cpu); |
| 133 | } |
| 134 | |
| 135 | static void loongarch_dintc_init(Object *obj) |
| 136 | { |
| 137 | LoongArchDINTCState *s = LOONGARCH_DINTC(obj); |
| 138 | SysBusDevice *shd = SYS_BUS_DEVICE(obj); |
| 139 | memory_region_init_io(&s->dintc_mmio, OBJECT(s), &loongarch_dintc_ops, |
| 140 | s, TYPE_LOONGARCH_DINTC, VIRT_DINTC_SIZE); |
| 141 | sysbus_init_mmio(shd, &s->dintc_mmio); |
| 142 | msi_nonbroken = true; |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | static DINTCCore *loongarch_dintc_get_cpu(LoongArchDINTCState *s, |
| 147 | DeviceState *dev) |
| 148 | { |
| 149 | CPUClass *k = CPU_GET_CLASS(dev); |
| 150 | uint64_t arch_id = k->get_arch_id(CPU(dev)); |
| 151 | int i; |
| 152 | |
| 153 | for (i = 0; i < s->num_cpu; i++) { |
| 154 | if (s->cpu[i].arch_id == arch_id) { |
| 155 | return &s->cpu[i]; |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | return NULL; |
| 160 | } |
| 161 | |
| 162 | static void loongarch_dintc_cpu_plug(HotplugHandler *hotplug_dev, |
| 163 | DeviceState *dev, Error **errp) |
| 164 | { |
| 165 | LoongArchDINTCState *s = LOONGARCH_DINTC(hotplug_dev); |
| 166 | Object *obj = OBJECT(dev); |
| 167 | DINTCCore *core; |
| 168 | int index; |
| 169 | |
| 170 | if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { |
| 171 | warn_report("LoongArch DINTC: Invalid %s device type", |
| 172 | object_get_typename(obj)); |
| 173 | return; |
| 174 | } |
| 175 | core = loongarch_dintc_get_cpu(s, dev); |
| 176 | if (!core) { |
| 177 | return; |
| 178 | } |
| 179 | |
| 180 | core->cpu = CPU(dev); |
| 181 | index = core - s->cpu; |
| 182 | |
| 183 | /* connect dintc msg irq to cpu irq */ |
| 184 | qdev_connect_gpio_out(DEVICE(s), index, qdev_get_gpio_in(dev, INT_DMSI)); |
| 185 | return; |
| 186 | } |
| 187 | |
| 188 | static void loongarch_dintc_cpu_unplug(HotplugHandler *hotplug_dev, |
| 189 | DeviceState *dev, Error **errp) |
| 190 | { |
| 191 | LoongArchDINTCState *s = LOONGARCH_DINTC(hotplug_dev); |
| 192 | Object *obj = OBJECT(dev); |
| 193 | DINTCCore *core; |
| 194 | |
| 195 | if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { |
| 196 | warn_report("LoongArch DINTC: Invalid %s device type", |
| 197 | object_get_typename(obj)); |
| 198 | return; |
| 199 | } |
| 200 | |
| 201 | core = loongarch_dintc_get_cpu(s, dev); |
| 202 | |
| 203 | if (!core) { |
| 204 | return; |
| 205 | } |
| 206 | |
| 207 | core->cpu = NULL; |
| 208 | } |
| 209 | |
| 210 | static void loongarch_dintc_class_init(ObjectClass *klass, const void *data) |
| 211 | { |
| 212 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 213 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
| 214 | LoongArchDINTCClass *lac = LOONGARCH_DINTC_CLASS(klass); |
| 215 | |
| 216 | dc->unrealize = loongarch_dintc_unrealize; |
| 217 | device_class_set_parent_realize(dc, loongarch_dintc_realize, |
| 218 | &lac->parent_realize); |
| 219 | hc->plug = loongarch_dintc_cpu_plug; |
| 220 | hc->unplug = loongarch_dintc_cpu_unplug; |
| 221 | } |
| 222 | |
| 223 | static const TypeInfo loongarch_dintc_info = { |
| 224 | .name = TYPE_LOONGARCH_DINTC, |
| 225 | .parent = TYPE_SYS_BUS_DEVICE, |
| 226 | .instance_size = sizeof(LoongArchDINTCState), |
| 227 | .instance_init = loongarch_dintc_init, |
| 228 | .class_size = sizeof(LoongArchDINTCClass), |
| 229 | .class_init = loongarch_dintc_class_init, |
| 230 | .interfaces = (const InterfaceInfo[]) { |
| 231 | { TYPE_HOTPLUG_HANDLER }, |
| 232 | { } |
| 233 | }, |
| 234 | }; |
| 235 | |
| 236 | static void loongarch_dintc_register_types(void) |
| 237 | { |
| 238 | type_register_static(&loongarch_dintc_info); |
| 239 | } |
| 240 | |
| 241 | type_init(loongarch_dintc_register_types) |