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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * QEMU Loongson 7A1000 msi interrupt controller.
4 *
5 * Copyright (C) 2021 Loongson Technology Corporation Limited
6 */
7
8 #include "qemu/osdep.h"
9 #include "hw/core/sysbus.h"
10 #include "hw/core/irq.h"
11 #include "hw/intc/loongarch_pch_msi.h"
12 #include "hw/intc/loongarch_pch_pic.h"
13 #include "hw/pci/msi.h"
14 #include "hw/misc/unimp.h"
15 #include "migration/vmstate.h"
16 #include "system/kvm.h"
17 #include "trace.h"
18
19 static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
20 {
21 return 0;
22 }
23
24 static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
25 uint64_t val, unsigned size)
26 {
27 LoongArchPCHMSI *s = (LoongArchPCHMSI *)opaque;
28 int irq_num;
29
30 if (kvm_irqchip_in_kernel()) {
31 MSIMessage msg;
32
33 msg.address = addr;
34 msg.data = val;
35 kvm_irqchip_send_msi(kvm_state, msg);
36 return;
37 }
38
39 /*
40 * vector number is irq number from upper extioi intc
41 * need subtract irq base to get msi vector offset
42 */
43 irq_num = (val & 0xff) - s->irq_base;
44 trace_loongarch_msi_set_irq(irq_num);
45 assert(irq_num < s->irq_num);
46 qemu_set_irq(s->pch_msi_irq[irq_num], 1);
47 }
48
49 static const MemoryRegionOps loongarch_pch_msi_ops = {
50 .read = loongarch_msi_mem_read,
51 .write = loongarch_msi_mem_write,
52 .endianness = DEVICE_LITTLE_ENDIAN,
53 };
54
55 static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
56 {
57 LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
58
59 if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
60 error_setg(errp, "Invalid 'msi_irq_num'");
61 return;
62 }
63
64 s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
65 qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
66 }
67
68 static void loongarch_pch_msi_unrealize(DeviceState *dev)
69 {
70 LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
71
72 g_free(s->pch_msi_irq);
73 }
74
75 static void loongarch_pch_msi_init(Object *obj)
76 {
77 LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
78 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
79
80 memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
81 s, TYPE_LOONGARCH_PCH_MSI, 0x8);
82 sysbus_init_mmio(sbd, &s->msi_mmio);
83 msi_nonbroken = true;
84
85 }
86
87 static const Property loongarch_msi_properties[] = {
88 DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
89 DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
90 };
91
92 static void loongarch_pch_msi_class_init(ObjectClass *klass, const void *data)
93 {
94 DeviceClass *dc = DEVICE_CLASS(klass);
95
96 dc->realize = loongarch_pch_msi_realize;
97 dc->unrealize = loongarch_pch_msi_unrealize;
98 device_class_set_props(dc, loongarch_msi_properties);
99 }
100
101 static const TypeInfo loongarch_pch_msi_info = {
102 .name = TYPE_LOONGARCH_PCH_MSI,
103 .parent = TYPE_SYS_BUS_DEVICE,
104 .instance_size = sizeof(LoongArchPCHMSI),
105 .instance_init = loongarch_pch_msi_init,
106 .class_init = loongarch_pch_msi_class_init,
107 };
108
109 static void loongarch_pch_msi_register_types(void)
110 {
111 type_register_static(&loongarch_pch_msi_info);
112 }
113
114 type_init(loongarch_pch_msi_register_types)