| 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
| 7 | * Authors: Sanjay Lal <sanjayl@kymasys.com> |
| 8 | * |
| 9 | * Copyright (C) 2016 Imagination Technologies |
| 10 | */ |
| 11 | |
| 12 | #include "qemu/osdep.h" |
| 13 | #include "qemu/log.h" |
| 14 | #include "qemu/module.h" |
| 15 | #include "qapi/error.h" |
| 16 | #include "hw/core/sysbus.h" |
| 17 | #include "system/memory.h" |
| 18 | #include "system/reset.h" |
| 19 | #include "hw/intc/mips_gic.h" |
| 20 | #include "hw/core/irq.h" |
| 21 | #include "hw/core/qdev-properties.h" |
| 22 | |
| 23 | static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) |
| 24 | { |
| 25 | int ored_level = 0; |
| 26 | int i; |
| 27 | |
| 28 | /* ORing pending registers sharing same pin */ |
| 29 | for (i = 0; i < gic->num_irq; i++) { |
| 30 | if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && |
| 31 | gic->irq_state[i].map_vp == vp && |
| 32 | gic->irq_state[i].enabled) { |
| 33 | ored_level |= gic->irq_state[i].pending; |
| 34 | } |
| 35 | if (ored_level) { |
| 36 | /* no need to iterate all interrupts */ |
| 37 | break; |
| 38 | } |
| 39 | } |
| 40 | if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && |
| 41 | (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { |
| 42 | /* ORing with local pending register (count/compare) */ |
| 43 | ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >> |
| 44 | GIC_VP_MASK_CMP_SHF; |
| 45 | } |
| 46 | qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET], ored_level); |
| 47 | } |
| 48 | |
| 49 | static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ) |
| 50 | { |
| 51 | int vp = gic->irq_state[n_IRQ].map_vp; |
| 52 | int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK; |
| 53 | |
| 54 | if (vp < 0 || vp >= gic->num_vps) { |
| 55 | return; |
| 56 | } |
| 57 | mips_gic_set_vp_irq(gic, vp, pin); |
| 58 | } |
| 59 | |
| 60 | static void gic_set_irq(void *opaque, int n_IRQ, int level) |
| 61 | { |
| 62 | MIPSGICState *gic = (MIPSGICState *) opaque; |
| 63 | |
| 64 | gic->irq_state[n_IRQ].pending = (uint8_t) level; |
| 65 | if (!gic->irq_state[n_IRQ].enabled) { |
| 66 | /* GIC interrupt source disabled */ |
| 67 | return; |
| 68 | } |
| 69 | gic_update_pin_for_irq(gic, n_IRQ); |
| 70 | } |
| 71 | |
| 72 | #define OFFSET_CHECK(c) \ |
| 73 | do { \ |
| 74 | if (!(c)) { \ |
| 75 | goto bad_offset; \ |
| 76 | } \ |
| 77 | } while (0) |
| 78 | |
| 79 | /* GIC Read VP Local/Other Registers */ |
| 80 | static uint64_t gic_read_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr, |
| 81 | unsigned size) |
| 82 | { |
| 83 | switch (addr) { |
| 84 | case GIC_VP_CTL_OFS: |
| 85 | return gic->vps[vp_index].ctl; |
| 86 | case GIC_VP_PEND_OFS: |
| 87 | mips_gictimer_get_sh_count(gic->gic_timer); |
| 88 | return gic->vps[vp_index].pend; |
| 89 | case GIC_VP_MASK_OFS: |
| 90 | return gic->vps[vp_index].mask; |
| 91 | case GIC_VP_COMPARE_MAP_OFS: |
| 92 | return gic->vps[vp_index].compare_map; |
| 93 | case GIC_VP_OTHER_ADDR_OFS: |
| 94 | return gic->vps[vp_index].other_addr; |
| 95 | case GIC_VP_IDENT_OFS: |
| 96 | return vp_index; |
| 97 | case GIC_VP_COMPARE_LO_OFS: |
| 98 | return mips_gictimer_get_vp_compare(gic->gic_timer, vp_index); |
| 99 | case GIC_VP_COMPARE_HI_OFS: |
| 100 | return 0; |
| 101 | default: |
| 102 | qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset LOCAL/OTHER 0x%" |
| 103 | PRIx64 "\n", size, addr); |
| 104 | break; |
| 105 | } |
| 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | static uint64_t gic_read(void *opaque, hwaddr addr, unsigned size) |
| 110 | { |
| 111 | MIPSGICState *gic = (MIPSGICState *) opaque; |
| 112 | uint32_t vp_index = current_cpu->cpu_index; |
| 113 | uint64_t ret = 0; |
| 114 | int i, base, irq_src; |
| 115 | uint32_t other_index; |
| 116 | |
| 117 | switch (addr) { |
| 118 | case GIC_SH_CONFIG_OFS: |
| 119 | ret = gic->sh_config | (mips_gictimer_get_countstop(gic->gic_timer) << |
| 120 | GIC_SH_CONFIG_COUNTSTOP_SHF); |
| 121 | break; |
| 122 | case GIC_SH_COUNTERLO_OFS: |
| 123 | ret = mips_gictimer_get_sh_count(gic->gic_timer); |
| 124 | break; |
| 125 | case GIC_SH_COUNTERHI_OFS: |
| 126 | ret = 0; |
| 127 | break; |
| 128 | case GIC_SH_PEND_OFS ... GIC_SH_PEND_LAST_OFS: |
| 129 | /* each bit represents pending status for an interrupt pin */ |
| 130 | base = (addr - GIC_SH_PEND_OFS) * 8; |
| 131 | OFFSET_CHECK((base + size * 8) <= gic->num_irq); |
| 132 | for (i = 0; i < size * 8; i++) { |
| 133 | ret |= (uint64_t) (gic->irq_state[base + i].pending) << i; |
| 134 | } |
| 135 | break; |
| 136 | case GIC_SH_MASK_OFS ... GIC_SH_MASK_LAST_OFS: |
| 137 | /* each bit represents status for an interrupt pin */ |
| 138 | base = (addr - GIC_SH_MASK_OFS) * 8; |
| 139 | OFFSET_CHECK((base + size * 8) <= gic->num_irq); |
| 140 | for (i = 0; i < size * 8; i++) { |
| 141 | ret |= (uint64_t) (gic->irq_state[base + i].enabled) << i; |
| 142 | } |
| 143 | break; |
| 144 | case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS: |
| 145 | /* 32 bits per a pin */ |
| 146 | irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4; |
| 147 | OFFSET_CHECK(irq_src < gic->num_irq); |
| 148 | ret = gic->irq_state[irq_src].map_pin; |
| 149 | break; |
| 150 | case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS: |
| 151 | /* up to 32 bytes per a pin */ |
| 152 | irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32; |
| 153 | OFFSET_CHECK(irq_src < gic->num_irq); |
| 154 | if ((gic->irq_state[irq_src].map_vp) >= 0) { |
| 155 | ret = (uint64_t) 1 << (gic->irq_state[irq_src].map_vp); |
| 156 | } else { |
| 157 | ret = 0; |
| 158 | } |
| 159 | break; |
| 160 | /* VP-Local Register */ |
| 161 | case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP): |
| 162 | ret = gic_read_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, size); |
| 163 | break; |
| 164 | /* VP-Other Register */ |
| 165 | case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP): |
| 166 | other_index = gic->vps[vp_index].other_addr; |
| 167 | ret = gic_read_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, size); |
| 168 | break; |
| 169 | /* User-Mode Visible section */ |
| 170 | case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO: |
| 171 | ret = mips_gictimer_get_sh_count(gic->gic_timer); |
| 172 | break; |
| 173 | case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI: |
| 174 | ret = 0; |
| 175 | break; |
| 176 | default: |
| 177 | qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset 0x%" PRIx64 "\n", |
| 178 | size, addr); |
| 179 | break; |
| 180 | } |
| 181 | return ret; |
| 182 | bad_offset: |
| 183 | qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr); |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | static void gic_timer_expire_cb(void *opaque, uint32_t vp_index) |
| 188 | { |
| 189 | MIPSGICState *gic = opaque; |
| 190 | |
| 191 | gic->vps[vp_index].pend |= (1 << GIC_LOCAL_INT_COMPARE); |
| 192 | if (gic->vps[vp_index].pend & |
| 193 | (gic->vps[vp_index].mask & GIC_VP_MASK_CMP_MSK)) { |
| 194 | if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) { |
| 195 | /* it is safe to set the irq high regardless of other GIC IRQs */ |
| 196 | uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK); |
| 197 | qemu_irq_raise(gic->vps[vp_index].env->irq |
| 198 | [pin + GIC_CPU_PIN_OFFSET]); |
| 199 | } |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | static void gic_timer_store_vp_compare(MIPSGICState *gic, uint32_t vp_index, |
| 204 | uint64_t compare) |
| 205 | { |
| 206 | gic->vps[vp_index].pend &= ~(1 << GIC_LOCAL_INT_COMPARE); |
| 207 | if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) { |
| 208 | uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK); |
| 209 | mips_gic_set_vp_irq(gic, vp_index, pin); |
| 210 | } |
| 211 | mips_gictimer_store_vp_compare(gic->gic_timer, vp_index, compare); |
| 212 | } |
| 213 | |
| 214 | /* GIC Write VP Local/Other Registers */ |
| 215 | static void gic_write_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr, |
| 216 | uint64_t data, unsigned size) |
| 217 | { |
| 218 | switch (addr) { |
| 219 | case GIC_VP_CTL_OFS: |
| 220 | /* EIC isn't supported */ |
| 221 | break; |
| 222 | case GIC_VP_RMASK_OFS: |
| 223 | gic->vps[vp_index].mask &= ~(data & GIC_VP_SET_RESET_MSK) & |
| 224 | GIC_VP_SET_RESET_MSK; |
| 225 | break; |
| 226 | case GIC_VP_SMASK_OFS: |
| 227 | gic->vps[vp_index].mask |= data & GIC_VP_SET_RESET_MSK; |
| 228 | break; |
| 229 | case GIC_VP_COMPARE_MAP_OFS: |
| 230 | /* EIC isn't supported */ |
| 231 | OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX); |
| 232 | gic->vps[vp_index].compare_map = data & GIC_MAP_TO_PIN_REG_MSK; |
| 233 | break; |
| 234 | case GIC_VP_OTHER_ADDR_OFS: |
| 235 | OFFSET_CHECK(data < gic->num_vps); |
| 236 | gic->vps[vp_index].other_addr = data; |
| 237 | break; |
| 238 | case GIC_VP_COMPARE_LO_OFS: |
| 239 | gic_timer_store_vp_compare(gic, vp_index, data); |
| 240 | break; |
| 241 | default: |
| 242 | qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset LOCAL/OTHER " |
| 243 | "0x%" PRIx64" 0x%08" PRIx64 "\n", size, addr, data); |
| 244 | break; |
| 245 | } |
| 246 | return; |
| 247 | bad_offset: |
| 248 | qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr); |
| 249 | } |
| 250 | |
| 251 | static void gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) |
| 252 | { |
| 253 | int intr; |
| 254 | MIPSGICState *gic = (MIPSGICState *) opaque; |
| 255 | uint32_t vp_index = current_cpu->cpu_index; |
| 256 | int i, base, irq_src; |
| 257 | uint32_t other_index; |
| 258 | |
| 259 | switch (addr) { |
| 260 | case GIC_SH_CONFIG_OFS: |
| 261 | { |
| 262 | uint32_t pre_cntstop = mips_gictimer_get_countstop(gic->gic_timer); |
| 263 | uint32_t new_cntstop = (data & GIC_SH_CONFIG_COUNTSTOP_MSK) >> |
| 264 | GIC_SH_CONFIG_COUNTSTOP_SHF; |
| 265 | if (pre_cntstop != new_cntstop) { |
| 266 | if (new_cntstop == 1) { |
| 267 | mips_gictimer_stop_count(gic->gic_timer); |
| 268 | } else { |
| 269 | mips_gictimer_start_count(gic->gic_timer); |
| 270 | } |
| 271 | } |
| 272 | } |
| 273 | break; |
| 274 | case GIC_SH_COUNTERLO_OFS: |
| 275 | if (mips_gictimer_get_countstop(gic->gic_timer)) { |
| 276 | mips_gictimer_store_sh_count(gic->gic_timer, data); |
| 277 | } |
| 278 | break; |
| 279 | case GIC_SH_RMASK_OFS ... GIC_SH_RMASK_LAST_OFS: |
| 280 | /* up to 64 bits per a pin */ |
| 281 | base = (addr - GIC_SH_RMASK_OFS) * 8; |
| 282 | OFFSET_CHECK((base + size * 8) <= gic->num_irq); |
| 283 | for (i = 0; i < size * 8; i++) { |
| 284 | gic->irq_state[base + i].enabled &= !((data >> i) & 1); |
| 285 | gic_update_pin_for_irq(gic, base + i); |
| 286 | } |
| 287 | break; |
| 288 | case GIC_SH_WEDGE_OFS: |
| 289 | /* Figure out which VP/HW Interrupt this maps to */ |
| 290 | intr = data & ~GIC_SH_WEDGE_RW_MSK; |
| 291 | /* Mask/Enabled Checks */ |
| 292 | OFFSET_CHECK(intr < gic->num_irq); |
| 293 | if (data & GIC_SH_WEDGE_RW_MSK) { |
| 294 | gic_set_irq(gic, intr, 1); |
| 295 | } else { |
| 296 | gic_set_irq(gic, intr, 0); |
| 297 | } |
| 298 | break; |
| 299 | case GIC_SH_SMASK_OFS ... GIC_SH_SMASK_LAST_OFS: |
| 300 | /* up to 64 bits per a pin */ |
| 301 | base = (addr - GIC_SH_SMASK_OFS) * 8; |
| 302 | OFFSET_CHECK((base + size * 8) <= gic->num_irq); |
| 303 | for (i = 0; i < size * 8; i++) { |
| 304 | gic->irq_state[base + i].enabled |= (data >> i) & 1; |
| 305 | gic_update_pin_for_irq(gic, base + i); |
| 306 | } |
| 307 | break; |
| 308 | case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS: |
| 309 | /* 32 bits per a pin */ |
| 310 | irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4; |
| 311 | OFFSET_CHECK(irq_src < gic->num_irq); |
| 312 | /* EIC isn't supported */ |
| 313 | OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX); |
| 314 | gic->irq_state[irq_src].map_pin = data & GIC_MAP_TO_PIN_REG_MSK; |
| 315 | break; |
| 316 | case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS: |
| 317 | /* up to 32 bytes per a pin */ |
| 318 | irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32; |
| 319 | OFFSET_CHECK(irq_src < gic->num_irq); |
| 320 | if (ctz64(data) >= gic->num_vps) { |
| 321 | qemu_log_mask(LOG_GUEST_ERROR, "Bad data value 0x%" PRIx64 |
| 322 | " at MAP VP register offset 0x%" PRIx64 "\n", |
| 323 | data, addr); |
| 324 | break; |
| 325 | } |
| 326 | gic->irq_state[irq_src].map_vp = ctz64(data); |
| 327 | break; |
| 328 | case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP): |
| 329 | gic_write_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, data, size); |
| 330 | break; |
| 331 | case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP): |
| 332 | other_index = gic->vps[vp_index].other_addr; |
| 333 | gic_write_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, data, size); |
| 334 | break; |
| 335 | case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO: |
| 336 | case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI: |
| 337 | /* do nothing. Read-only section */ |
| 338 | break; |
| 339 | default: |
| 340 | qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset 0x%" PRIx64 |
| 341 | " 0x%08" PRIx64 "\n", size, addr, data); |
| 342 | break; |
| 343 | } |
| 344 | return; |
| 345 | bad_offset: |
| 346 | qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr); |
| 347 | } |
| 348 | |
| 349 | static void gic_reset(void *opaque) |
| 350 | { |
| 351 | int i; |
| 352 | MIPSGICState *gic = (MIPSGICState *) opaque; |
| 353 | int numintrs = (gic->num_irq / 8) - 1; |
| 354 | |
| 355 | gic->sh_config = /* COUNTSTOP = 0 it is accessible via MIPSGICTimer*/ |
| 356 | /* CounterHi not implemented */ |
| 357 | (0 << GIC_SH_CONFIG_COUNTBITS_SHF) | |
| 358 | (numintrs << GIC_SH_CONFIG_NUMINTRS_SHF) | |
| 359 | (gic->num_vps << GIC_SH_CONFIG_PVPS_SHF); |
| 360 | for (i = 0; i < gic->num_vps; i++) { |
| 361 | gic->vps[i].ctl = 0x0; |
| 362 | gic->vps[i].pend = 0x0; |
| 363 | /* PERFCNT, TIMER and WD not implemented */ |
| 364 | gic->vps[i].mask = 0x32; |
| 365 | gic->vps[i].compare_map = GIC_MAP_TO_PIN_MSK; |
| 366 | mips_gictimer_store_vp_compare(gic->gic_timer, i, 0xffffffff); |
| 367 | gic->vps[i].other_addr = 0x0; |
| 368 | } |
| 369 | for (i = 0; i < gic->num_irq; i++) { |
| 370 | gic->irq_state[i].enabled = 0; |
| 371 | gic->irq_state[i].pending = 0; |
| 372 | gic->irq_state[i].map_pin = GIC_MAP_TO_PIN_MSK; |
| 373 | gic->irq_state[i].map_vp = -1; |
| 374 | } |
| 375 | mips_gictimer_store_sh_count(gic->gic_timer, 0); |
| 376 | /* COUNTSTOP = 0 */ |
| 377 | mips_gictimer_start_count(gic->gic_timer); |
| 378 | } |
| 379 | |
| 380 | static const MemoryRegionOps gic_ops = { |
| 381 | .read = gic_read, |
| 382 | .write = gic_write, |
| 383 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 384 | .impl = { |
| 385 | .max_access_size = 8, |
| 386 | }, |
| 387 | }; |
| 388 | |
| 389 | static void mips_gic_init(Object *obj) |
| 390 | { |
| 391 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 392 | MIPSGICState *s = MIPS_GIC(obj); |
| 393 | |
| 394 | memory_region_init_io(&s->mr, OBJECT(s), &gic_ops, s, |
| 395 | "mips-gic", GIC_ADDRSPACE_SZ); |
| 396 | sysbus_init_mmio(sbd, &s->mr); |
| 397 | qemu_register_reset(gic_reset, s); |
| 398 | } |
| 399 | |
| 400 | static void mips_gic_realize(DeviceState *dev, Error **errp) |
| 401 | { |
| 402 | MIPSGICState *s = MIPS_GIC(dev); |
| 403 | CPUState *cs = first_cpu; |
| 404 | int i; |
| 405 | |
| 406 | if (s->num_vps > GIC_MAX_VPS) { |
| 407 | error_setg(errp, "Exceeded maximum CPUs %d", s->num_vps); |
| 408 | return; |
| 409 | } |
| 410 | if ((s->num_irq > GIC_MAX_INTRS) || (s->num_irq % 8) || (s->num_irq <= 0)) { |
| 411 | error_setg(errp, "GIC supports up to %d external interrupts in " |
| 412 | "multiples of 8 : %d", GIC_MAX_INTRS, s->num_irq); |
| 413 | return; |
| 414 | } |
| 415 | s->vps = g_new(MIPSGICVPState, s->num_vps); |
| 416 | s->irq_state = g_new(MIPSGICIRQState, s->num_irq); |
| 417 | /* Register the env for all VPs with the GIC */ |
| 418 | for (i = 0; i < s->num_vps; i++) { |
| 419 | if (cs != NULL) { |
| 420 | s->vps[i].env = cpu_env(cs); |
| 421 | cs = CPU_NEXT(cs); |
| 422 | } else { |
| 423 | error_setg(errp, |
| 424 | "Unable to initialize GIC, CPUState for CPU#%d not valid.", i); |
| 425 | return; |
| 426 | } |
| 427 | } |
| 428 | s->gic_timer = mips_gictimer_init(s, s->num_vps, gic_timer_expire_cb); |
| 429 | qdev_init_gpio_in(dev, gic_set_irq, s->num_irq); |
| 430 | for (i = 0; i < s->num_irq; i++) { |
| 431 | s->irq_state[i].irq = qdev_get_gpio_in(dev, i); |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | static const Property mips_gic_properties[] = { |
| 436 | DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1), |
| 437 | DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256), |
| 438 | }; |
| 439 | |
| 440 | static void mips_gic_class_init(ObjectClass *klass, const void *data) |
| 441 | { |
| 442 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 443 | |
| 444 | device_class_set_props(dc, mips_gic_properties); |
| 445 | dc->realize = mips_gic_realize; |
| 446 | } |
| 447 | |
| 448 | static const TypeInfo mips_gic_info = { |
| 449 | .name = TYPE_MIPS_GIC, |
| 450 | .parent = TYPE_SYS_BUS_DEVICE, |
| 451 | .instance_size = sizeof(MIPSGICState), |
| 452 | .instance_init = mips_gic_init, |
| 453 | .class_init = mips_gic_class_init, |
| 454 | }; |
| 455 | |
| 456 | static void mips_gic_register_types(void) |
| 457 | { |
| 458 | type_register_static(&mips_gic_info); |
| 459 | } |
| 460 | |
| 461 | type_init(mips_gic_register_types) |