| 1 | /* |
| 2 | * QEMU PowerPC XIVE2 interrupt controller model (POWER10) |
| 3 | * |
| 4 | * Copyright (c) 2019-2022, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef PPC_PNV_XIVE2_REGS_H |
| 11 | #define PPC_PNV_XIVE2_REGS_H |
| 12 | |
| 13 | /* |
| 14 | * CQ Common Queue (PowerBus bridge) Registers |
| 15 | */ |
| 16 | |
| 17 | /* XIVE2 Capabilities */ |
| 18 | #define X_CQ_XIVE_CAP 0x02 |
| 19 | #define CQ_XIVE_CAP 0x010 |
| 20 | #define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3) |
| 21 | /* 4:6 reserved */ |
| 22 | #define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8, 9) |
| 23 | #define CQ_XIVE_CAP_USER_INT_PRIO_1 0 |
| 24 | #define CQ_XIVE_CAP_USER_INT_PRIO_1_2 1 |
| 25 | #define CQ_XIVE_CAP_USER_INT_PRIO_1_4 2 |
| 26 | #define CQ_XIVE_CAP_USER_INT_PRIO_1_8 3 |
| 27 | #define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10, 11) |
| 28 | #define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0 |
| 29 | #define CQ_XIVE_CAP_VP_INT_PRIO_2_8 1 |
| 30 | #define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2 |
| 31 | #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 |
| 32 | #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) |
| 33 | #define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38) |
| 34 | |
| 35 | #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) |
| 36 | #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) |
| 37 | #define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) |
| 38 | #define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) |
| 39 | |
| 40 | /* XIVE2 Configuration */ |
| 41 | #define X_CQ_XIVE_CFG 0x03 |
| 42 | #define CQ_XIVE_CFG 0x018 |
| 43 | |
| 44 | /* 0:7 reserved */ |
| 45 | #define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8, 9) |
| 46 | #define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10, 11) |
| 47 | #define CQ_XIVE_CFG_INT_PRIO_1 0 |
| 48 | #define CQ_XIVE_CFG_INT_PRIO_2 1 |
| 49 | #define CQ_XIVE_CFG_INT_PRIO_4 2 |
| 50 | #define CQ_XIVE_CFG_INT_PRIO_8 3 |
| 51 | #define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) |
| 52 | #define CQ_XIVE_CFG_BLOCK_ID_4BITS 0 |
| 53 | #define CQ_XIVE_CFG_BLOCK_ID_5BITS 1 |
| 54 | #define CQ_XIVE_CFG_BLOCK_ID_6BITS 2 |
| 55 | #define CQ_XIVE_CFG_BLOCK_ID_7BITS 3 |
| 56 | #define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14, 15) |
| 57 | #define CQ_XIVE_CFG_THREADID_7BITS 0 |
| 58 | #define CQ_XIVE_CFG_THREADID_8BITS 1 |
| 59 | #define CQ_XIVE_CFG_THREADID_9BITS 2 |
| 60 | #define CQ_XIVE_CFG_THREADID_10BITs 3 |
| 61 | #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16) |
| 62 | #define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23) |
| 63 | |
| 64 | #define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24) |
| 65 | #define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25) |
| 66 | #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */ |
| 67 | #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */ |
| 68 | #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28) |
| 69 | #define CQ_XIVE_CFG_EN_VP_GRP_PRIORITY PPC_BIT(32) /* 0 if bit[25]=1 */ |
| 70 | #define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */ |
| 71 | #define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */ |
| 72 | |
| 73 | /* Interrupt Controller Base Address Register - 512 pages (32M) */ |
| 74 | #define X_CQ_IC_BAR 0x08 |
| 75 | #define CQ_IC_BAR 0x040 |
| 76 | #define CQ_IC_BAR_VALID PPC_BIT(0) |
| 77 | #define CQ_IC_BAR_64K PPC_BIT(1) |
| 78 | /* 2:7 reserved */ |
| 79 | #define CQ_IC_BAR_ADDR PPC_BITMASK(8, 42) |
| 80 | /* 43:63 reserved */ |
| 81 | |
| 82 | /* Thread Management Base Address Register - 4 pages */ |
| 83 | #define X_CQ_TM_BAR 0x09 |
| 84 | #define CQ_TM_BAR 0x048 |
| 85 | #define CQ_TM_BAR_VALID PPC_BIT(0) |
| 86 | #define CQ_TM_BAR_64K PPC_BIT(1) |
| 87 | #define CQ_TM_BAR_ADDR PPC_BITMASK(8, 49) |
| 88 | |
| 89 | /* ESB Base Address Register */ |
| 90 | #define X_CQ_ESB_BAR 0x0A |
| 91 | #define CQ_ESB_BAR 0x050 |
| 92 | #define CQ_BAR_VALID PPC_BIT(0) |
| 93 | #define CQ_BAR_64K PPC_BIT(1) |
| 94 | /* 2:7 reserved */ |
| 95 | #define CQ_BAR_ADDR PPC_BITMASK(8, 39) |
| 96 | #define CQ_BAR_SET_DIV PPC_BITMASK(56, 58) |
| 97 | #define CQ_BAR_RANGE PPC_BITMASK(59, 63) |
| 98 | /* 0 (16M) - 16 (16T) */ |
| 99 | |
| 100 | /* END Base Address Register */ |
| 101 | #define X_CQ_END_BAR 0x0B |
| 102 | #define CQ_END_BAR 0x058 |
| 103 | |
| 104 | /* NVPG Base Address Register */ |
| 105 | #define X_CQ_NVPG_BAR 0x0C |
| 106 | #define CQ_NVPG_BAR 0x060 |
| 107 | |
| 108 | /* NVC Base Address Register */ |
| 109 | #define X_CQ_NVC_BAR 0x0D |
| 110 | #define CQ_NVC_BAR 0x068 |
| 111 | |
| 112 | /* Table Address Register */ |
| 113 | #define X_CQ_TAR 0x0E |
| 114 | #define CQ_TAR 0x070 |
| 115 | #define CQ_TAR_AUTOINC PPC_BIT(0) |
| 116 | #define CQ_TAR_SELECT PPC_BITMASK(12, 15) |
| 117 | #define CQ_TAR_ESB 0 /* 0 - 15 */ |
| 118 | #define CQ_TAR_END 2 /* 0 - 15 */ |
| 119 | #define CQ_TAR_NVPG 3 /* 0 - 15 */ |
| 120 | #define CQ_TAR_NVC 5 /* 0 - 15 */ |
| 121 | #define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28, 31) |
| 122 | |
| 123 | /* Table Data Register */ |
| 124 | #define X_CQ_TDR 0x0F |
| 125 | #define CQ_TDR 0x078 |
| 126 | /* for the NVPG, NVC, ESB, END Set Translation Tables */ |
| 127 | #define CQ_TDR_VALID PPC_BIT(0) |
| 128 | #define CQ_TDR_BLOCK_ID PPC_BITMASK(60, 63) |
| 129 | |
| 130 | /* |
| 131 | * Processor Cores Enabled for MsgSnd |
| 132 | * Identifies which of the 32 possible core chiplets are enabled and |
| 133 | * available to receive the MsgSnd command |
| 134 | */ |
| 135 | #define X_CQ_MSGSND 0x10 |
| 136 | #define CQ_MSGSND 0x080 |
| 137 | |
| 138 | /* Interrupt Unit Reset Control */ |
| 139 | #define X_CQ_RST_CTL 0x12 |
| 140 | #define CQ_RST_CTL 0x090 |
| 141 | #define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */ |
| 142 | #define CQ_RST_QUIESCE_PB PPC_BIT(1) /* RW */ |
| 143 | #define CQ_RST_MASTER_IDLE PPC_BIT(2) /* Read Only */ |
| 144 | #define CQ_RST_SAVE_IDLE PPC_BIT(3) /* Read Only */ |
| 145 | #define CQ_RST_PB_BAR_RESET PPC_BIT(4) /* Write Only */ |
| 146 | |
| 147 | /* PowerBus General Configuration */ |
| 148 | #define X_CQ_CFG_PB_GEN 0x14 |
| 149 | #define CQ_CFG_PB_GEN 0x0A0 |
| 150 | #define CQ_CFG_PB_GEN_PB_INIT PPC_BIT(45) |
| 151 | |
| 152 | /* |
| 153 | * FIR |
| 154 | * (And-Mask) |
| 155 | * (Or-Mask) |
| 156 | */ |
| 157 | #define X_CQ_FIR 0x30 |
| 158 | #define X_CQ_FIR_AND 0x31 |
| 159 | #define X_CQ_FIR_OR 0x32 |
| 160 | #define CQ_FIR 0x180 |
| 161 | #define CQ_FIR_AND 0x188 |
| 162 | #define CQ_FIR_OR 0x190 |
| 163 | #define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) |
| 164 | #define CQ_FIR_VC_INFO_ERROR_0_2 PPC_BITMASK(61, 63) |
| 165 | |
| 166 | /* |
| 167 | * FIR Mask |
| 168 | * (And-Mask) |
| 169 | * (Or-Mask) |
| 170 | */ |
| 171 | #define X_CQ_FIRMASK 0x33 |
| 172 | #define X_CQ_FIRMASK_AND 0x34 |
| 173 | #define X_CQ_FIRMASK_OR 0x35 |
| 174 | #define CQ_FIRMASK 0x198 |
| 175 | #define CQ_FIRMASK_AND 0x1A0 |
| 176 | #define CQ_FIRMASK_OR 0x1A8 |
| 177 | |
| 178 | /* |
| 179 | * VC0 |
| 180 | */ |
| 181 | |
| 182 | /* VSD table address */ |
| 183 | #define X_VC_VSD_TABLE_ADDR 0x100 |
| 184 | #define VC_VSD_TABLE_ADDR 0x000 |
| 185 | #define VC_VSD_TABLE_AUTOINC PPC_BIT(0) |
| 186 | #define VC_VSD_TABLE_SELECT PPC_BITMASK(12, 15) |
| 187 | #define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31) |
| 188 | |
| 189 | /* VSD table data */ |
| 190 | #define X_VC_VSD_TABLE_DATA 0x101 |
| 191 | #define VC_VSD_TABLE_DATA 0x008 |
| 192 | |
| 193 | /* AIB AT macro indirect kill */ |
| 194 | #define X_VC_AT_MACRO_KILL 0x102 |
| 195 | #define VC_AT_MACRO_KILL 0x010 |
| 196 | #define VC_AT_MACRO_KILL_VALID PPC_BIT(0) |
| 197 | #define VC_AT_MACRO_KILL_VSD PPC_BITMASK(12, 15) |
| 198 | #define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28, 31) |
| 199 | #define VC_AT_MACRO_KILL_OFFSET PPC_BITMASK(48, 60) |
| 200 | |
| 201 | /* AIB AT macro indirect kill mask (same bit definitions) */ |
| 202 | #define X_VC_AT_MACRO_KILL_MASK 0x103 |
| 203 | #define VC_AT_MACRO_KILL_MASK 0x018 |
| 204 | |
| 205 | /* Remote IRQs and ERQs configuration [n] (n = 0:6) */ |
| 206 | #define X_VC_QUEUES_CFG_REM0 0x117 |
| 207 | |
| 208 | #define VC_QUEUES_CFG_REM0 0x0B8 |
| 209 | #define VC_QUEUES_CFG_REM1 0x0C0 |
| 210 | #define VC_QUEUES_CFG_REM2 0x0C8 |
| 211 | #define VC_QUEUES_CFG_REM3 0x0D0 |
| 212 | #define VC_QUEUES_CFG_REM4 0x0D8 |
| 213 | #define VC_QUEUES_CFG_REM5 0x0E0 |
| 214 | #define VC_QUEUES_CFG_REM6 0x0E8 |
| 215 | #define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38) |
| 216 | #define VC_QUEUES_CFG_MEMB_SZ PPC_BITMASK(42, 47) |
| 217 | |
| 218 | /* |
| 219 | * VC1 |
| 220 | */ |
| 221 | |
| 222 | /* ESBC cache flush control trigger */ |
| 223 | #define X_VC_ESBC_FLUSH_CTRL 0x140 |
| 224 | #define VC_ESBC_FLUSH_CTRL 0x200 |
| 225 | #define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) |
| 226 | #define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) |
| 227 | |
| 228 | /* ESBC cache flush poll trigger */ |
| 229 | #define X_VC_ESBC_FLUSH_POLL 0x141 |
| 230 | #define VC_ESBC_FLUSH_POLL 0x208 |
| 231 | #define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3) |
| 232 | #define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */ |
| 233 | #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) |
| 234 | #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ |
| 235 | |
| 236 | /* ESBC cache flush inject register */ |
| 237 | #define X_VC_ESBC_FLUSH_INJECT 0x142 |
| 238 | #define VC_ESBC_FLUSH_INJECT 0x210 |
| 239 | |
| 240 | /* ESBC configuration */ |
| 241 | #define X_VC_ESBC_CFG 0x148 |
| 242 | #define VC_ESBC_CFG 0x240 |
| 243 | |
| 244 | /* EASC flush control register */ |
| 245 | #define X_VC_EASC_FLUSH_CTRL 0x160 |
| 246 | #define VC_EASC_FLUSH_CTRL 0x300 |
| 247 | #define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) |
| 248 | #define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) |
| 249 | |
| 250 | /* EASC flush poll register */ |
| 251 | #define X_VC_EASC_FLUSH_POLL 0x161 |
| 252 | #define VC_EASC_FLUSH_POLL 0x308 |
| 253 | #define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3) |
| 254 | #define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */ |
| 255 | #define VC_EASC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) |
| 256 | #define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ |
| 257 | |
| 258 | /* EASC flush inject register */ |
| 259 | #define X_VC_EASC_FLUSH_INJECT 0x162 |
| 260 | #define VC_EASC_FLUSH_INJECT 0x310 |
| 261 | |
| 262 | /* |
| 263 | * VC2 |
| 264 | */ |
| 265 | |
| 266 | /* ENDC flush control register */ |
| 267 | #define X_VC_ENDC_FLUSH_CTRL 0x180 |
| 268 | #define VC_ENDC_FLUSH_CTRL 0x400 |
| 269 | #define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) |
| 270 | #define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) |
| 271 | #define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) |
| 272 | #define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) |
| 273 | |
| 274 | /* ENDC flush poll register */ |
| 275 | #define X_VC_ENDC_FLUSH_POLL 0x181 |
| 276 | #define VC_ENDC_FLUSH_POLL 0x408 |
| 277 | #define VC_ENDC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7) |
| 278 | #define VC_ENDC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */ |
| 279 | #define VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39) |
| 280 | #define VC_ENDC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */ |
| 281 | |
| 282 | /* ENDC flush inject register */ |
| 283 | #define X_VC_ENDC_FLUSH_INJECT 0x182 |
| 284 | #define VC_ENDC_FLUSH_INJECT 0x410 |
| 285 | |
| 286 | /* ENDC Sync done */ |
| 287 | #define X_VC_ENDC_SYNC_DONE 0x184 |
| 288 | #define VC_ENDC_SYNC_DONE 0x420 |
| 289 | #define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0, 6) |
| 290 | #define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0) |
| 291 | #define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1) |
| 292 | #define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2) |
| 293 | #define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3) |
| 294 | #define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4) |
| 295 | #define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5) |
| 296 | #define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6) |
| 297 | #define VC_QUEUE_COUNT 7 |
| 298 | |
| 299 | /* ENDC cache watch assign */ |
| 300 | #define X_VC_ENDC_WATCH_ASSIGN 0x186 |
| 301 | #define VC_ENDC_WATCH_ASSIGN 0x430 |
| 302 | |
| 303 | /* ENDC configuration register */ |
| 304 | #define X_VC_ENDC_CFG 0x188 |
| 305 | #define VC_ENDC_CFG 0x440 |
| 306 | #define VC_ENDC_CFG_CACHE_WATCH_ASSIGN PPC_BITMASK(32, 35) |
| 307 | |
| 308 | /* ENDC cache watch specification 0 */ |
| 309 | #define X_VC_ENDC_WATCH0_SPEC 0x1A0 |
| 310 | #define VC_ENDC_WATCH0_SPEC 0x500 |
| 311 | #define VC_ENDC_WATCH_CONFLICT PPC_BIT(0) |
| 312 | #define VC_ENDC_WATCH_FULL PPC_BIT(8) |
| 313 | #define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) |
| 314 | #define VC_ENDC_WATCH_INDEX PPC_BITMASK(40, 63) |
| 315 | |
| 316 | /* ENDC cache watch data 0 */ |
| 317 | #define X_VC_ENDC_WATCH0_DATA0 0x1A4 |
| 318 | #define X_VC_ENDC_WATCH0_DATA1 0x1A5 |
| 319 | #define X_VC_ENDC_WATCH0_DATA2 0x1A6 |
| 320 | #define X_VC_ENDC_WATCH0_DATA3 0x1A7 |
| 321 | |
| 322 | #define VC_ENDC_WATCH0_DATA0 0x520 |
| 323 | #define VC_ENDC_WATCH0_DATA1 0x528 |
| 324 | #define VC_ENDC_WATCH0_DATA2 0x530 |
| 325 | #define VC_ENDC_WATCH0_DATA3 0x538 |
| 326 | |
| 327 | /* ENDC cache watch 1 */ |
| 328 | #define X_VC_ENDC_WATCH1_SPEC 0x1A8 |
| 329 | #define VC_ENDC_WATCH1_SPEC 0x540 |
| 330 | #define X_VC_ENDC_WATCH1_DATA0 0x1AC |
| 331 | #define X_VC_ENDC_WATCH1_DATA1 0x1AD |
| 332 | #define X_VC_ENDC_WATCH1_DATA2 0x1AE |
| 333 | #define X_VC_ENDC_WATCH1_DATA3 0x1AF |
| 334 | #define VC_ENDC_WATCH1_DATA0 0x560 |
| 335 | #define VC_ENDC_WATCH1_DATA1 0x568 |
| 336 | #define VC_ENDC_WATCH1_DATA2 0x570 |
| 337 | #define VC_ENDC_WATCH1_DATA3 0x578 |
| 338 | |
| 339 | /* ENDC cache watch 2 */ |
| 340 | #define X_VC_ENDC_WATCH2_SPEC 0x1B0 |
| 341 | #define VC_ENDC_WATCH2_SPEC 0x580 |
| 342 | #define X_VC_ENDC_WATCH2_DATA0 0x1B4 |
| 343 | #define X_VC_ENDC_WATCH2_DATA1 0x1B5 |
| 344 | #define X_VC_ENDC_WATCH2_DATA2 0x1B6 |
| 345 | #define X_VC_ENDC_WATCH2_DATA3 0x1B7 |
| 346 | #define VC_ENDC_WATCH2_DATA0 0x5A0 |
| 347 | #define VC_ENDC_WATCH2_DATA1 0x5A8 |
| 348 | #define VC_ENDC_WATCH2_DATA2 0x5B0 |
| 349 | #define VC_ENDC_WATCH2_DATA3 0x5B8 |
| 350 | |
| 351 | /* ENDC cache watch 3 */ |
| 352 | #define X_VC_ENDC_WATCH3_SPEC 0x1B8 |
| 353 | #define VC_ENDC_WATCH3_SPEC 0x5C0 |
| 354 | #define X_VC_ENDC_WATCH3_DATA0 0x1BC |
| 355 | #define X_VC_ENDC_WATCH3_DATA1 0x1BD |
| 356 | #define X_VC_ENDC_WATCH3_DATA2 0x1BE |
| 357 | #define X_VC_ENDC_WATCH3_DATA3 0x1BF |
| 358 | #define VC_ENDC_WATCH3_DATA0 0x5E0 |
| 359 | #define VC_ENDC_WATCH3_DATA1 0x5E8 |
| 360 | #define VC_ENDC_WATCH3_DATA2 0x5F0 |
| 361 | #define VC_ENDC_WATCH3_DATA3 0x5F8 |
| 362 | |
| 363 | /* |
| 364 | * PC LSB1 |
| 365 | */ |
| 366 | |
| 367 | /* VSD table address register */ |
| 368 | #define X_PC_VSD_TABLE_ADDR 0x200 |
| 369 | #define PC_VSD_TABLE_ADDR 0x000 |
| 370 | #define PC_VSD_TABLE_AUTOINC PPC_BIT(0) |
| 371 | #define PC_VSD_TABLE_SELECT PPC_BITMASK(12, 15) |
| 372 | #define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31) |
| 373 | |
| 374 | /* VSD table data register */ |
| 375 | #define X_PC_VSD_TABLE_DATA 0x201 |
| 376 | #define PC_VSD_TABLE_DATA 0x008 |
| 377 | |
| 378 | /* AT indirect kill register */ |
| 379 | #define X_PC_AT_KILL 0x202 |
| 380 | #define PC_AT_KILL 0x010 |
| 381 | #define PC_AT_KILL_VALID PPC_BIT(0) |
| 382 | #define PC_AT_KILL_VSD_TYPE PPC_BITMASK(24, 27) |
| 383 | /* Only NVP, NVG, NVC */ |
| 384 | #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(28, 31) |
| 385 | #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60) |
| 386 | |
| 387 | /* AT indirect kill mask register */ |
| 388 | #define X_PC_AT_KILL_MASK 0x203 |
| 389 | #define PC_AT_KILL_MASK 0x018 |
| 390 | #define PC_AT_KILL_MASK_VSD_TYPE PPC_BITMASK(24, 27) |
| 391 | #define PC_AT_KILL_MASK_BLOCK_ID PPC_BITMASK(28, 31) |
| 392 | #define PC_AT_KILL_MASK_OFFSET PPC_BITMASK(48, 60) |
| 393 | |
| 394 | /* |
| 395 | * PC LSB2 |
| 396 | */ |
| 397 | |
| 398 | /* NxC Cache flush control */ |
| 399 | #define X_PC_NXC_FLUSH_CTRL 0x280 |
| 400 | #define PC_NXC_FLUSH_CTRL 0x400 |
| 401 | #define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) |
| 402 | #define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) |
| 403 | #define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) |
| 404 | #define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) |
| 405 | |
| 406 | /* NxC Cache flush poll */ |
| 407 | #define X_PC_NXC_FLUSH_POLL 0x281 |
| 408 | #define PC_NXC_FLUSH_POLL 0x408 |
| 409 | #define PC_NXC_FLUSH_POLL_NXC_TYPE PPC_BITMASK(2, 3) |
| 410 | #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0 |
| 411 | #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVG 2 |
| 412 | #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVC 3 |
| 413 | #define PC_NXC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7) |
| 414 | #define PC_NXC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */ |
| 415 | #define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34, 35) /* 0: Ign */ |
| 416 | #define PC_NXC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39) |
| 417 | #define PC_NXC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */ |
| 418 | |
| 419 | /* NxC Cache flush inject */ |
| 420 | #define X_PC_NXC_FLUSH_INJECT 0x282 |
| 421 | #define PC_NXC_FLUSH_INJECT 0x410 |
| 422 | |
| 423 | /* NxC Cache watch assign */ |
| 424 | #define X_PC_NXC_WATCH_ASSIGN 0x286 |
| 425 | #define PC_NXC_WATCH_ASSIGN 0x430 |
| 426 | |
| 427 | /* NxC Proc config */ |
| 428 | #define X_PC_NXC_PROC_CONFIG 0x28A |
| 429 | #define PC_NXC_PROC_CONFIG 0x450 |
| 430 | #define PC_NXC_PROC_CONFIG_WATCH_ASSIGN PPC_BITMASK(0, 3) |
| 431 | #define PC_NXC_PROC_CONFIG_NVG_TABLE_COMPRESS PPC_BITMASK(32, 35) |
| 432 | #define PC_NXC_PROC_CONFIG_NVC_TABLE_COMPRESS PPC_BITMASK(36, 39) |
| 433 | |
| 434 | /* NxC Cache Watch 0 Specification */ |
| 435 | #define X_PC_NXC_WATCH0_SPEC 0x2A0 |
| 436 | #define PC_NXC_WATCH0_SPEC 0x500 |
| 437 | #define PC_NXC_WATCH_CONFLICT PPC_BIT(0) |
| 438 | #define PC_NXC_WATCH_FULL PPC_BIT(8) |
| 439 | #define PC_NXC_WATCH_NXC_TYPE PPC_BITMASK(26, 27) |
| 440 | #define PC_NXC_WATCH_NXC_NVP 0 |
| 441 | #define PC_NXC_WATCH_NXC_NVG 2 |
| 442 | #define PC_NXC_WATCH_NXC_NVC 3 |
| 443 | #define PC_NXC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) |
| 444 | #define PC_NXC_WATCH_INDEX PPC_BITMASK(40, 63) |
| 445 | |
| 446 | /* NxC Cache Watch 0 Data */ |
| 447 | #define X_PC_NXC_WATCH0_DATA0 0x2A4 |
| 448 | #define X_PC_NXC_WATCH0_DATA1 0x2A5 |
| 449 | #define X_PC_NXC_WATCH0_DATA2 0x2A6 |
| 450 | #define X_PC_NXC_WATCH0_DATA3 0x2A7 |
| 451 | |
| 452 | #define PC_NXC_WATCH0_DATA0 0x520 |
| 453 | #define PC_NXC_WATCH0_DATA1 0x528 |
| 454 | #define PC_NXC_WATCH0_DATA2 0x530 |
| 455 | #define PC_NXC_WATCH0_DATA3 0x538 |
| 456 | |
| 457 | /* NxC Cache Watch 1 */ |
| 458 | #define X_PC_NXC_WATCH1_SPEC 0x2A8 |
| 459 | #define PC_NXC_WATCH1_SPEC 0x540 |
| 460 | #define X_PC_NXC_WATCH1_DATA0 0x2AC |
| 461 | #define X_PC_NXC_WATCH1_DATA1 0x2AD |
| 462 | #define X_PC_NXC_WATCH1_DATA2 0x2AE |
| 463 | #define X_PC_NXC_WATCH1_DATA3 0x2AF |
| 464 | #define PC_NXC_WATCH1_DATA0 0x560 |
| 465 | #define PC_NXC_WATCH1_DATA1 0x568 |
| 466 | #define PC_NXC_WATCH1_DATA2 0x570 |
| 467 | #define PC_NXC_WATCH1_DATA3 0x578 |
| 468 | |
| 469 | /* NxC Cache Watch 2 */ |
| 470 | #define X_PC_NXC_WATCH2_SPEC 0x2B0 |
| 471 | #define PC_NXC_WATCH2_SPEC 0x580 |
| 472 | #define X_PC_NXC_WATCH2_DATA0 0x2B4 |
| 473 | #define X_PC_NXC_WATCH2_DATA1 0x2B5 |
| 474 | #define X_PC_NXC_WATCH2_DATA2 0x2B6 |
| 475 | #define X_PC_NXC_WATCH2_DATA3 0x2B7 |
| 476 | #define PC_NXC_WATCH2_DATA0 0x5A0 |
| 477 | #define PC_NXC_WATCH2_DATA1 0x5A8 |
| 478 | #define PC_NXC_WATCH2_DATA2 0x5B0 |
| 479 | #define PC_NXC_WATCH2_DATA3 0x5B8 |
| 480 | |
| 481 | /* NxC Cache Watch 3 */ |
| 482 | #define X_PC_NXC_WATCH3_SPEC 0x2B8 |
| 483 | #define PC_NXC_WATCH3_SPEC 0x5C0 |
| 484 | #define X_PC_NXC_WATCH3_DATA0 0x2BC |
| 485 | #define X_PC_NXC_WATCH3_DATA1 0x2BD |
| 486 | #define X_PC_NXC_WATCH3_DATA2 0x2BE |
| 487 | #define X_PC_NXC_WATCH3_DATA3 0x2BF |
| 488 | #define PC_NXC_WATCH3_DATA0 0x5E0 |
| 489 | #define PC_NXC_WATCH3_DATA1 0x5E8 |
| 490 | #define PC_NXC_WATCH3_DATA2 0x5F0 |
| 491 | #define PC_NXC_WATCH3_DATA3 0x5F8 |
| 492 | |
| 493 | /* |
| 494 | * TCTXT Registers |
| 495 | */ |
| 496 | |
| 497 | /* Physical Thread Enable0 register */ |
| 498 | #define X_TCTXT_EN0 0x300 |
| 499 | #define TCTXT_EN0 0x000 |
| 500 | |
| 501 | /* Physical Thread Enable0 Set register */ |
| 502 | #define X_TCTXT_EN0_SET 0x302 |
| 503 | #define TCTXT_EN0_SET 0x010 |
| 504 | |
| 505 | /* Physical Thread Enable0 Reset register */ |
| 506 | #define X_TCTXT_EN0_RESET 0x303 |
| 507 | #define TCTXT_EN0_RESET 0x018 |
| 508 | |
| 509 | /* Physical Thread Enable1 register */ |
| 510 | #define X_TCTXT_EN1 0x304 |
| 511 | #define TCTXT_EN1 0x020 |
| 512 | |
| 513 | /* Physical Thread Enable1 Set register */ |
| 514 | #define X_TCTXT_EN1_SET 0x306 |
| 515 | #define TCTXT_EN1_SET 0x030 |
| 516 | |
| 517 | /* Physical Thread Enable1 Reset register */ |
| 518 | #define X_TCTXT_EN1_RESET 0x307 |
| 519 | #define TCTXT_EN1_RESET 0x038 |
| 520 | |
| 521 | /* TCTXT Config register */ |
| 522 | #define X_TCTXT_CFG 0x328 |
| 523 | #define TCTXT_CFG 0x140 |
| 524 | |
| 525 | /* |
| 526 | * VSD Tables |
| 527 | */ |
| 528 | #define VST_ESB 0 |
| 529 | #define VST_EAS 1 /* No used by PC */ |
| 530 | #define VST_END 2 |
| 531 | #define VST_NVP 3 |
| 532 | #define VST_NVG 4 |
| 533 | #define VST_NVC 5 |
| 534 | #define VST_IC 6 /* No used by PC */ |
| 535 | #define VST_SYNC 7 |
| 536 | #define VST_ERQ 8 /* No used by PC */ |
| 537 | |
| 538 | /* |
| 539 | * Bits in a VSD entry. |
| 540 | * |
| 541 | * Note: the address is naturally aligned, we don't use a PPC_BITMASK, |
| 542 | * but just a mask to apply to the address before OR'ing it in. |
| 543 | * |
| 544 | * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the |
| 545 | * VSD and is only meant to be used in indirect mode ! |
| 546 | */ |
| 547 | #define VSD_MODE PPC_BITMASK(0, 1) |
| 548 | #define VSD_MODE_SHARED 1 |
| 549 | #define VSD_MODE_EXCLUSIVE 2 |
| 550 | #define VSD_MODE_FORWARD 3 |
| 551 | #define VSD_FIRMWARE PPC_BIT(2) /* Read warning */ |
| 552 | #define VSD_FIRMWARE2 PPC_BIT(3) /* unused */ |
| 553 | #define VSD_RESERVED PPC_BITMASK(4, 7) /* P10 reserved */ |
| 554 | #define VSD_ADDRESS_MASK 0x00fffffffffff000ull |
| 555 | #define VSD_MIGRATION_REG PPC_BITMASK(52, 55) |
| 556 | #define VSD_INDIRECT PPC_BIT(56) |
| 557 | #define VSD_TSIZE PPC_BITMASK(59, 63) |
| 558 | |
| 559 | #endif /* PPC_PNV_XIVE2_REGS_H */ |