| 1 | /* |
| 2 | * QEMU PowerPC XIVE interrupt controller model |
| 3 | * |
| 4 | * Copyright (c) 2017-2018, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef PPC_PNV_XIVE_REGS_H |
| 11 | #define PPC_PNV_XIVE_REGS_H |
| 12 | |
| 13 | /* IC register offsets 0x0 - 0x400 */ |
| 14 | #define CQ_SWI_CMD_HIST 0x020 |
| 15 | #define CQ_SWI_CMD_POLL 0x028 |
| 16 | #define CQ_SWI_CMD_BCAST 0x030 |
| 17 | #define CQ_SWI_CMD_ASSIGN 0x038 |
| 18 | #define CQ_SWI_CMD_BLK_UPD 0x040 |
| 19 | #define CQ_SWI_RSP 0x048 |
| 20 | #define CQ_CFG_PB_GEN 0x050 |
| 21 | #define CQ_INT_ADDR_OPT PPC_BITMASK(14, 15) |
| 22 | #define CQ_MSGSND 0x058 |
| 23 | #define CQ_CNPM_SEL 0x078 |
| 24 | #define CQ_IC_BAR 0x080 |
| 25 | #define CQ_IC_BAR_VALID PPC_BIT(0) |
| 26 | #define CQ_IC_BAR_64K PPC_BIT(1) |
| 27 | #define CQ_TM1_BAR 0x90 |
| 28 | #define CQ_TM2_BAR 0x0a0 |
| 29 | #define CQ_TM_BAR_VALID PPC_BIT(0) |
| 30 | #define CQ_TM_BAR_64K PPC_BIT(1) |
| 31 | #define CQ_PC_BAR 0x0b0 |
| 32 | #define CQ_PC_BAR_VALID PPC_BIT(0) |
| 33 | #define CQ_PC_BARM 0x0b8 |
| 34 | #define CQ_PC_BARM_MASK PPC_BITMASK(26, 38) |
| 35 | #define CQ_VC_BAR 0x0c0 |
| 36 | #define CQ_VC_BAR_VALID PPC_BIT(0) |
| 37 | #define CQ_VC_BARM 0x0c8 |
| 38 | #define CQ_VC_BARM_MASK PPC_BITMASK(21, 37) |
| 39 | #define CQ_TAR 0x0f0 |
| 40 | #define CQ_TAR_TBL_AUTOINC PPC_BIT(0) |
| 41 | #define CQ_TAR_TSEL PPC_BITMASK(12, 15) |
| 42 | #define CQ_TAR_TSEL_BLK PPC_BIT(12) |
| 43 | #define CQ_TAR_TSEL_MIG PPC_BIT(13) |
| 44 | #define CQ_TAR_TSEL_VDT PPC_BIT(14) |
| 45 | #define CQ_TAR_TSEL_EDT PPC_BIT(15) |
| 46 | #define CQ_TAR_TSEL_INDEX PPC_BITMASK(26, 31) |
| 47 | #define CQ_TDR 0x0f8 |
| 48 | #define CQ_TDR_VDT_VALID PPC_BIT(0) |
| 49 | #define CQ_TDR_VDT_BLK PPC_BITMASK(11, 15) |
| 50 | #define CQ_TDR_VDT_INDEX PPC_BITMASK(28, 31) |
| 51 | #define CQ_TDR_EDT_TYPE PPC_BITMASK(0, 1) |
| 52 | #define CQ_TDR_EDT_INVALID 0 |
| 53 | #define CQ_TDR_EDT_IPI 1 |
| 54 | #define CQ_TDR_EDT_EQ 2 |
| 55 | #define CQ_TDR_EDT_BLK PPC_BITMASK(12, 15) |
| 56 | #define CQ_TDR_EDT_INDEX PPC_BITMASK(26, 31) |
| 57 | #define CQ_PBI_CTL 0x100 |
| 58 | #define CQ_PBI_PC_64K PPC_BIT(5) |
| 59 | #define CQ_PBI_VC_64K PPC_BIT(6) |
| 60 | #define CQ_PBI_LNX_TRIG PPC_BIT(7) |
| 61 | #define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) |
| 62 | #define CQ_PBO_CTL 0x108 |
| 63 | #define CQ_AIB_CTL 0x110 |
| 64 | #define CQ_RST_CTL 0x118 |
| 65 | #define CQ_FIRMASK 0x198 |
| 66 | #define CQ_FIRMASK_AND 0x1a0 |
| 67 | #define CQ_FIRMASK_OR 0x1a8 |
| 68 | |
| 69 | /* PC LBS1 register offsets 0x400 - 0x800 */ |
| 70 | #define PC_TCTXT_CFG 0x400 |
| 71 | #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) |
| 72 | #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) |
| 73 | #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) |
| 74 | #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) |
| 75 | #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) |
| 76 | #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) |
| 77 | #define PC_TCTXT_CHIPID PPC_BITMASK(12, 15) |
| 78 | #define PC_TCTXT_INIT_AGE PPC_BITMASK(30, 31) |
| 79 | #define PC_TCTXT_TRACK 0x408 |
| 80 | #define PC_TCTXT_TRACK_EN PPC_BIT(0) |
| 81 | #define PC_TCTXT_INDIR0 0x420 |
| 82 | #define PC_TCTXT_INDIR_VALID PPC_BIT(0) |
| 83 | #define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9, 15) |
| 84 | #define PC_TCTXT_INDIR1 0x428 |
| 85 | #define PC_TCTXT_INDIR2 0x430 |
| 86 | #define PC_TCTXT_INDIR3 0x438 |
| 87 | #define PC_THREAD_EN_REG0 0x440 |
| 88 | #define PC_THREAD_EN_REG0_SET 0x448 |
| 89 | #define PC_THREAD_EN_REG0_CLR 0x450 |
| 90 | #define PC_THREAD_EN_REG1 0x460 |
| 91 | #define PC_THREAD_EN_REG1_SET 0x468 |
| 92 | #define PC_THREAD_EN_REG1_CLR 0x470 |
| 93 | #define PC_GLOBAL_CONFIG 0x480 |
| 94 | #define PC_GCONF_INDIRECT PPC_BIT(32) |
| 95 | #define PC_GCONF_CHIPID_OVR PPC_BIT(40) |
| 96 | #define PC_GCONF_CHIPID PPC_BITMASK(44, 47) |
| 97 | #define PC_VSD_TABLE_ADDR 0x488 |
| 98 | #define PC_VSD_TABLE_DATA 0x490 |
| 99 | #define PC_AT_KILL 0x4b0 |
| 100 | #define PC_AT_KILL_VALID PPC_BIT(0) |
| 101 | #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27, 31) |
| 102 | #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60) |
| 103 | #define PC_AT_KILL_MASK 0x4b8 |
| 104 | |
| 105 | /* PC LBS2 register offsets */ |
| 106 | #define PC_VPC_CACHE_ENABLE 0x708 |
| 107 | #define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0, 31) |
| 108 | #define PC_VPC_SCRUB_TRIG 0x710 |
| 109 | #define PC_VPC_SCRUB_MASK 0x718 |
| 110 | #define PC_SCRUB_VALID PPC_BIT(0) |
| 111 | #define PC_SCRUB_WANT_DISABLE PPC_BIT(1) |
| 112 | #define PC_SCRUB_WANT_INVAL PPC_BIT(2) |
| 113 | #define PC_SCRUB_BLOCK_ID PPC_BITMASK(27, 31) |
| 114 | #define PC_SCRUB_OFFSET PPC_BITMASK(45, 63) |
| 115 | #define PC_VPC_CWATCH_SPEC 0x738 |
| 116 | #define PC_VPC_CWATCH_CONFLICT PPC_BIT(0) |
| 117 | #define PC_VPC_CWATCH_FULL PPC_BIT(8) |
| 118 | #define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27, 31) |
| 119 | #define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45, 63) |
| 120 | #define PC_VPC_CWATCH_DAT0 0x740 |
| 121 | #define PC_VPC_CWATCH_DAT1 0x748 |
| 122 | #define PC_VPC_CWATCH_DAT2 0x750 |
| 123 | #define PC_VPC_CWATCH_DAT3 0x758 |
| 124 | #define PC_VPC_CWATCH_DAT4 0x760 |
| 125 | #define PC_VPC_CWATCH_DAT5 0x768 |
| 126 | #define PC_VPC_CWATCH_DAT6 0x770 |
| 127 | #define PC_VPC_CWATCH_DAT7 0x778 |
| 128 | |
| 129 | /* VC0 register offsets 0x800 - 0xFFF */ |
| 130 | #define VC_GLOBAL_CONFIG 0x800 |
| 131 | #define VC_GCONF_INDIRECT PPC_BIT(32) |
| 132 | #define VC_VSD_TABLE_ADDR 0x808 |
| 133 | #define VC_VSD_TABLE_DATA 0x810 |
| 134 | #define VC_IVE_ISB_BLOCK_MODE 0x818 |
| 135 | #define VC_EQD_BLOCK_MODE 0x820 |
| 136 | #define VC_VPS_BLOCK_MODE 0x828 |
| 137 | #define VC_IRQ_CONFIG_IPI 0x840 |
| 138 | #define VC_IRQ_CONFIG_MEMB_EN PPC_BIT(45) |
| 139 | #define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46, 51) |
| 140 | #define VC_IRQ_CONFIG_HW 0x848 |
| 141 | #define VC_IRQ_CONFIG_CASCADE1 0x850 |
| 142 | #define VC_IRQ_CONFIG_CASCADE2 0x858 |
| 143 | #define VC_IRQ_CONFIG_REDIST 0x860 |
| 144 | #define VC_IRQ_CONFIG_IPI_CASC 0x868 |
| 145 | #define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) |
| 146 | #define VC_AIB_TX_ORDER_TAG2 0x890 |
| 147 | #define VC_AT_MACRO_KILL 0x8b0 |
| 148 | #define VC_AT_MACRO_KILL_MASK 0x8b8 |
| 149 | #define VC_KILL_VALID PPC_BIT(0) |
| 150 | #define VC_KILL_TYPE PPC_BITMASK(14, 15) |
| 151 | #define VC_KILL_IRQ 0 |
| 152 | #define VC_KILL_IVC 1 |
| 153 | #define VC_KILL_SBC 2 |
| 154 | #define VC_KILL_EQD 3 |
| 155 | #define VC_KILL_BLOCK_ID PPC_BITMASK(27, 31) |
| 156 | #define VC_KILL_OFFSET PPC_BITMASK(48, 60) |
| 157 | #define VC_EQC_CACHE_ENABLE 0x908 |
| 158 | #define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0, 15) |
| 159 | #define VC_EQC_SCRUB_TRIG 0x910 |
| 160 | #define VC_EQC_SCRUB_MASK 0x918 |
| 161 | #define VC_EQC_CONFIG 0x920 |
| 162 | #define X_VC_EQC_CONFIG 0x214 /* XSCOM register */ |
| 163 | #define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) |
| 164 | #define VC_EQC_CONF_SYNC_HW PPC_BIT(33) |
| 165 | #define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) |
| 166 | #define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) |
| 167 | #define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) |
| 168 | #define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) |
| 169 | #define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) |
| 170 | #define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) |
| 171 | #define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) |
| 172 | #define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) |
| 173 | #define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) |
| 174 | #define VC_EQC_CWATCH_SPEC 0x928 |
| 175 | #define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) |
| 176 | #define VC_EQC_CWATCH_FULL PPC_BIT(8) |
| 177 | #define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28, 31) |
| 178 | #define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40, 63) |
| 179 | #define VC_EQC_CWATCH_DAT0 0x930 |
| 180 | #define VC_EQC_CWATCH_DAT1 0x938 |
| 181 | #define VC_EQC_CWATCH_DAT2 0x940 |
| 182 | #define VC_EQC_CWATCH_DAT3 0x948 |
| 183 | #define VC_IVC_SCRUB_TRIG 0x990 |
| 184 | #define VC_IVC_SCRUB_MASK 0x998 |
| 185 | #define VC_SBC_SCRUB_TRIG 0xa10 |
| 186 | #define VC_SBC_SCRUB_MASK 0xa18 |
| 187 | #define VC_SCRUB_VALID PPC_BIT(0) |
| 188 | #define VC_SCRUB_WANT_DISABLE PPC_BIT(1) |
| 189 | #define VC_SCRUB_WANT_INVAL PPC_BIT(2) /* EQC and SBC only */ |
| 190 | #define VC_SCRUB_BLOCK_ID PPC_BITMASK(28, 31) |
| 191 | #define VC_SCRUB_OFFSET PPC_BITMASK(40, 63) |
| 192 | #define VC_IVC_CACHE_ENABLE 0x988 |
| 193 | #define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0, 15) |
| 194 | #define VC_SBC_CACHE_ENABLE 0xa08 |
| 195 | #define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0, 15) |
| 196 | #define VC_IVC_CACHE_SCRUB_TRIG 0x990 |
| 197 | #define VC_IVC_CACHE_SCRUB_MASK 0x998 |
| 198 | #define VC_SBC_CACHE_ENABLE 0xa08 |
| 199 | #define VC_SBC_CACHE_SCRUB_TRIG 0xa10 |
| 200 | #define VC_SBC_CACHE_SCRUB_MASK 0xa18 |
| 201 | #define VC_SBC_CONFIG 0xa20 |
| 202 | #define VC_SBC_CONF_CPLX_CIST PPC_BIT(44) |
| 203 | #define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) |
| 204 | #define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) |
| 205 | |
| 206 | /* VC1 register offsets */ |
| 207 | |
| 208 | /* VSD Table address register definitions (shared) */ |
| 209 | #define VST_ADDR_AUTOINC PPC_BIT(0) |
| 210 | #define VST_TABLE_SELECT PPC_BITMASK(13, 15) |
| 211 | #define VST_TSEL_IVT 0 |
| 212 | #define VST_TSEL_SBE 1 |
| 213 | #define VST_TSEL_EQDT 2 |
| 214 | #define VST_TSEL_VPDT 3 |
| 215 | #define VST_TSEL_IRQ 4 /* VC only */ |
| 216 | #define VST_TABLE_BLOCK PPC_BITMASK(27, 31) |
| 217 | |
| 218 | /* Number of queue overflow pages */ |
| 219 | #define VC_QUEUE_OVF_COUNT 6 |
| 220 | |
| 221 | /* |
| 222 | * Bits in a VSD entry. |
| 223 | * |
| 224 | * Note: the address is naturally aligned, we don't use a PPC_BITMASK, |
| 225 | * but just a mask to apply to the address before OR'ing it in. |
| 226 | * |
| 227 | * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the |
| 228 | * VSD and is only meant to be used in indirect mode ! |
| 229 | */ |
| 230 | #define VSD_MODE PPC_BITMASK(0, 1) |
| 231 | #define VSD_MODE_INVALID 0 |
| 232 | #define VSD_MODE_SHARED 1 |
| 233 | #define VSD_MODE_EXCLUSIVE 2 |
| 234 | #define VSD_MODE_FORWARD 3 |
| 235 | #define VSD_ADDRESS_MASK 0x0ffffffffffff000ull |
| 236 | #define VSD_MIGRATION_REG PPC_BITMASK(52, 55) |
| 237 | #define VSD_INDIRECT PPC_BIT(56) |
| 238 | #define VSD_TSIZE PPC_BITMASK(59, 63) |
| 239 | #define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */ |
| 240 | |
| 241 | #define VC_EQC_SYNC_MASK \ |
| 242 | (VC_EQC_CONF_SYNC_IPI | \ |
| 243 | VC_EQC_CONF_SYNC_HW | \ |
| 244 | VC_EQC_CONF_SYNC_ESC1 | \ |
| 245 | VC_EQC_CONF_SYNC_ESC2 | \ |
| 246 | VC_EQC_CONF_SYNC_REDI) |
| 247 | |
| 248 | |
| 249 | #endif /* PPC_PNV_XIVE_REGS_H */ |