| 1 | /* |
| 2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator |
| 3 | * |
| 4 | * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics |
| 5 | * |
| 6 | * Copyright (c) 2010,2011 David Gibson, IBM Corporation. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "qemu/osdep.h" |
| 29 | #include "qemu/log.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "trace.h" |
| 32 | #include "qemu/timer.h" |
| 33 | #include "hw/ppc/xics.h" |
| 34 | #include "hw/core/qdev-properties.h" |
| 35 | #include "qemu/error-report.h" |
| 36 | #include "qemu/module.h" |
| 37 | #include "qapi/visitor.h" |
| 38 | #include "migration/vmstate.h" |
| 39 | #include "hw/intc/intc.h" |
| 40 | #include "hw/core/irq.h" |
| 41 | #include "system/kvm.h" |
| 42 | #include "system/reset.h" |
| 43 | #include "target/ppc/cpu.h" |
| 44 | |
| 45 | void icp_pic_print_info(ICPState *icp, GString *buf) |
| 46 | { |
| 47 | int cpu_index; |
| 48 | |
| 49 | /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs |
| 50 | * are hot plugged or unplugged. |
| 51 | */ |
| 52 | if (!icp) { |
| 53 | return; |
| 54 | } |
| 55 | |
| 56 | cpu_index = icp->cs ? icp->cs->cpu_index : -1; |
| 57 | |
| 58 | if (!icp->output) { |
| 59 | return; |
| 60 | } |
| 61 | |
| 62 | if (kvm_irqchip_in_kernel()) { |
| 63 | icp_synchronize_state(icp); |
| 64 | } |
| 65 | |
| 66 | g_string_append_printf(buf, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", |
| 67 | cpu_index, icp->xirr, icp->xirr_owner, |
| 68 | icp->pending_priority, icp->mfrr); |
| 69 | } |
| 70 | |
| 71 | void ics_pic_print_info(ICSState *ics, GString *buf) |
| 72 | { |
| 73 | uint32_t i; |
| 74 | |
| 75 | g_string_append_printf(buf, "ICS %4x..%4x %p\n", |
| 76 | ics->offset, ics->offset + ics->nr_irqs - 1, ics); |
| 77 | |
| 78 | if (!ics->irqs) { |
| 79 | return; |
| 80 | } |
| 81 | |
| 82 | if (kvm_irqchip_in_kernel()) { |
| 83 | ics_synchronize_state(ics); |
| 84 | } |
| 85 | |
| 86 | for (i = 0; i < ics->nr_irqs; i++) { |
| 87 | ICSIRQState *irq = ics->irqs + i; |
| 88 | |
| 89 | if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { |
| 90 | continue; |
| 91 | } |
| 92 | g_string_append_printf(buf, " %4x %s %02x %02x\n", |
| 93 | ics->offset + i, |
| 94 | (irq->flags & XICS_FLAGS_IRQ_LSI) ? |
| 95 | "LSI" : "MSI", |
| 96 | irq->priority, irq->status); |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * ICP: Presentation layer |
| 102 | */ |
| 103 | |
| 104 | #define XISR_MASK 0x00ffffff |
| 105 | #define CPPR_MASK 0xff000000 |
| 106 | |
| 107 | #define XISR(icp) (((icp)->xirr) & XISR_MASK) |
| 108 | #define CPPR(icp) (((icp)->xirr) >> 24) |
| 109 | |
| 110 | static void ics_reject(ICSState *ics, uint32_t nr); |
| 111 | static void ics_eoi(ICSState *ics, uint32_t nr); |
| 112 | |
| 113 | static void icp_check_ipi(ICPState *icp) |
| 114 | { |
| 115 | if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) { |
| 116 | return; |
| 117 | } |
| 118 | |
| 119 | trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr); |
| 120 | |
| 121 | if (XISR(icp) && icp->xirr_owner) { |
| 122 | ics_reject(icp->xirr_owner, XISR(icp)); |
| 123 | } |
| 124 | |
| 125 | icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI; |
| 126 | icp->pending_priority = icp->mfrr; |
| 127 | icp->xirr_owner = NULL; |
| 128 | qemu_irq_raise(icp->output); |
| 129 | } |
| 130 | |
| 131 | void icp_resend(ICPState *icp) |
| 132 | { |
| 133 | XICSFabric *xi = icp->xics; |
| 134 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
| 135 | |
| 136 | if (icp->mfrr < CPPR(icp)) { |
| 137 | icp_check_ipi(icp); |
| 138 | } |
| 139 | |
| 140 | xic->ics_resend(xi); |
| 141 | } |
| 142 | |
| 143 | void icp_set_cppr(ICPState *icp, uint8_t cppr) |
| 144 | { |
| 145 | uint8_t old_cppr; |
| 146 | uint32_t old_xisr; |
| 147 | |
| 148 | old_cppr = CPPR(icp); |
| 149 | icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24); |
| 150 | |
| 151 | if (cppr < old_cppr) { |
| 152 | if (XISR(icp) && (cppr <= icp->pending_priority)) { |
| 153 | old_xisr = XISR(icp); |
| 154 | icp->xirr &= ~XISR_MASK; /* Clear XISR */ |
| 155 | icp->pending_priority = 0xff; |
| 156 | qemu_irq_lower(icp->output); |
| 157 | if (icp->xirr_owner) { |
| 158 | ics_reject(icp->xirr_owner, old_xisr); |
| 159 | icp->xirr_owner = NULL; |
| 160 | } |
| 161 | } |
| 162 | } else { |
| 163 | if (!XISR(icp)) { |
| 164 | icp_resend(icp); |
| 165 | } |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | void icp_set_mfrr(ICPState *icp, uint8_t mfrr) |
| 170 | { |
| 171 | icp->mfrr = mfrr; |
| 172 | if (mfrr < CPPR(icp)) { |
| 173 | icp_check_ipi(icp); |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | uint32_t icp_accept(ICPState *icp) |
| 178 | { |
| 179 | uint32_t xirr = icp->xirr; |
| 180 | |
| 181 | qemu_irq_lower(icp->output); |
| 182 | icp->xirr = icp->pending_priority << 24; |
| 183 | icp->pending_priority = 0xff; |
| 184 | icp->xirr_owner = NULL; |
| 185 | |
| 186 | trace_xics_icp_accept(xirr, icp->xirr); |
| 187 | |
| 188 | return xirr; |
| 189 | } |
| 190 | |
| 191 | uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr) |
| 192 | { |
| 193 | if (mfrr) { |
| 194 | *mfrr = icp->mfrr; |
| 195 | } |
| 196 | return icp->xirr; |
| 197 | } |
| 198 | |
| 199 | void icp_eoi(ICPState *icp, uint32_t xirr) |
| 200 | { |
| 201 | XICSFabric *xi = icp->xics; |
| 202 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
| 203 | ICSState *ics; |
| 204 | uint32_t irq; |
| 205 | |
| 206 | /* Send EOI -> ICS */ |
| 207 | icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); |
| 208 | trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); |
| 209 | irq = xirr & XISR_MASK; |
| 210 | |
| 211 | ics = xic->ics_get(xi, irq); |
| 212 | if (ics) { |
| 213 | ics_eoi(ics, irq); |
| 214 | } |
| 215 | if (!XISR(icp)) { |
| 216 | icp_resend(icp); |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) |
| 221 | { |
| 222 | ICPState *icp = xics_icp_get(ics->xics, server); |
| 223 | |
| 224 | trace_xics_icp_irq(server, nr, priority); |
| 225 | |
| 226 | if (!icp) { |
| 227 | qemu_log_mask(LOG_GUEST_ERROR, "XICS: invalid server %d for IRQ 0x%x\n", |
| 228 | server, nr); |
| 229 | ics_reject(ics, nr); |
| 230 | return; |
| 231 | } |
| 232 | |
| 233 | if ((priority >= CPPR(icp)) |
| 234 | || (XISR(icp) && (icp->pending_priority <= priority))) { |
| 235 | ics_reject(ics, nr); |
| 236 | } else { |
| 237 | if (XISR(icp) && icp->xirr_owner) { |
| 238 | ics_reject(icp->xirr_owner, XISR(icp)); |
| 239 | icp->xirr_owner = NULL; |
| 240 | } |
| 241 | icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK); |
| 242 | icp->xirr_owner = ics; |
| 243 | icp->pending_priority = priority; |
| 244 | trace_xics_icp_raise(icp->xirr, icp->pending_priority); |
| 245 | qemu_irq_raise(icp->output); |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | static int icp_pre_save(void *opaque) |
| 250 | { |
| 251 | ICPState *icp = opaque; |
| 252 | |
| 253 | if (kvm_irqchip_in_kernel()) { |
| 254 | icp_get_kvm_state(icp); |
| 255 | } |
| 256 | |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | static int icp_post_load(void *opaque, int version_id) |
| 261 | { |
| 262 | ICPState *icp = opaque; |
| 263 | |
| 264 | if (kvm_irqchip_in_kernel()) { |
| 265 | Error *local_err = NULL; |
| 266 | int ret; |
| 267 | |
| 268 | ret = icp_set_kvm_state(icp, &local_err); |
| 269 | if (ret < 0) { |
| 270 | error_report_err(local_err); |
| 271 | return ret; |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | static const VMStateDescription vmstate_icp_server = { |
| 279 | .name = "icp/server", |
| 280 | .version_id = 1, |
| 281 | .minimum_version_id = 1, |
| 282 | .pre_save = icp_pre_save, |
| 283 | .post_load = icp_post_load, |
| 284 | .fields = (const VMStateField[]) { |
| 285 | /* Sanity check */ |
| 286 | VMSTATE_UINT32(xirr, ICPState), |
| 287 | VMSTATE_UINT8(pending_priority, ICPState), |
| 288 | VMSTATE_UINT8(mfrr, ICPState), |
| 289 | VMSTATE_END_OF_LIST() |
| 290 | }, |
| 291 | }; |
| 292 | |
| 293 | void icp_reset(ICPState *icp) |
| 294 | { |
| 295 | icp->xirr = 0; |
| 296 | icp->pending_priority = 0xff; |
| 297 | icp->mfrr = 0xff; |
| 298 | |
| 299 | if (kvm_irqchip_in_kernel()) { |
| 300 | Error *local_err = NULL; |
| 301 | |
| 302 | icp_set_kvm_state(icp, &local_err); |
| 303 | if (local_err) { |
| 304 | error_report_err(local_err); |
| 305 | } |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | static void icp_realize(DeviceState *dev, Error **errp) |
| 310 | { |
| 311 | ICPState *icp = ICP(dev); |
| 312 | PowerPCCPU *cpu; |
| 313 | CPUPPCState *env; |
| 314 | Error *err = NULL; |
| 315 | |
| 316 | assert(icp->xics); |
| 317 | assert(icp->cs); |
| 318 | |
| 319 | cpu = POWERPC_CPU(icp->cs); |
| 320 | env = &cpu->env; |
| 321 | switch (PPC_INPUT(env)) { |
| 322 | case PPC_FLAGS_INPUT_POWER7: |
| 323 | icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER7_INPUT_INT); |
| 324 | break; |
| 325 | case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */ |
| 326 | icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT); |
| 327 | break; |
| 328 | |
| 329 | case PPC_FLAGS_INPUT_970: |
| 330 | icp->output = qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT); |
| 331 | break; |
| 332 | |
| 333 | default: |
| 334 | error_setg(errp, "XICS interrupt controller does not support this CPU bus model"); |
| 335 | return; |
| 336 | } |
| 337 | |
| 338 | /* Connect the presenter to the VCPU (required for CPU hotplug) */ |
| 339 | if (kvm_irqchip_in_kernel()) { |
| 340 | icp_kvm_realize(dev, &err); |
| 341 | if (err) { |
| 342 | error_propagate(errp, err); |
| 343 | return; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); |
| 348 | } |
| 349 | |
| 350 | static void icp_unrealize(DeviceState *dev) |
| 351 | { |
| 352 | ICPState *icp = ICP(dev); |
| 353 | |
| 354 | vmstate_unregister(NULL, &vmstate_icp_server, icp); |
| 355 | } |
| 356 | |
| 357 | static const Property icp_properties[] = { |
| 358 | DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC, |
| 359 | XICSFabric *), |
| 360 | DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *), |
| 361 | }; |
| 362 | |
| 363 | static void icp_class_init(ObjectClass *klass, const void *data) |
| 364 | { |
| 365 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 366 | |
| 367 | dc->realize = icp_realize; |
| 368 | dc->unrealize = icp_unrealize; |
| 369 | device_class_set_props(dc, icp_properties); |
| 370 | /* |
| 371 | * Reason: part of XICS interrupt controller, needs to be wired up |
| 372 | * by icp_create(). |
| 373 | */ |
| 374 | dc->user_creatable = false; |
| 375 | } |
| 376 | |
| 377 | static const TypeInfo icp_info = { |
| 378 | .name = TYPE_ICP, |
| 379 | .parent = TYPE_DEVICE, |
| 380 | .instance_size = sizeof(ICPState), |
| 381 | .class_init = icp_class_init, |
| 382 | .class_size = sizeof(ICPStateClass), |
| 383 | }; |
| 384 | |
| 385 | Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) |
| 386 | { |
| 387 | Object *obj; |
| 388 | |
| 389 | obj = object_new(type); |
| 390 | object_property_add_child(cpu, type, obj); |
| 391 | object_unref(obj); |
| 392 | object_property_set_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort); |
| 393 | object_property_set_link(obj, ICP_PROP_CPU, cpu, &error_abort); |
| 394 | if (!qdev_realize(DEVICE(obj), NULL, errp)) { |
| 395 | object_unparent(obj); |
| 396 | obj = NULL; |
| 397 | } |
| 398 | |
| 399 | return obj; |
| 400 | } |
| 401 | |
| 402 | void icp_destroy(ICPState *icp) |
| 403 | { |
| 404 | Object *obj = OBJECT(icp); |
| 405 | |
| 406 | object_unparent(obj); |
| 407 | } |
| 408 | |
| 409 | /* |
| 410 | * ICS: Source layer |
| 411 | */ |
| 412 | static void ics_resend_msi(ICSState *ics, int srcno) |
| 413 | { |
| 414 | ICSIRQState *irq = ics->irqs + srcno; |
| 415 | |
| 416 | /* FIXME: filter by server#? */ |
| 417 | if (irq->status & XICS_STATUS_REJECTED) { |
| 418 | irq->status &= ~XICS_STATUS_REJECTED; |
| 419 | if (irq->priority != 0xff) { |
| 420 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
| 421 | } |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | static void ics_resend_lsi(ICSState *ics, int srcno) |
| 426 | { |
| 427 | ICSIRQState *irq = ics->irqs + srcno; |
| 428 | |
| 429 | if ((irq->priority != 0xff) |
| 430 | && (irq->status & XICS_STATUS_ASSERTED) |
| 431 | && !(irq->status & XICS_STATUS_SENT)) { |
| 432 | irq->status |= XICS_STATUS_SENT; |
| 433 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | static void ics_set_irq_msi(ICSState *ics, int srcno, int val) |
| 438 | { |
| 439 | ICSIRQState *irq = ics->irqs + srcno; |
| 440 | |
| 441 | trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset); |
| 442 | |
| 443 | if (val) { |
| 444 | if (irq->priority == 0xff) { |
| 445 | irq->status |= XICS_STATUS_MASKED_PENDING; |
| 446 | trace_xics_masked_pending(); |
| 447 | } else { |
| 448 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
| 449 | } |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | static void ics_set_irq_lsi(ICSState *ics, int srcno, int val) |
| 454 | { |
| 455 | ICSIRQState *irq = ics->irqs + srcno; |
| 456 | |
| 457 | trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset); |
| 458 | if (val) { |
| 459 | irq->status |= XICS_STATUS_ASSERTED; |
| 460 | } else { |
| 461 | irq->status &= ~XICS_STATUS_ASSERTED; |
| 462 | } |
| 463 | ics_resend_lsi(ics, srcno); |
| 464 | } |
| 465 | |
| 466 | void ics_set_irq(void *opaque, int srcno, int val) |
| 467 | { |
| 468 | ICSState *ics = (ICSState *)opaque; |
| 469 | |
| 470 | if (kvm_irqchip_in_kernel()) { |
| 471 | ics_kvm_set_irq(ics, srcno, val); |
| 472 | return; |
| 473 | } |
| 474 | |
| 475 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
| 476 | ics_set_irq_lsi(ics, srcno, val); |
| 477 | } else { |
| 478 | ics_set_irq_msi(ics, srcno, val); |
| 479 | } |
| 480 | } |
| 481 | |
| 482 | static void ics_write_xive_msi(ICSState *ics, int srcno) |
| 483 | { |
| 484 | ICSIRQState *irq = ics->irqs + srcno; |
| 485 | |
| 486 | if (!(irq->status & XICS_STATUS_MASKED_PENDING) |
| 487 | || (irq->priority == 0xff)) { |
| 488 | return; |
| 489 | } |
| 490 | |
| 491 | irq->status &= ~XICS_STATUS_MASKED_PENDING; |
| 492 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
| 493 | } |
| 494 | |
| 495 | static void ics_write_xive_lsi(ICSState *ics, int srcno) |
| 496 | { |
| 497 | ics_resend_lsi(ics, srcno); |
| 498 | } |
| 499 | |
| 500 | void ics_write_xive(ICSState *ics, int srcno, int server, |
| 501 | uint8_t priority, uint8_t saved_priority) |
| 502 | { |
| 503 | ICSIRQState *irq = ics->irqs + srcno; |
| 504 | |
| 505 | irq->server = server; |
| 506 | irq->priority = priority; |
| 507 | irq->saved_priority = saved_priority; |
| 508 | |
| 509 | trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority); |
| 510 | |
| 511 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
| 512 | ics_write_xive_lsi(ics, srcno); |
| 513 | } else { |
| 514 | ics_write_xive_msi(ics, srcno); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | static void ics_reject(ICSState *ics, uint32_t nr) |
| 519 | { |
| 520 | ICSStateClass *isc = ICS_GET_CLASS(ics); |
| 521 | ICSIRQState *irq = ics->irqs + nr - ics->offset; |
| 522 | |
| 523 | if (isc->reject) { |
| 524 | isc->reject(ics, nr); |
| 525 | return; |
| 526 | } |
| 527 | |
| 528 | trace_xics_ics_reject(nr, nr - ics->offset); |
| 529 | if (irq->flags & XICS_FLAGS_IRQ_MSI) { |
| 530 | irq->status |= XICS_STATUS_REJECTED; |
| 531 | } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { |
| 532 | irq->status &= ~XICS_STATUS_SENT; |
| 533 | } |
| 534 | } |
| 535 | |
| 536 | void ics_resend(ICSState *ics) |
| 537 | { |
| 538 | ICSStateClass *isc = ICS_GET_CLASS(ics); |
| 539 | int i; |
| 540 | |
| 541 | if (isc->resend) { |
| 542 | isc->resend(ics); |
| 543 | return; |
| 544 | } |
| 545 | |
| 546 | for (i = 0; i < ics->nr_irqs; i++) { |
| 547 | /* FIXME: filter by server#? */ |
| 548 | if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { |
| 549 | ics_resend_lsi(ics, i); |
| 550 | } else { |
| 551 | ics_resend_msi(ics, i); |
| 552 | } |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | static void ics_eoi(ICSState *ics, uint32_t nr) |
| 557 | { |
| 558 | int srcno = nr - ics->offset; |
| 559 | ICSIRQState *irq = ics->irqs + srcno; |
| 560 | |
| 561 | trace_xics_ics_eoi(nr); |
| 562 | |
| 563 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
| 564 | irq->status &= ~XICS_STATUS_SENT; |
| 565 | } |
| 566 | } |
| 567 | |
| 568 | static void ics_reset_irq(ICSIRQState *irq) |
| 569 | { |
| 570 | irq->priority = 0xff; |
| 571 | irq->saved_priority = 0xff; |
| 572 | } |
| 573 | |
| 574 | static void ics_reset_hold(Object *obj, ResetType type) |
| 575 | { |
| 576 | ICSState *ics = ICS(obj); |
| 577 | g_autofree uint8_t *flags = g_malloc(ics->nr_irqs); |
| 578 | int i; |
| 579 | |
| 580 | for (i = 0; i < ics->nr_irqs; i++) { |
| 581 | flags[i] = ics->irqs[i].flags; |
| 582 | } |
| 583 | |
| 584 | memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); |
| 585 | |
| 586 | for (i = 0; i < ics->nr_irqs; i++) { |
| 587 | ics_reset_irq(ics->irqs + i); |
| 588 | ics->irqs[i].flags = flags[i]; |
| 589 | } |
| 590 | |
| 591 | if (kvm_irqchip_in_kernel()) { |
| 592 | Error *local_err = NULL; |
| 593 | |
| 594 | ics_set_kvm_state(ics, &local_err); |
| 595 | if (local_err) { |
| 596 | error_report_err(local_err); |
| 597 | } |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | static void ics_reset_handler(void *dev) |
| 602 | { |
| 603 | device_cold_reset(dev); |
| 604 | } |
| 605 | |
| 606 | static void ics_realize(DeviceState *dev, Error **errp) |
| 607 | { |
| 608 | ICSState *ics = ICS(dev); |
| 609 | |
| 610 | assert(ics->xics); |
| 611 | |
| 612 | if (!ics->nr_irqs) { |
| 613 | error_setg(errp, "Number of interrupts needs to be greater 0"); |
| 614 | return; |
| 615 | } |
| 616 | ics->irqs = g_new0(ICSIRQState, ics->nr_irqs); |
| 617 | |
| 618 | qemu_register_reset(ics_reset_handler, ics); |
| 619 | } |
| 620 | |
| 621 | static void ics_instance_init(Object *obj) |
| 622 | { |
| 623 | ICSState *ics = ICS(obj); |
| 624 | |
| 625 | ics->offset = XICS_IRQ_BASE; |
| 626 | } |
| 627 | |
| 628 | static int ics_pre_save(void *opaque) |
| 629 | { |
| 630 | ICSState *ics = opaque; |
| 631 | |
| 632 | if (kvm_irqchip_in_kernel()) { |
| 633 | ics_get_kvm_state(ics); |
| 634 | } |
| 635 | |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | static int ics_post_load(void *opaque, int version_id) |
| 640 | { |
| 641 | ICSState *ics = opaque; |
| 642 | |
| 643 | if (kvm_irqchip_in_kernel()) { |
| 644 | Error *local_err = NULL; |
| 645 | int ret; |
| 646 | |
| 647 | ret = ics_set_kvm_state(ics, &local_err); |
| 648 | if (ret < 0) { |
| 649 | error_report_err(local_err); |
| 650 | return ret; |
| 651 | } |
| 652 | } |
| 653 | |
| 654 | return 0; |
| 655 | } |
| 656 | |
| 657 | static const VMStateDescription vmstate_ics_irq = { |
| 658 | .name = "ics/irq", |
| 659 | .version_id = 2, |
| 660 | .minimum_version_id = 1, |
| 661 | .fields = (const VMStateField[]) { |
| 662 | VMSTATE_UINT32(server, ICSIRQState), |
| 663 | VMSTATE_UINT8(priority, ICSIRQState), |
| 664 | VMSTATE_UINT8(saved_priority, ICSIRQState), |
| 665 | VMSTATE_UINT8(status, ICSIRQState), |
| 666 | VMSTATE_UINT8(flags, ICSIRQState), |
| 667 | VMSTATE_END_OF_LIST() |
| 668 | }, |
| 669 | }; |
| 670 | |
| 671 | static const VMStateDescription vmstate_ics = { |
| 672 | .name = "ics", |
| 673 | .version_id = 1, |
| 674 | .minimum_version_id = 1, |
| 675 | .pre_save = ics_pre_save, |
| 676 | .post_load = ics_post_load, |
| 677 | .fields = (const VMStateField[]) { |
| 678 | /* Sanity check */ |
| 679 | VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), |
| 680 | |
| 681 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, |
| 682 | vmstate_ics_irq, |
| 683 | ICSIRQState), |
| 684 | VMSTATE_END_OF_LIST() |
| 685 | }, |
| 686 | }; |
| 687 | |
| 688 | static const Property ics_properties[] = { |
| 689 | DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), |
| 690 | DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC, |
| 691 | XICSFabric *), |
| 692 | }; |
| 693 | |
| 694 | static void ics_class_init(ObjectClass *klass, const void *data) |
| 695 | { |
| 696 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 697 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 698 | |
| 699 | dc->realize = ics_realize; |
| 700 | device_class_set_props(dc, ics_properties); |
| 701 | dc->vmsd = &vmstate_ics; |
| 702 | /* |
| 703 | * Reason: part of XICS interrupt controller, needs to be wired up, |
| 704 | * e.g. by spapr_irq_init(). |
| 705 | */ |
| 706 | dc->user_creatable = false; |
| 707 | rc->phases.hold = ics_reset_hold; |
| 708 | } |
| 709 | |
| 710 | static const TypeInfo ics_info = { |
| 711 | .name = TYPE_ICS, |
| 712 | .parent = TYPE_DEVICE, |
| 713 | .instance_size = sizeof(ICSState), |
| 714 | .instance_init = ics_instance_init, |
| 715 | .class_init = ics_class_init, |
| 716 | .class_size = sizeof(ICSStateClass), |
| 717 | }; |
| 718 | |
| 719 | static const TypeInfo xics_fabric_info = { |
| 720 | .name = TYPE_XICS_FABRIC, |
| 721 | .parent = TYPE_INTERFACE, |
| 722 | .class_size = sizeof(XICSFabricClass), |
| 723 | }; |
| 724 | |
| 725 | /* |
| 726 | * Exported functions |
| 727 | */ |
| 728 | ICPState *xics_icp_get(XICSFabric *xi, int server) |
| 729 | { |
| 730 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
| 731 | |
| 732 | return xic->icp_get(xi, server); |
| 733 | } |
| 734 | |
| 735 | void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) |
| 736 | { |
| 737 | assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); |
| 738 | |
| 739 | ics->irqs[srcno].flags |= |
| 740 | lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; |
| 741 | |
| 742 | if (kvm_irqchip_in_kernel()) { |
| 743 | Error *local_err = NULL; |
| 744 | |
| 745 | ics_reset_irq(ics->irqs + srcno); |
| 746 | ics_set_kvm_state_one(ics, srcno, &local_err); |
| 747 | if (local_err) { |
| 748 | error_report_err(local_err); |
| 749 | } |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | static void xics_register_types(void) |
| 754 | { |
| 755 | type_register_static(&ics_info); |
| 756 | type_register_static(&icp_info); |
| 757 | type_register_static(&xics_fabric_info); |
| 758 | } |
| 759 | |
| 760 | type_init(xics_register_types) |