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1 /*
2 * QEMU PowerPC XIVE interrupt controller model
3 *
4 * Copyright (c) 2017-2018, IBM Corporation.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "qemu/module.h"
12 #include "qapi/error.h"
13 #include "target/ppc/cpu.h"
14 #include "system/cpus.h"
15 #include "system/dma.h"
16 #include "system/reset.h"
17 #include "hw/core/qdev-properties.h"
18 #include "migration/vmstate.h"
19 #include "hw/core/irq.h"
20 #include "hw/ppc/xive.h"
21 #include "hw/ppc/xive2.h"
22 #include "hw/ppc/xive_regs.h"
23 #include "trace.h"
24
25 /*
26 * XIVE Thread Interrupt Management context
27 */
28 bool xive_ring_valid(XiveTCTX *tctx, uint8_t ring)
29 {
30 uint8_t cur_ring;
31
32 for (cur_ring = ring; cur_ring <= TM_QW3_HV_PHYS;
33 cur_ring += XIVE_TM_RING_SIZE) {
34 if (!(tctx->regs[cur_ring + TM_WORD2] & 0x80)) {
35 return false;
36 }
37 }
38 return true;
39 }
40
41 bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr)
42 {
43 switch (ring) {
44 case TM_QW1_OS:
45 return !!(nsr & TM_QW1_NSR_EO);
46 case TM_QW2_HV_POOL:
47 case TM_QW3_HV_PHYS:
48 return !!(nsr & TM_QW3_NSR_HE);
49 default:
50 g_assert_not_reached();
51 }
52 }
53
54 bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr)
55 {
56 if ((nsr & TM_NSR_GRP_LVL) > 0) {
57 g_assert(xive_nsr_indicates_exception(ring, nsr));
58 return true;
59 }
60 return false;
61 }
62
63 uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr)
64 {
65 /* NSR determines if pool/phys ring is for phys or pool interrupt */
66 if ((ring == TM_QW3_HV_PHYS) || (ring == TM_QW2_HV_POOL)) {
67 uint8_t he = (nsr & TM_QW3_NSR_HE) >> 6;
68
69 if (he == TM_QW3_NSR_HE_PHYS) {
70 return TM_QW3_HV_PHYS;
71 } else if (he == TM_QW3_NSR_HE_POOL) {
72 return TM_QW2_HV_POOL;
73 } else {
74 /* Don't support LSI mode */
75 g_assert_not_reached();
76 }
77 }
78 return ring;
79 }
80
81 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring)
82 {
83 switch (ring) {
84 case TM_QW0_USER:
85 return 0; /* Not supported */
86 case TM_QW1_OS:
87 return tctx->os_output;
88 case TM_QW2_HV_POOL:
89 case TM_QW3_HV_PHYS:
90 return tctx->hv_output;
91 default:
92 return 0;
93 }
94 }
95
96 /*
97 * interrupt is accepted on the presentation ring, for PHYS ring the NSR
98 * directs it to the PHYS or POOL rings.
99 */
100 uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring)
101 {
102 uint8_t *sig_regs = &tctx->regs[sig_ring];
103 uint8_t nsr = sig_regs[TM_NSR];
104
105 g_assert(sig_ring == TM_QW1_OS || sig_ring == TM_QW3_HV_PHYS);
106
107 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0);
108 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0);
109 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0);
110
111 if (xive_nsr_indicates_exception(sig_ring, nsr)) {
112 uint8_t cppr = sig_regs[TM_PIPR];
113 uint8_t ring;
114 uint8_t *regs;
115
116 ring = xive_nsr_exception_ring(sig_ring, nsr);
117 regs = &tctx->regs[ring];
118
119 sig_regs[TM_CPPR] = cppr;
120
121 /*
122 * If the interrupt was for a specific VP, reset the pending
123 * buffer bit, otherwise clear the logical server indicator
124 */
125 if (!xive_nsr_indicates_group_exception(sig_ring, nsr)) {
126 regs[TM_IPB] &= ~xive_priority_to_ipb(cppr);
127 }
128
129 /* Clear the exception from NSR */
130 sig_regs[TM_NSR] = 0;
131 qemu_irq_lower(xive_tctx_output(tctx, sig_ring));
132
133 trace_xive_tctx_accept(tctx->cs->cpu_index, ring,
134 regs[TM_IPB], sig_regs[TM_PIPR],
135 sig_regs[TM_CPPR], sig_regs[TM_NSR]);
136 }
137
138 return ((uint64_t)nsr << 8) | sig_regs[TM_CPPR];
139 }
140
141 /* Change PIPR and calculate NSR and irq based on PIPR, CPPR, group */
142 void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t pipr,
143 uint8_t group_level)
144 {
145 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
146 uint8_t *regs = &tctx->regs[ring];
147
148 g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR]));
149
150 sig_regs[TM_PIPR] = pipr;
151
152 if (pipr < sig_regs[TM_CPPR]) {
153 switch (ring) {
154 case TM_QW1_OS:
155 sig_regs[TM_NSR] = TM_QW1_NSR_EO | (group_level & 0x3F);
156 break;
157 case TM_QW2_HV_POOL:
158 sig_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6) | (group_level & 0x3F);
159 break;
160 case TM_QW3_HV_PHYS:
161 sig_regs[TM_NSR] = (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x3F);
162 break;
163 default:
164 g_assert_not_reached();
165 }
166 trace_xive_tctx_notify(tctx->cs->cpu_index, ring,
167 regs[TM_IPB], pipr,
168 sig_regs[TM_CPPR], sig_regs[TM_NSR]);
169 qemu_irq_raise(xive_tctx_output(tctx, ring));
170 } else {
171 sig_regs[TM_NSR] = 0;
172 qemu_irq_lower(xive_tctx_output(tctx, ring));
173 }
174 }
175
176 void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring)
177 {
178 /*
179 * Lower the External interrupt. Used when pulling a context. It is
180 * necessary to avoid catching it in the higher privilege context. It
181 * should be raised again when re-pushing the lower privilege context.
182 */
183 qemu_irq_lower(xive_tctx_output(tctx, ring));
184 }
185
186 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
187 {
188 uint8_t *sig_regs = &tctx->regs[ring];
189 uint8_t pipr_min;
190 uint8_t ring_min;
191
192 g_assert(ring == TM_QW1_OS || ring == TM_QW3_HV_PHYS);
193
194 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0);
195 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0);
196 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0);
197
198 /* XXX: should show pool IPB for PHYS ring */
199 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring,
200 sig_regs[TM_IPB], sig_regs[TM_PIPR],
201 cppr, sig_regs[TM_NSR]);
202
203 if (cppr > XIVE_PRIORITY_MAX) {
204 cppr = 0xff;
205 }
206
207 sig_regs[TM_CPPR] = cppr;
208
209 /*
210 * Recompute the PIPR based on local pending interrupts. The PHYS
211 * ring must take the minimum of both the PHYS and POOL PIPR values.
212 */
213 pipr_min = xive_ipb_to_pipr(sig_regs[TM_IPB]);
214 ring_min = ring;
215
216 /* PHYS updates also depend on POOL values */
217 if (ring == TM_QW3_HV_PHYS) {
218 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL];
219
220 /* POOL values only matter if POOL ctx is valid */
221 if (pool_regs[TM_WORD2] & 0x80) {
222 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]);
223
224 /*
225 * Determine highest priority interrupt and
226 * remember which ring has it.
227 */
228 if (pool_pipr < pipr_min) {
229 pipr_min = pool_pipr;
230 ring_min = TM_QW2_HV_POOL;
231 }
232 }
233 }
234
235 /* CPPR has changed, this may present or preclude a pending exception */
236 xive_tctx_pipr_set(tctx, ring_min, pipr_min, 0);
237 }
238
239 static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring)
240 {
241 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
242 uint8_t *regs = &tctx->regs[ring];
243
244 /* Does not support a presented group interrupt */
245 g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR]));
246
247 xive_tctx_pipr_set(tctx, ring, xive_ipb_to_pipr(regs[TM_IPB]), 0);
248 }
249
250 void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
251 uint8_t group_level)
252 {
253 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
254 uint8_t *regs = &tctx->regs[ring];
255 uint8_t pipr = xive_priority_to_pipr(priority);
256
257 if (group_level == 0) {
258 regs[TM_IPB] |= xive_priority_to_ipb(priority);
259 if (pipr >= sig_regs[TM_PIPR]) {
260 /* VP interrupts can come here with lower priority than PIPR */
261 return;
262 }
263 }
264 g_assert(pipr <= xive_ipb_to_pipr(regs[TM_IPB]));
265 g_assert(pipr < sig_regs[TM_PIPR]);
266 xive_tctx_pipr_set(tctx, ring, pipr, group_level);
267 }
268
269 /*
270 * XIVE Thread Interrupt Management Area (TIMA)
271 */
272
273 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
274 hwaddr offset, uint64_t value, unsigned size)
275 {
276 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
277 }
278
279 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,
280 hwaddr offset, unsigned size)
281 {
282 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
283 }
284
285 static void xive_pool_cam_decode(uint32_t cam, uint8_t *nvt_blk,
286 uint32_t *nvt_idx, bool *vp)
287 {
288 if (nvt_blk) {
289 *nvt_blk = xive_nvt_blk(cam);
290 }
291 if (nvt_idx) {
292 *nvt_idx = xive_nvt_idx(cam);
293 }
294 if (vp) {
295 *vp = !!(cam & TM_QW2W2_VP);
296 }
297 }
298
299 static uint32_t xive_tctx_get_pool_cam(XiveTCTX *tctx, uint8_t *nvt_blk,
300 uint32_t *nvt_idx, bool *vp)
301 {
302 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
303 uint32_t cam = be32_to_cpu(qw2w2);
304
305 xive_pool_cam_decode(cam, nvt_blk, nvt_idx, vp);
306 return qw2w2;
307 }
308
309 static void xive_tctx_set_pool_cam(XiveTCTX *tctx, uint32_t qw2w2)
310 {
311 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4);
312 }
313
314 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
315 hwaddr offset, unsigned size)
316 {
317 uint32_t qw2w2;
318 uint32_t qw2w2_new;
319 uint8_t nvt_blk;
320 uint32_t nvt_idx;
321 bool vp;
322
323 qw2w2 = xive_tctx_get_pool_cam(tctx, &nvt_blk, &nvt_idx, &vp);
324
325 if (!vp) {
326 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pull invalid POOL NVT %x/%x !?\n",
327 nvt_blk, nvt_idx);
328 }
329
330 /* Invalidate CAM line */
331 qw2w2_new = xive_set_field32(TM_QW2W2_VP, qw2w2, 0);
332 xive_tctx_set_pool_cam(tctx, qw2w2_new);
333
334 xive_tctx_reset_signal(tctx, TM_QW1_OS);
335 xive_tctx_reset_signal(tctx, TM_QW2_HV_POOL);
336 /* Re-check phys for interrupts if pool was disabled */
337 xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW3_HV_PHYS);
338
339 return qw2w2;
340 }
341
342 static uint64_t xive_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx,
343 hwaddr offset, unsigned size)
344 {
345 uint8_t qw3b8 = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2];
346 uint8_t qw3b8_new;
347
348 qw3b8 = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2];
349 if (!(qw3b8 & TM_QW3B8_VT)) {
350 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid PHYS thread!?\n");
351 }
352 qw3b8_new = qw3b8 & ~TM_QW3B8_VT;
353 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8_new;
354
355 xive_tctx_reset_signal(tctx, TM_QW1_OS);
356 xive_tctx_reset_signal(tctx, TM_QW3_HV_PHYS);
357 return qw3b8;
358 }
359
360 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
361 uint64_t value, unsigned size)
362 {
363 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
364 }
365
366 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,
367 hwaddr offset, unsigned size)
368 {
369 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
370 }
371
372 /*
373 * Define an access map for each page of the TIMA that we will use in
374 * the memory region ops to filter values when doing loads and stores
375 * of raw registers values
376 *
377 * Registers accessibility bits :
378 *
379 * 0x0 - no access
380 * 0x1 - write only
381 * 0x2 - read only
382 * 0x3 - read/write
383 */
384
385 static const uint8_t xive_tm_hw_view[] = {
386 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
387 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */
388 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
389 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
390 };
391
392 static const uint8_t xive_tm_hv_view[] = {
393 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
394 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */
395 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
396 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
397 };
398
399 static const uint8_t xive_tm_os_view[] = {
400 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
401 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
402 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
404 };
405
406 static const uint8_t xive_tm_user_view[] = {
407 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
409 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
410 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
411 };
412
413 /*
414 * Overall TIMA access map for the thread interrupt management context
415 * registers
416 */
417 static const uint8_t *xive_tm_views[] = {
418 [XIVE_TM_HW_PAGE] = xive_tm_hw_view,
419 [XIVE_TM_HV_PAGE] = xive_tm_hv_view,
420 [XIVE_TM_OS_PAGE] = xive_tm_os_view,
421 [XIVE_TM_USER_PAGE] = xive_tm_user_view,
422 };
423
424 /*
425 * Computes a register access mask for a given offset in the TIMA
426 */
427 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write)
428 {
429 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3;
430 uint8_t reg_offset = offset & TM_REG_OFFSET;
431 uint8_t reg_mask = write ? 0x1 : 0x2;
432 uint64_t mask = 0x0;
433 int i;
434
435 for (i = 0; i < size; i++) {
436 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) {
437 mask |= (uint64_t) 0xff << (8 * (size - i - 1));
438 }
439 }
440
441 return mask;
442 }
443
444 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
445 unsigned size)
446 {
447 uint8_t ring_offset = offset & TM_RING_OFFSET;
448 uint8_t reg_offset = offset & TM_REG_OFFSET;
449 uint64_t mask = xive_tm_mask(offset, size, true);
450 int i;
451
452 /*
453 * Only 4 or 8 bytes stores are allowed and the User ring is
454 * excluded
455 */
456 if (size < 4 || !mask || ring_offset == TM_QW0_USER) {
457 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%"
458 HWADDR_PRIx" size %d\n", offset, size);
459 return;
460 }
461
462 /*
463 * Use the register offset for the raw values and filter out
464 * reserved values
465 */
466 for (i = 0; i < size; i++) {
467 uint8_t byte_mask = (mask >> (8 * (size - i - 1)));
468 if (byte_mask) {
469 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) &
470 byte_mask;
471 }
472 }
473 }
474
475 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
476 {
477 uint8_t ring_offset = offset & TM_RING_OFFSET;
478 uint8_t reg_offset = offset & TM_REG_OFFSET;
479 uint64_t mask = xive_tm_mask(offset, size, false);
480 uint64_t ret;
481 int i;
482
483 /*
484 * Only 4 or 8 bytes loads are allowed and the User ring is
485 * excluded
486 */
487 if (size < 4 || !mask || ring_offset == TM_QW0_USER) {
488 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%"
489 HWADDR_PRIx" size %d\n", offset, size);
490 return -1;
491 }
492
493 /* Use the register offset for the raw values */
494 ret = 0;
495 for (i = 0; i < size; i++) {
496 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1));
497 }
498
499 /* filter out reserved values */
500 return ret & mask;
501 }
502
503 /*
504 * The TM context is mapped twice within each page. Stores and loads
505 * to the first mapping below 2K write and read the specified values
506 * without modification. The second mapping above 2K performs specific
507 * state changes (side effects) in addition to setting/returning the
508 * interrupt management area context of the processor thread.
509 */
510 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,
511 hwaddr offset, unsigned size)
512 {
513 return xive_tctx_accept(tctx, TM_QW1_OS);
514 }
515
516 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
517 hwaddr offset, uint64_t value, unsigned size)
518 {
519 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
520 }
521
522 static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs)
523 {
524 uint8_t *regs = &tctx->regs[ring];
525
526 regs[TM_LGS] = lgs;
527 }
528
529 static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx,
530 hwaddr offset, uint64_t value, unsigned size)
531 {
532 xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff);
533 }
534
535 static void xive_tm_set_pool_lgs(XivePresenter *xptr, XiveTCTX *tctx,
536 hwaddr offset, uint64_t value, unsigned size)
537 {
538 xive_tctx_set_lgs(tctx, TM_QW2_HV_POOL, value & 0xff);
539 }
540
541 /*
542 * Adjust the PIPR to allow a CPU to process event queues of other
543 * priorities during one physical interrupt cycle.
544 */
545 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
546 hwaddr offset, uint64_t value, unsigned size)
547 {
548 uint8_t ring = TM_QW1_OS;
549 uint8_t *regs = &tctx->regs[ring];
550
551 /* XXX: how should this work exactly? */
552 regs[TM_IPB] |= xive_priority_to_ipb(value & 0xff);
553 xive_tctx_pipr_recompute_from_ipb(tctx, ring);
554 }
555
556 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
557 uint32_t *nvt_idx, bool *vo)
558 {
559 if (nvt_blk) {
560 *nvt_blk = xive_nvt_blk(cam);
561 }
562 if (nvt_idx) {
563 *nvt_idx = xive_nvt_idx(cam);
564 }
565 if (vo) {
566 *vo = !!(cam & TM_QW1W2_VO);
567 }
568 }
569
570 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk,
571 uint32_t *nvt_idx, bool *vo)
572 {
573 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
574 uint32_t cam = be32_to_cpu(qw1w2);
575
576 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo);
577 return qw1w2;
578 }
579
580 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
581 {
582 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
583 }
584
585 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
586 hwaddr offset, unsigned size)
587 {
588 uint32_t qw1w2;
589 uint32_t qw1w2_new;
590 uint8_t nvt_blk;
591 uint32_t nvt_idx;
592 bool vo;
593
594 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
595
596 if (!vo) {
597 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pull invalid OS NVT %x/%x !?\n",
598 nvt_blk, nvt_idx);
599 }
600
601 /* Invalidate CAM line */
602 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
603 xive_tctx_set_os_cam(tctx, qw1w2_new);
604
605 xive_tctx_reset_signal(tctx, TM_QW1_OS);
606 return qw1w2;
607 }
608
609 static void xive_tctx_restore_nvp(XiveRouter *xrtr, XiveTCTX *tctx,
610 uint8_t nvt_blk, uint32_t nvt_idx)
611 {
612 XiveNVT nvt;
613 uint8_t ipb;
614
615 /*
616 * Grab the associated NVT to pull the pending bits, and merge
617 * them with the IPB of the thread interrupt context registers
618 */
619 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
620 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n",
621 nvt_blk, nvt_idx);
622 return;
623 }
624
625 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4);
626
627 if (ipb) {
628 /* Reset the NVT value */
629 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
630 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
631
632 uint8_t *regs = &tctx->regs[TM_QW1_OS];
633 regs[TM_IPB] |= ipb;
634 }
635 }
636
637 /*
638 * Updating the OS CAM line can trigger a resend of interrupt
639 */
640 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
641 hwaddr offset, uint64_t value, unsigned size)
642 {
643 uint32_t cam = value;
644 uint32_t qw1w2 = cpu_to_be32(cam);
645 uint8_t nvt_blk;
646 uint32_t nvt_idx;
647 bool vo;
648
649 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
650
651 /* First update the registers */
652 xive_tctx_set_os_cam(tctx, qw1w2);
653
654 /* Check the interrupt pending bits */
655 if (vo) {
656 xive_tctx_restore_nvp(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
657
658 /*
659 * Always call xive_tctx_recompute_from_ipb(). Even if there were no
660 * escalation triggered, there could be a pending interrupt which
661 * was saved when the context was pulled and that we need to take
662 * into account by recalculating the PIPR (which is not
663 * saved/restored).
664 * It will also raise the External interrupt signal if needed.
665 */
666 xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */
667 }
668 }
669
670 static uint32_t xive_presenter_get_config(XivePresenter *xptr)
671 {
672 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
673
674 return xpc->get_config(xptr);
675 }
676
677 /*
678 * Define a mapping of "special" operations depending on the TIMA page
679 * offset and the size of the operation.
680 */
681 typedef struct XiveTmOp {
682 uint8_t page_offset;
683 uint32_t op_offset;
684 unsigned size;
685 bool hw_ok;
686 bool sw_ok;
687 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
688 hwaddr offset,
689 uint64_t value, unsigned size);
690 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
691 unsigned size);
692 } XiveTmOp;
693
694 static const XiveTmOp xive_tm_operations[] = {
695 /*
696 * MMIOs below 2K : raw values and special operations without side
697 * effects
698 */
699 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true,
700 xive_tm_set_os_cppr, NULL },
701 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, true, true,
702 xive_tm_push_os_ctx, NULL },
703 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true,
704 xive_tm_set_hv_cppr, NULL },
705 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, false, true,
706 xive_tm_vt_push, NULL },
707 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true,
708 NULL, xive_tm_vt_poll },
709
710 /* MMIOs above 2K : special operations with side effects */
711 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false,
712 NULL, xive_tm_ack_os_reg },
713 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, true, false,
714 xive_tm_set_os_pending, NULL },
715 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false,
716 NULL, xive_tm_pull_os_ctx },
717 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, true, false,
718 NULL, xive_tm_pull_os_ctx },
719 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, true, false,
720 NULL, xive_tm_ack_hv_reg },
721 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, true, false,
722 NULL, xive_tm_pull_pool_ctx },
723 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, true, false,
724 NULL, xive_tm_pull_pool_ctx },
725 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, true, false,
726 NULL, xive_tm_pull_phys_ctx },
727 };
728
729 static const XiveTmOp xive2_tm_operations[] = {
730 /*
731 * MMIOs below 2K : raw values and special operations without side
732 * effects
733 */
734 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true,
735 xive2_tm_set_os_cppr, NULL },
736 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, true, true,
737 xive2_tm_push_os_ctx, NULL },
738 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, true, true,
739 xive2_tm_push_os_ctx, NULL },
740 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, true, true,
741 xive_tm_set_os_lgs, NULL },
742 { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_WORD2, 4, true, true,
743 xive2_tm_push_pool_ctx, NULL },
744 { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_WORD2, 8, true, true,
745 xive2_tm_push_pool_ctx, NULL },
746 { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_LGS, 1, true, true,
747 xive_tm_set_pool_lgs, NULL },
748 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true,
749 xive2_tm_set_hv_cppr, NULL },
750 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, false, true,
751 xive2_tm_push_phys_ctx, NULL },
752 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true,
753 NULL, xive_tm_vt_poll },
754 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, true, true,
755 xive2_tm_set_hv_target, NULL },
756
757 /* MMIOs above 2K : special operations with side effects */
758 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false,
759 NULL, xive_tm_ack_os_reg },
760 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, true, false,
761 xive2_tm_set_os_pending, NULL },
762 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, true, false,
763 NULL, xive2_tm_pull_os_ctx },
764 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false,
765 NULL, xive2_tm_pull_os_ctx },
766 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, true, false,
767 NULL, xive2_tm_pull_os_ctx },
768 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, true, false,
769 NULL, xive_tm_ack_hv_reg },
770 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, true, false,
771 NULL, xive2_tm_pull_pool_ctx },
772 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, true, false,
773 NULL, xive2_tm_pull_pool_ctx },
774 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, true, false,
775 NULL, xive2_tm_pull_pool_ctx },
776 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, true, false,
777 xive2_tm_pull_os_ctx_ol, NULL },
778 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, true, false,
779 NULL, xive2_tm_pull_phys_ctx },
780 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, true, false,
781 NULL, xive2_tm_pull_phys_ctx },
782 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, true, false,
783 xive2_tm_pull_phys_ctx_ol, NULL },
784 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, true, false,
785 xive2_tm_ack_os_el, NULL },
786 };
787
788 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset,
789 unsigned size, bool write)
790 {
791 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3;
792 uint32_t op_offset = offset & TM_ADDRESS_MASK;
793 const XiveTmOp *tm_ops;
794 int i, tm_ops_count;
795 uint32_t cfg;
796
797 cfg = xive_presenter_get_config(xptr);
798 if (cfg & XIVE_PRESENTER_GEN1_TIMA_OS) {
799 tm_ops = xive_tm_operations;
800 tm_ops_count = ARRAY_SIZE(xive_tm_operations);
801 } else {
802 tm_ops = xive2_tm_operations;
803 tm_ops_count = ARRAY_SIZE(xive2_tm_operations);
804 }
805
806 for (i = 0; i < tm_ops_count; i++) {
807 const XiveTmOp *xto = &tm_ops[i];
808
809 /* Accesses done from a more privileged TIMA page is allowed */
810 if (xto->page_offset >= page_offset &&
811 xto->op_offset == op_offset &&
812 xto->size == size &&
813 ((write && xto->write_handler) || (!write && xto->read_handler))) {
814 return xto;
815 }
816 }
817 return NULL;
818 }
819
820 /*
821 * TIMA MMIO handlers
822 */
823 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
824 uint64_t value, unsigned size)
825 {
826 const XiveTmOp *xto;
827 uint8_t ring = offset & TM_RING_OFFSET;
828 bool is_valid = xive_ring_valid(tctx, ring);
829 bool hw_owned = is_valid;
830
831 trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);
832
833 /*
834 * First, check for special operations in the 2K region
835 */
836 xto = xive_tm_find_op(tctx->xptr, offset, size, true);
837 if (xto) {
838 if (hw_owned && !xto->hw_ok) {
839 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to HW TIMA "
840 "@%"HWADDR_PRIx" size %d\n", offset, size);
841 }
842 if (!hw_owned && !xto->sw_ok) {
843 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to SW TIMA "
844 "@%"HWADDR_PRIx" size %d\n", offset, size);
845 }
846 }
847
848 if (offset & TM_SPECIAL_OP) {
849 if (!xto) {
850 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA "
851 "@%"HWADDR_PRIx" size %d\n", offset, size);
852 } else {
853 xto->write_handler(xptr, tctx, offset, value, size);
854 }
855 return;
856 }
857
858 /*
859 * Then, for special operations in the region below 2K.
860 */
861 if (xto) {
862 xto->write_handler(xptr, tctx, offset, value, size);
863 return;
864 }
865
866 /*
867 * Finish with raw access to the register values
868 */
869 if (hw_owned) {
870 /* Store context operations are dangerous when context is valid */
871 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to HW TIMA "
872 "@%"HWADDR_PRIx" size %d\n", offset, size);
873 }
874 xive_tm_raw_write(tctx, offset, value, size);
875 }
876
877 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
878 unsigned size)
879 {
880 const XiveTmOp *xto;
881 uint8_t ring = offset & TM_RING_OFFSET;
882 bool is_valid = xive_ring_valid(tctx, ring);
883 bool hw_owned = is_valid;
884 uint64_t ret;
885
886 xto = xive_tm_find_op(tctx->xptr, offset, size, false);
887 if (xto) {
888 if (hw_owned && !xto->hw_ok) {
889 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined read to HW TIMA "
890 "@%"HWADDR_PRIx" size %d\n", offset, size);
891 }
892 if (!hw_owned && !xto->sw_ok) {
893 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined read to SW TIMA "
894 "@%"HWADDR_PRIx" size %d\n", offset, size);
895 }
896 }
897
898 /*
899 * First, check for special operations in the 2K region
900 */
901 if (offset & TM_SPECIAL_OP) {
902 if (!xto) {
903 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA"
904 "@%"HWADDR_PRIx" size %d\n", offset, size);
905 return -1;
906 }
907 ret = xto->read_handler(xptr, tctx, offset, size);
908 goto out;
909 }
910
911 /*
912 * Then, for special operations in the region below 2K.
913 */
914 if (xto) {
915 ret = xto->read_handler(xptr, tctx, offset, size);
916 goto out;
917 }
918
919 /*
920 * Finish with raw access to the register values
921 */
922 ret = xive_tm_raw_read(tctx, offset, size);
923 out:
924 trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret);
925 return ret;
926 }
927
928 static char *xive_tctx_ring_print(uint8_t *ring)
929 {
930 uint32_t w2 = xive_tctx_word2(ring);
931
932 return g_strdup_printf("%02x %02x %02x %02x %02x "
933 "%02x %02x %02x %08x",
934 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB],
935 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR],
936 be32_to_cpu(w2));
937 }
938
939 static const char * const xive_tctx_ring_names[] = {
940 "USER", "OS", "POOL", "PHYS",
941 };
942
943 /*
944 * kvm_irqchip_in_kernel() will cause the compiler to turn this
945 * info a nop if CONFIG_KVM isn't defined.
946 */
947 #define xive_in_kernel(xptr) \
948 (kvm_irqchip_in_kernel() && \
949 ({ \
950 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \
951 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \
952 }))
953
954 void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf)
955 {
956 int cpu_index;
957 int i;
958
959 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
960 * are hot plugged or unplugged.
961 */
962 if (!tctx) {
963 return;
964 }
965
966 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1;
967
968 if (xive_in_kernel(tctx->xptr)) {
969 Error *local_err = NULL;
970
971 kvmppc_xive_cpu_synchronize_state(tctx, &local_err);
972 if (local_err) {
973 error_report_err(local_err);
974 return;
975 }
976 }
977
978 if (xive_presenter_get_config(tctx->xptr) & XIVE_PRESENTER_GEN1_TIMA_OS) {
979 g_string_append_printf(buf, "CPU[%04x]: "
980 "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
981 " W2\n", cpu_index);
982 } else {
983 g_string_append_printf(buf, "CPU[%04x]: "
984 "QW NSR CPPR IPB LSMFB - LGS T PIPR"
985 " W2\n", cpu_index);
986 }
987
988 for (i = 0; i < XIVE_TM_RING_COUNT; i++) {
989 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]);
990 g_string_append_printf(buf, "CPU[%04x]: %4s %s\n",
991 cpu_index, xive_tctx_ring_names[i], s);
992 g_free(s);
993 }
994 }
995
996 void xive_tctx_reset(XiveTCTX *tctx)
997 {
998 memset(tctx->regs, 0, sizeof(tctx->regs));
999
1000 /* Set some defaults */
1001 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF;
1002 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF;
1003 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF;
1004 if (!(xive_presenter_get_config(tctx->xptr) &
1005 XIVE_PRESENTER_GEN1_TIMA_OS)) {
1006 tctx->regs[TM_QW1_OS + TM_OGEN] = 2;
1007 }
1008
1009 /*
1010 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
1011 * CPPR is first set.
1012 */
1013 tctx->regs[TM_QW1_OS + TM_PIPR] =
1014 xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
1015 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =
1016 xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
1017 }
1018
1019 static void xive_tctx_realize(DeviceState *dev, Error **errp)
1020 {
1021 XiveTCTX *tctx = XIVE_TCTX(dev);
1022 PowerPCCPU *cpu;
1023 CPUPPCState *env;
1024
1025 assert(tctx->cs);
1026 assert(tctx->xptr);
1027
1028 cpu = POWERPC_CPU(tctx->cs);
1029 env = &cpu->env;
1030 switch (PPC_INPUT(env)) {
1031 case PPC_FLAGS_INPUT_POWER9:
1032 tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT);
1033 tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT);
1034 break;
1035
1036 default:
1037 error_setg(errp, "XIVE interrupt controller does not support "
1038 "this CPU bus model");
1039 return;
1040 }
1041
1042 /* Connect the presenter to the VCPU (required for CPU hotplug) */
1043 if (xive_in_kernel(tctx->xptr)) {
1044 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) {
1045 return;
1046 }
1047 }
1048 }
1049
1050 static int vmstate_xive_tctx_pre_save(void *opaque)
1051 {
1052 XiveTCTX *tctx = XIVE_TCTX(opaque);
1053 Error *local_err = NULL;
1054 int ret;
1055
1056 if (xive_in_kernel(tctx->xptr)) {
1057 ret = kvmppc_xive_cpu_get_state(tctx, &local_err);
1058 if (ret < 0) {
1059 error_report_err(local_err);
1060 return ret;
1061 }
1062 }
1063
1064 return 0;
1065 }
1066
1067 static int vmstate_xive_tctx_post_load(void *opaque, int version_id)
1068 {
1069 XiveTCTX *tctx = XIVE_TCTX(opaque);
1070 Error *local_err = NULL;
1071 int ret;
1072
1073 if (xive_in_kernel(tctx->xptr)) {
1074 /*
1075 * Required for hotplugged CPU, for which the state comes
1076 * after all states of the machine.
1077 */
1078 ret = kvmppc_xive_cpu_set_state(tctx, &local_err);
1079 if (ret < 0) {
1080 error_report_err(local_err);
1081 return ret;
1082 }
1083 } else {
1084 uint8_t pipr = tctx->regs[TM_QW1_OS + TM_PIPR];
1085 xive_tctx_pipr_set(tctx, TM_QW1_OS, pipr, 0);
1086 }
1087
1088 return 0;
1089 }
1090
1091 static const VMStateDescription vmstate_xive_tctx = {
1092 .name = TYPE_XIVE_TCTX,
1093 .version_id = 1,
1094 .minimum_version_id = 1,
1095 .pre_save = vmstate_xive_tctx_pre_save,
1096 .post_load = vmstate_xive_tctx_post_load,
1097 .fields = (const VMStateField[]) {
1098 VMSTATE_BUFFER(regs, XiveTCTX),
1099 VMSTATE_END_OF_LIST()
1100 },
1101 };
1102
1103 static const Property xive_tctx_properties[] = {
1104 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *),
1105 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER,
1106 XivePresenter *),
1107 };
1108
1109 static void xive_tctx_class_init(ObjectClass *klass, const void *data)
1110 {
1111 DeviceClass *dc = DEVICE_CLASS(klass);
1112
1113 dc->desc = "XIVE Interrupt Thread Context";
1114 dc->realize = xive_tctx_realize;
1115 dc->vmsd = &vmstate_xive_tctx;
1116 device_class_set_props(dc, xive_tctx_properties);
1117 /*
1118 * Reason: part of XIVE interrupt controller, needs to be wired up
1119 * by xive_tctx_create().
1120 */
1121 dc->user_creatable = false;
1122 }
1123
1124 static const TypeInfo xive_tctx_info = {
1125 .name = TYPE_XIVE_TCTX,
1126 .parent = TYPE_DEVICE,
1127 .instance_size = sizeof(XiveTCTX),
1128 .class_init = xive_tctx_class_init,
1129 };
1130
1131 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp)
1132 {
1133 Object *obj;
1134
1135 obj = object_new(TYPE_XIVE_TCTX);
1136 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj);
1137 object_unref(obj);
1138 object_property_set_link(obj, "cpu", cpu, &error_abort);
1139 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort);
1140 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
1141 object_unparent(obj);
1142 return NULL;
1143 }
1144 return obj;
1145 }
1146
1147 void xive_tctx_destroy(XiveTCTX *tctx)
1148 {
1149 Object *obj = OBJECT(tctx);
1150
1151 object_unparent(obj);
1152 }
1153
1154 /*
1155 * XIVE ESB helpers
1156 */
1157
1158 uint8_t xive_esb_set(uint8_t *pq, uint8_t value)
1159 {
1160 uint8_t old_pq = *pq & 0x3;
1161
1162 *pq &= ~0x3;
1163 *pq |= value & 0x3;
1164
1165 return old_pq;
1166 }
1167
1168 bool xive_esb_trigger(uint8_t *pq)
1169 {
1170 uint8_t old_pq = *pq & 0x3;
1171
1172 switch (old_pq) {
1173 case XIVE_ESB_RESET:
1174 xive_esb_set(pq, XIVE_ESB_PENDING);
1175 return true;
1176 case XIVE_ESB_PENDING:
1177 case XIVE_ESB_QUEUED:
1178 xive_esb_set(pq, XIVE_ESB_QUEUED);
1179 return false;
1180 case XIVE_ESB_OFF:
1181 xive_esb_set(pq, XIVE_ESB_OFF);
1182 return false;
1183 default:
1184 g_assert_not_reached();
1185 }
1186 }
1187
1188 bool xive_esb_eoi(uint8_t *pq)
1189 {
1190 uint8_t old_pq = *pq & 0x3;
1191
1192 switch (old_pq) {
1193 case XIVE_ESB_RESET:
1194 case XIVE_ESB_PENDING:
1195 xive_esb_set(pq, XIVE_ESB_RESET);
1196 return false;
1197 case XIVE_ESB_QUEUED:
1198 xive_esb_set(pq, XIVE_ESB_PENDING);
1199 return true;
1200 case XIVE_ESB_OFF:
1201 xive_esb_set(pq, XIVE_ESB_OFF);
1202 return false;
1203 default:
1204 g_assert_not_reached();
1205 }
1206 }
1207
1208 /*
1209 * XIVE Interrupt Source (or IVSE)
1210 */
1211
1212 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno)
1213 {
1214 assert(srcno < xsrc->nr_irqs);
1215
1216 return xsrc->status[srcno] & 0x3;
1217 }
1218
1219 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq)
1220 {
1221 assert(srcno < xsrc->nr_irqs);
1222
1223 return xive_esb_set(&xsrc->status[srcno], pq);
1224 }
1225
1226 /*
1227 * Returns whether the event notification should be forwarded.
1228 */
1229 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno)
1230 {
1231 uint8_t old_pq = xive_source_esb_get(xsrc, srcno);
1232
1233 xive_source_set_asserted(xsrc, srcno, true);
1234
1235 switch (old_pq) {
1236 case XIVE_ESB_RESET:
1237 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING);
1238 return true;
1239 default:
1240 return false;
1241 }
1242 }
1243
1244 /*
1245 * Sources can be configured with PQ offloading in which case the check
1246 * on the PQ state bits of MSIs is disabled
1247 */
1248 static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno)
1249 {
1250 return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) &&
1251 !xive_source_irq_is_lsi(xsrc, srcno);
1252 }
1253
1254 /*
1255 * Returns whether the event notification should be forwarded.
1256 */
1257 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno)
1258 {
1259 bool ret;
1260
1261 assert(srcno < xsrc->nr_irqs);
1262
1263 if (xive_source_esb_disabled(xsrc, srcno)) {
1264 return true;
1265 }
1266
1267 ret = xive_esb_trigger(&xsrc->status[srcno]);
1268
1269 if (xive_source_irq_is_lsi(xsrc, srcno) &&
1270 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) {
1271 qemu_log_mask(LOG_GUEST_ERROR,
1272 "XIVE: queued an event on LSI IRQ %d\n", srcno);
1273 }
1274
1275 return ret;
1276 }
1277
1278 /*
1279 * Returns whether the event notification should be forwarded.
1280 */
1281 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno)
1282 {
1283 bool ret;
1284
1285 assert(srcno < xsrc->nr_irqs);
1286
1287 if (xive_source_esb_disabled(xsrc, srcno)) {
1288 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno);
1289 return false;
1290 }
1291
1292 ret = xive_esb_eoi(&xsrc->status[srcno]);
1293
1294 /*
1295 * LSI sources do not set the Q bit but they can still be
1296 * asserted, in which case we should forward a new event
1297 * notification
1298 */
1299 if (xive_source_irq_is_lsi(xsrc, srcno) &&
1300 xive_source_is_asserted(xsrc, srcno)) {
1301 ret = xive_source_lsi_trigger(xsrc, srcno);
1302 }
1303
1304 return ret;
1305 }
1306
1307 /*
1308 * Forward the source event notification to the Router
1309 */
1310 static void xive_source_notify(XiveSource *xsrc, int srcno)
1311 {
1312 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive);
1313 bool pq_checked = !xive_source_esb_disabled(xsrc, srcno);
1314
1315 if (xnc->notify) {
1316 xnc->notify(xsrc->xive, srcno, pq_checked);
1317 }
1318 }
1319
1320 /*
1321 * In a two pages ESB MMIO setting, even page is the trigger page, odd
1322 * page is for management
1323 */
1324 static inline bool addr_is_even(hwaddr addr, uint32_t shift)
1325 {
1326 return !((addr >> shift) & 1);
1327 }
1328
1329 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr)
1330 {
1331 return xive_source_esb_has_2page(xsrc) &&
1332 addr_is_even(addr, xsrc->esb_shift - 1);
1333 }
1334
1335 /*
1336 * ESB MMIO loads
1337 * Trigger page Management/EOI page
1338 *
1339 * ESB MMIO setting 2 pages 1 or 2 pages
1340 *
1341 * 0x000 .. 0x3FF -1 EOI and return 0|1
1342 * 0x400 .. 0x7FF -1 EOI and return 0|1
1343 * 0x800 .. 0xBFF -1 return PQ
1344 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
1345 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
1346 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
1347 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
1348 */
1349 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size)
1350 {
1351 XiveSource *xsrc = XIVE_SOURCE(opaque);
1352 uint32_t offset = addr & 0xFFF;
1353 uint32_t srcno = addr >> xsrc->esb_shift;
1354 uint64_t ret = -1;
1355
1356 /* In a two pages ESB MMIO setting, trigger page should not be read */
1357 if (xive_source_is_trigger_page(xsrc, addr)) {
1358 qemu_log_mask(LOG_GUEST_ERROR,
1359 "XIVE: invalid load on IRQ %d trigger page at "
1360 "0x%"HWADDR_PRIx"\n", srcno, addr);
1361 return -1;
1362 }
1363
1364 switch (offset) {
1365 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
1366 ret = xive_source_esb_eoi(xsrc, srcno);
1367
1368 /* Forward the source event notification for routing */
1369 if (ret) {
1370 trace_xive_source_notify(srcno);
1371 xive_source_notify(xsrc, srcno);
1372 }
1373 break;
1374
1375 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
1376 ret = xive_source_esb_get(xsrc, srcno);
1377 break;
1378
1379 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
1380 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
1381 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
1382 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
1383 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3);
1384 break;
1385 default:
1386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n",
1387 offset);
1388 }
1389
1390 trace_xive_source_esb_read(addr, srcno, ret);
1391
1392 return ret;
1393 }
1394
1395 /*
1396 * ESB MMIO stores
1397 * Trigger page Management/EOI page
1398 *
1399 * ESB MMIO setting 2 pages 1 or 2 pages
1400 *
1401 * 0x000 .. 0x3FF Trigger Trigger
1402 * 0x400 .. 0x7FF Trigger EOI
1403 * 0x800 .. 0xBFF Trigger undefined
1404 * 0xC00 .. 0xCFF Trigger PQ=00
1405 * 0xD00 .. 0xDFF Trigger PQ=01
1406 * 0xE00 .. 0xDFF Trigger PQ=10
1407 * 0xF00 .. 0xDFF Trigger PQ=11
1408 */
1409 static void xive_source_esb_write(void *opaque, hwaddr addr,
1410 uint64_t value, unsigned size)
1411 {
1412 XiveSource *xsrc = XIVE_SOURCE(opaque);
1413 uint32_t offset = addr & 0xFFF;
1414 uint32_t srcno = addr >> xsrc->esb_shift;
1415 bool notify = false;
1416
1417 trace_xive_source_esb_write(addr, srcno, value);
1418
1419 /* In a two pages ESB MMIO setting, trigger page only triggers */
1420 if (xive_source_is_trigger_page(xsrc, addr)) {
1421 notify = xive_source_esb_trigger(xsrc, srcno);
1422 goto out;
1423 }
1424
1425 switch (offset) {
1426 case 0 ... 0x3FF:
1427 notify = xive_source_esb_trigger(xsrc, srcno);
1428 break;
1429
1430 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF:
1431 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) {
1432 qemu_log_mask(LOG_GUEST_ERROR,
1433 "XIVE: invalid Store EOI for IRQ %d\n", srcno);
1434 return;
1435 }
1436
1437 notify = xive_source_esb_eoi(xsrc, srcno);
1438 break;
1439
1440 /*
1441 * This is an internal offset used to inject triggers when the PQ
1442 * state bits are not controlled locally. Such as for LSIs when
1443 * under ABT mode.
1444 */
1445 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
1446 notify = true;
1447 break;
1448
1449 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
1450 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
1451 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
1452 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
1453 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3);
1454 break;
1455
1456 default:
1457 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n",
1458 offset);
1459 return;
1460 }
1461
1462 out:
1463 /* Forward the source event notification for routing */
1464 if (notify) {
1465 xive_source_notify(xsrc, srcno);
1466 } else {
1467 trace_xive_source_blocked(srcno);
1468 }
1469 }
1470
1471 static const MemoryRegionOps xive_source_esb_ops = {
1472 .read = xive_source_esb_read,
1473 .write = xive_source_esb_write,
1474 .endianness = DEVICE_BIG_ENDIAN,
1475 .valid = {
1476 .min_access_size = 1,
1477 .max_access_size = 8,
1478 },
1479 .impl = {
1480 .min_access_size = 1,
1481 .max_access_size = 8,
1482 },
1483 };
1484
1485 void xive_source_set_irq(void *opaque, int srcno, int val)
1486 {
1487 XiveSource *xsrc = XIVE_SOURCE(opaque);
1488 bool notify = false;
1489
1490 if (xive_source_irq_is_lsi(xsrc, srcno)) {
1491 if (val) {
1492 notify = xive_source_lsi_trigger(xsrc, srcno);
1493 } else {
1494 xive_source_set_asserted(xsrc, srcno, false);
1495 }
1496 } else {
1497 if (val) {
1498 notify = xive_source_esb_trigger(xsrc, srcno);
1499 }
1500 }
1501
1502 /* Forward the source event notification for routing */
1503 if (notify) {
1504 xive_source_notify(xsrc, srcno);
1505 }
1506 }
1507
1508 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, GString *buf)
1509 {
1510 for (unsigned i = 0; i < xsrc->nr_irqs; i++) {
1511 uint8_t pq = xive_source_esb_get(xsrc, i);
1512
1513 if (pq == XIVE_ESB_OFF) {
1514 continue;
1515 }
1516
1517 g_string_append_printf(buf, " %08x %s %c%c%c\n", i + offset,
1518 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
1519 pq & XIVE_ESB_VAL_P ? 'P' : '-',
1520 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
1521 xive_source_is_asserted(xsrc, i) ? 'A' : ' ');
1522 }
1523 }
1524
1525 static void xive_source_reset(void *dev)
1526 {
1527 XiveSource *xsrc = XIVE_SOURCE(dev);
1528
1529 /* Do not clear the LSI bitmap */
1530
1531 memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs);
1532 }
1533
1534 static void xive_source_realize(DeviceState *dev, Error **errp)
1535 {
1536 XiveSource *xsrc = XIVE_SOURCE(dev);
1537 uint64_t esb_len = xive_source_esb_len(xsrc);
1538
1539 assert(xsrc->xive);
1540
1541 if (!xsrc->nr_irqs) {
1542 error_setg(errp, "Number of interrupt needs to be greater than 0");
1543 return;
1544 }
1545
1546 if (xsrc->esb_shift != XIVE_ESB_4K &&
1547 xsrc->esb_shift != XIVE_ESB_4K_2PAGE &&
1548 xsrc->esb_shift != XIVE_ESB_64K &&
1549 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) {
1550 error_setg(errp, "Invalid ESB shift setting");
1551 return;
1552 }
1553
1554 xsrc->status = g_malloc0(xsrc->nr_irqs);
1555 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs);
1556
1557 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len);
1558 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc),
1559 &xive_source_esb_ops, xsrc, "xive.esb-emulated",
1560 esb_len);
1561 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated);
1562
1563 qemu_register_reset(xive_source_reset, dev);
1564 }
1565
1566 static const VMStateDescription vmstate_xive_source = {
1567 .name = TYPE_XIVE_SOURCE,
1568 .version_id = 1,
1569 .minimum_version_id = 1,
1570 .fields = (const VMStateField[]) {
1571 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource),
1572 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs),
1573 VMSTATE_END_OF_LIST()
1574 },
1575 };
1576
1577 /*
1578 * The default XIVE interrupt source setting for the ESB MMIOs is two
1579 * 64k pages without Store EOI, to be in sync with KVM.
1580 */
1581 static const Property xive_source_properties[] = {
1582 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0),
1583 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0),
1584 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE),
1585 /*
1586 * By default, PQs are initialized to 0b01 (Q=1) which corresponds
1587 * to "ints off"
1588 */
1589 DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF),
1590 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER,
1591 XiveNotifier *),
1592 };
1593
1594 static void xive_source_class_init(ObjectClass *klass, const void *data)
1595 {
1596 DeviceClass *dc = DEVICE_CLASS(klass);
1597
1598 dc->desc = "XIVE Interrupt Source";
1599 device_class_set_props(dc, xive_source_properties);
1600 dc->realize = xive_source_realize;
1601 dc->vmsd = &vmstate_xive_source;
1602 /*
1603 * Reason: part of XIVE interrupt controller, needs to be wired up,
1604 * e.g. by spapr_xive_instance_init().
1605 */
1606 dc->user_creatable = false;
1607 }
1608
1609 static const TypeInfo xive_source_info = {
1610 .name = TYPE_XIVE_SOURCE,
1611 .parent = TYPE_DEVICE,
1612 .instance_size = sizeof(XiveSource),
1613 .class_init = xive_source_class_init,
1614 };
1615
1616 /*
1617 * XiveEND helpers
1618 */
1619
1620 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf)
1621 {
1622 uint64_t qaddr_base = xive_end_qaddr(end);
1623 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
1624 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
1625 uint32_t qentries = 1 << (qsize + 10);
1626 int i;
1627
1628 /*
1629 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1630 */
1631 g_string_append_printf(buf, " [ ");
1632 qindex = (qindex - (width - 1)) & (qentries - 1);
1633 for (i = 0; i < width; i++) {
1634 uint64_t qaddr = qaddr_base + (qindex << 2);
1635 uint32_t qdata = -1;
1636
1637 if (dma_memory_read(&address_space_memory, qaddr,
1638 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) {
1639 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%"
1640 HWADDR_PRIx "\n", qaddr);
1641 return;
1642 }
1643 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "",
1644 be32_to_cpu(qdata));
1645 qindex = (qindex + 1) & (qentries - 1);
1646 }
1647 g_string_append_c(buf, ']');
1648 }
1649
1650 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf)
1651 {
1652 uint64_t qaddr_base = xive_end_qaddr(end);
1653 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
1654 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1);
1655 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
1656 uint32_t qentries = 1 << (qsize + 10);
1657
1658 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6);
1659 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6);
1660 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7);
1661 uint8_t pq;
1662
1663 if (!xive_end_is_valid(end)) {
1664 return;
1665 }
1666
1667 pq = xive_get_field32(END_W1_ESn, end->w1);
1668
1669 g_string_append_printf(buf,
1670 " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
1671 end_idx,
1672 pq & XIVE_ESB_VAL_P ? 'P' : '-',
1673 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
1674 xive_end_is_valid(end) ? 'v' : '-',
1675 xive_end_is_enqueue(end) ? 'q' : '-',
1676 xive_end_is_notify(end) ? 'n' : '-',
1677 xive_end_is_backlog(end) ? 'b' : '-',
1678 xive_end_is_escalate(end) ? 'e' : '-',
1679 xive_end_is_uncond_escalation(end) ? 'u' : '-',
1680 xive_end_is_silent_escalation(end) ? 's' : '-',
1681 xive_end_is_firmware(end) ? 'f' : '-',
1682 priority, nvt_blk, nvt_idx);
1683
1684 if (qaddr_base) {
1685 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d",
1686 qaddr_base, qindex, qentries, qgen);
1687 xive_end_queue_pic_print_info(end, 6, buf);
1688 }
1689 g_string_append_c(buf, '\n');
1690 }
1691
1692 static void xive_end_enqueue(XiveEND *end, uint32_t data)
1693 {
1694 uint64_t qaddr_base = xive_end_qaddr(end);
1695 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
1696 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
1697 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1);
1698
1699 uint64_t qaddr = qaddr_base + (qindex << 2);
1700 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));
1701 uint32_t qentries = 1 << (qsize + 10);
1702
1703 if (dma_memory_write(&address_space_memory, qaddr,
1704 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) {
1705 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%"
1706 HWADDR_PRIx "\n", qaddr);
1707 return;
1708 }
1709
1710 qindex = (qindex + 1) & (qentries - 1);
1711 if (qindex == 0) {
1712 qgen ^= 1;
1713 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen);
1714 }
1715 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex);
1716 }
1717
1718 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf)
1719 {
1720 XiveEAS *eas = (XiveEAS *) &end->w4;
1721 uint8_t pq;
1722
1723 if (!xive_end_is_escalate(end)) {
1724 return;
1725 }
1726
1727 pq = xive_get_field32(END_W1_ESe, end->w1);
1728
1729 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
1730 end_idx,
1731 pq & XIVE_ESB_VAL_P ? 'P' : '-',
1732 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
1733 xive_eas_is_valid(eas) ? 'V' : ' ',
1734 xive_eas_is_masked(eas) ? 'M' : ' ',
1735 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
1736 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
1737 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
1738 }
1739
1740 /*
1741 * XIVE Router (aka. Virtualization Controller or IVRE)
1742 */
1743
1744 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
1745 XiveEAS *eas)
1746 {
1747 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1748
1749 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
1750 }
1751
1752 static
1753 int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
1754 uint8_t *pq)
1755 {
1756 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1757
1758 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq);
1759 }
1760
1761 static
1762 int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
1763 uint8_t *pq)
1764 {
1765 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1766
1767 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq);
1768 }
1769
1770 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
1771 XiveEND *end)
1772 {
1773 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1774
1775 return xrc->get_end(xrtr, end_blk, end_idx, end);
1776 }
1777
1778 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
1779 XiveEND *end, uint8_t word_number)
1780 {
1781 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1782
1783 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number);
1784 }
1785
1786 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
1787 XiveNVT *nvt)
1788 {
1789 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1790
1791 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt);
1792 }
1793
1794 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
1795 XiveNVT *nvt, uint8_t word_number)
1796 {
1797 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1798
1799 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
1800 }
1801
1802 static int xive_router_get_block_id(XiveRouter *xrtr)
1803 {
1804 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1805
1806 return xrc->get_block_id(xrtr);
1807 }
1808
1809 static void xive_router_realize(DeviceState *dev, Error **errp)
1810 {
1811 XiveRouter *xrtr = XIVE_ROUTER(dev);
1812
1813 assert(xrtr->xfb);
1814 }
1815
1816 static void xive_router_end_notify_handler(XiveRouter *xrtr, XiveEAS *eas)
1817 {
1818 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
1819
1820 return xrc->end_notify(xrtr, eas);
1821 }
1822
1823 /*
1824 * Encode the HW CAM line in the block group mode format :
1825 *
1826 * chip << 19 | 0000000 0 0001 thread (7Bit)
1827 */
1828 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
1829 {
1830 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
1831 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
1832 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr));
1833
1834 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
1835 }
1836
1837 uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
1838 {
1839 /*
1840 * Group size is a power of 2. The position of the first 0
1841 * (starting with the least significant bits) in the NVP index
1842 * gives the size of the group.
1843 */
1844 int first_zero = cto32(nvp_index);
1845 if (first_zero >= 31) {
1846 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x",
1847 nvp_index);
1848 return 0;
1849 }
1850
1851 return 1U << (first_zero + 1);
1852 }
1853
1854 uint8_t xive_get_group_level(bool crowd, bool ignore,
1855 uint32_t nvp_blk, uint32_t nvp_index)
1856 {
1857 int first_zero;
1858 uint8_t level;
1859
1860 if (!ignore) {
1861 g_assert(!crowd);
1862 return 0;
1863 }
1864
1865 first_zero = cto32(nvp_index);
1866 if (first_zero >= 31) {
1867 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x",
1868 nvp_index);
1869 return 0;
1870 }
1871
1872 level = (first_zero + 1) & 0b1111;
1873 if (crowd) {
1874 uint32_t blk;
1875
1876 /* crowd level is bit position of first 0 from the right in nvp_blk */
1877 first_zero = cto32(nvp_blk);
1878 if (first_zero >= 31) {
1879 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd block 0x%08x",
1880 nvp_blk);
1881 return 0;
1882 }
1883 blk = first_zero + 1;
1884
1885 /*
1886 * Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not supported.
1887 * HW will encode level 4 as the value 3. See xive2_pgofnext().
1888 */
1889 switch (blk) {
1890 case 1:
1891 case 2:
1892 break;
1893 case 4:
1894 blk = 3;
1895 break;
1896 default:
1897 g_assert_not_reached();
1898 }
1899
1900 /* Crowd level bits reside in upper 2 bits of the 6 bit group level */
1901 level |= blk << 4;
1902 }
1903 return level;
1904 }
1905
1906 /*
1907 * The thread context register words are in big-endian format.
1908 */
1909 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
1910 uint8_t format,
1911 uint8_t nvt_blk, uint32_t nvt_idx,
1912 bool cam_ignore, uint32_t logic_serv)
1913 {
1914 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
1915 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
1916 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
1917 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
1918 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
1919
1920 /*
1921 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1922 * identifier are ignored in the "CAM" match.
1923 */
1924
1925 if (format == 0) {
1926 if (cam_ignore == true) {
1927 /*
1928 * F=0 & i=1: Logical server notification (bits ignored at
1929 * the end of the NVT identifier)
1930 */
1931 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
1932 nvt_blk, nvt_idx);
1933 return -1;
1934 }
1935
1936 /* F=0 & i=0: Specific NVT notification */
1937
1938 /* PHYS ring */
1939 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
1940 cam == xive_tctx_hw_cam_line(xptr, tctx)) {
1941 return TM_QW3_HV_PHYS;
1942 }
1943
1944 /* HV POOL ring */
1945 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) &&
1946 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) {
1947 return TM_QW2_HV_POOL;
1948 }
1949
1950 /* OS ring */
1951 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) &&
1952 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) {
1953 return TM_QW1_OS;
1954 }
1955 } else {
1956 /* F=1 : User level Event-Based Branch (EBB) notification */
1957
1958 /* USER ring */
1959 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) &&
1960 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) &&
1961 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) &&
1962 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) {
1963 return TM_QW0_USER;
1964 }
1965 }
1966 return -1;
1967 }
1968
1969 /*
1970 * This is our simple Xive Presenter Engine model. It is merged in the
1971 * Router as it does not require an extra object.
1972 */
1973 bool xive_presenter_match(XiveFabric *xfb, uint8_t format,
1974 uint8_t nvt_blk, uint32_t nvt_idx,
1975 bool crowd, bool cam_ignore, uint8_t priority,
1976 uint32_t logic_serv, XiveTCTXMatch *match)
1977 {
1978 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);
1979
1980 memset(match, 0, sizeof(*match));
1981
1982 /*
1983 * Ask the machine to scan the interrupt controllers for a match.
1984 *
1985 * For VP-specific notification, we expect at most one match and
1986 * one call to the presenters is all we need (abbreviated notify
1987 * sequence documented by the architecture).
1988 *
1989 * For VP-group notification, match_nvt() is the equivalent of the
1990 * "histogram" and "poll" commands sent to the power bus to the
1991 * presenters. 'count' could be more than one, but we always
1992 * select the first match for now. 'precluded' tells if (at least)
1993 * one thread matches but can't take the interrupt now because
1994 * it's running at a more favored priority. We return the
1995 * information to the router so that it can take appropriate
1996 * actions (backlog, escalation, broadcast, etc...)
1997 *
1998 * If we were to implement a better way of dispatching the
1999 * interrupt in case of multiple matches (instead of the first
2000 * match), we would need a heuristic to elect a thread (for
2001 * example, the hardware keeps track of an 'age' in the TIMA) and
2002 * a new command to the presenters (the equivalent of the "assign"
2003 * power bus command in the documented full notify sequence.
2004 */
2005 return xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ignore,
2006 priority, logic_serv, match);
2007 }
2008
2009 /*
2010 * Notification using the END ESe/ESn bit (Event State Buffer for
2011 * escalation and notification). Provide further coalescing in the
2012 * Router.
2013 */
2014 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk,
2015 uint32_t end_idx, XiveEND *end,
2016 uint32_t end_esmask)
2017 {
2018 uint8_t pq = xive_get_field32(end_esmask, end->w1);
2019 bool notify = xive_esb_trigger(&pq);
2020
2021 if (pq != xive_get_field32(end_esmask, end->w1)) {
2022 end->w1 = xive_set_field32(end_esmask, end->w1, pq);
2023 xive_router_write_end(xrtr, end_blk, end_idx, end, 1);
2024 }
2025
2026 /* ESe/n[Q]=1 : end of notification */
2027 return notify;
2028 }
2029
2030 /*
2031 * An END trigger can come from an event trigger (IPI or HW) or from
2032 * another chip. We don't model the PowerBus but the END trigger
2033 * message has the same parameters than in the function below.
2034 */
2035 void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas)
2036 {
2037 XiveEND end;
2038 uint8_t priority;
2039 uint8_t format;
2040 uint8_t nvt_blk;
2041 uint32_t nvt_idx;
2042 XiveNVT nvt;
2043 XiveTCTXMatch match;
2044
2045 uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w);
2046 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w);
2047 uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w);
2048
2049 /* END cache lookup */
2050 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) {
2051 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
2052 end_idx);
2053 return;
2054 }
2055
2056 if (!xive_end_is_valid(&end)) {
2057 trace_xive_router_end_notify(end_blk, end_idx, end_data);
2058 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
2059 end_blk, end_idx);
2060 return;
2061 }
2062
2063 if (xive_end_is_enqueue(&end)) {
2064 xive_end_enqueue(&end, end_data);
2065 /* Enqueuing event data modifies the EQ toggle and index */
2066 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1);
2067 }
2068
2069 /*
2070 * When the END is silent, we skip the notification part.
2071 */
2072 if (xive_end_is_silent_escalation(&end)) {
2073 goto do_escalation;
2074 }
2075
2076 /*
2077 * The W7 format depends on the F bit in W6. It defines the type
2078 * of the notification :
2079 *
2080 * F=0 : single or multiple NVT notification
2081 * F=1 : User level Event-Based Branch (EBB) notification, no
2082 * priority
2083 */
2084 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6);
2085 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7);
2086
2087 /* The END is masked */
2088 if (format == 0 && priority == 0xff) {
2089 return;
2090 }
2091
2092 /*
2093 * Check the END ESn (Event State Buffer for notification) for
2094 * even further coalescing in the Router
2095 */
2096 if (!xive_end_is_notify(&end)) {
2097 /* ESn[Q]=1 : end of notification */
2098 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx,
2099 &end, END_W1_ESn)) {
2100 return;
2101 }
2102 }
2103
2104 /*
2105 * Follows IVPE notification
2106 */
2107 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6);
2108 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6);
2109
2110 /* NVT cache lookup */
2111 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
2112 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n",
2113 nvt_blk, nvt_idx);
2114 return;
2115 }
2116
2117 if (!xive_nvt_is_valid(&nvt)) {
2118 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n",
2119 nvt_blk, nvt_idx);
2120 return;
2121 }
2122
2123 /* TODO: Auto EOI. */
2124 /* we don't support VP-group notification on P9, so precluded is not used */
2125 if (xive_presenter_match(xrtr->xfb, format, nvt_blk, nvt_idx,
2126 false /* crowd */,
2127 xive_get_field32(END_W7_F0_IGNORE, end.w7),
2128 priority,
2129 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7),
2130 &match)) {
2131 trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, 0);
2132 xive_tctx_pipr_present(match.tctx, match.ring, priority, 0);
2133 return;
2134 }
2135
2136 /*
2137 * If no matching NVT is dispatched on a HW thread :
2138 * - specific VP: update the NVT structure if backlog is activated
2139 * - logical server : forward request to IVPE (not supported)
2140 */
2141 if (xive_end_is_backlog(&end)) {
2142 uint8_t ipb;
2143
2144 if (format == 1) {
2145 qemu_log_mask(LOG_GUEST_ERROR,
2146 "XIVE: END %x/%x invalid config: F1 & backlog\n",
2147 end_blk, end_idx);
2148 return;
2149 }
2150 /*
2151 * Record the IPB in the associated NVT structure for later
2152 * use. The presenter will resend the interrupt when the vCPU
2153 * is dispatched again on a HW thread.
2154 */
2155 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) |
2156 xive_priority_to_ipb(priority);
2157 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb);
2158 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
2159
2160 /*
2161 * On HW, follows a "Broadcast Backlog" to IVPEs
2162 */
2163 }
2164
2165 do_escalation:
2166 /*
2167 * If activated, escalate notification using the ESe PQ bits and
2168 * the EAS in w4-5
2169 */
2170 if (!xive_end_is_escalate(&end)) {
2171 return;
2172 }
2173
2174 /*
2175 * Check the END ESe (Event State Buffer for escalation) for even
2176 * further coalescing in the Router
2177 */
2178 if (!xive_end_is_uncond_escalation(&end)) {
2179 /* ESe[Q]=1 : end of notification */
2180 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx,
2181 &end, END_W1_ESe)) {
2182 return;
2183 }
2184 }
2185
2186 trace_xive_router_end_escalate(end_blk, end_idx,
2187 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4),
2188 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4),
2189 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5));
2190 /*
2191 * The END trigger becomes an Escalation trigger
2192 */
2193 xive_router_end_notify_handler(xrtr, (XiveEAS *) &end.w4);
2194 }
2195
2196 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
2197 {
2198 XiveRouter *xrtr = XIVE_ROUTER(xn);
2199 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
2200 uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
2201 XiveEAS eas;
2202
2203 /* EAS cache lookup */
2204 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) {
2205 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn);
2206 return;
2207 }
2208
2209 if (!pq_checked) {
2210 bool notify;
2211 uint8_t pq;
2212
2213 /* PQ cache lookup */
2214 if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) {
2215 /* Set FIR */
2216 g_assert_not_reached();
2217 }
2218
2219 notify = xive_esb_trigger(&pq);
2220
2221 if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) {
2222 /* Set FIR */
2223 g_assert_not_reached();
2224 }
2225
2226 if (!notify) {
2227 return;
2228 }
2229 }
2230
2231 if (!xive_eas_is_valid(&eas)) {
2232 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn);
2233 return;
2234 }
2235
2236 if (xive_eas_is_masked(&eas)) {
2237 /* Notification completed */
2238 return;
2239 }
2240
2241 /*
2242 * The event trigger becomes an END trigger
2243 */
2244 xive_router_end_notify_handler(xrtr, &eas);
2245 }
2246
2247 static const Property xive_router_properties[] = {
2248 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb,
2249 TYPE_XIVE_FABRIC, XiveFabric *),
2250 };
2251
2252 static void xive_router_class_init(ObjectClass *klass, const void *data)
2253 {
2254 DeviceClass *dc = DEVICE_CLASS(klass);
2255 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
2256 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
2257
2258 dc->desc = "XIVE Router Engine";
2259 device_class_set_props(dc, xive_router_properties);
2260 /* Parent is SysBusDeviceClass. No need to call its realize hook */
2261 dc->realize = xive_router_realize;
2262 xnc->notify = xive_router_notify;
2263
2264 /* By default, the router handles END triggers locally */
2265 xrc->end_notify = xive_router_end_notify;
2266 }
2267
2268 static const TypeInfo xive_router_info = {
2269 .name = TYPE_XIVE_ROUTER,
2270 .parent = TYPE_SYS_BUS_DEVICE,
2271 .abstract = true,
2272 .instance_size = sizeof(XiveRouter),
2273 .class_size = sizeof(XiveRouterClass),
2274 .class_init = xive_router_class_init,
2275 .interfaces = (const InterfaceInfo[]) {
2276 { TYPE_XIVE_NOTIFIER },
2277 { TYPE_XIVE_PRESENTER },
2278 { }
2279 }
2280 };
2281
2282 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf)
2283 {
2284 if (!xive_eas_is_valid(eas)) {
2285 return;
2286 }
2287
2288 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n",
2289 lisn, xive_eas_is_masked(eas) ? "M" : " ",
2290 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
2291 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
2292 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
2293 }
2294
2295 /*
2296 * END ESB MMIO loads
2297 */
2298 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size)
2299 {
2300 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque);
2301 uint32_t offset = addr & 0xFFF;
2302 uint8_t end_blk;
2303 uint32_t end_idx;
2304 XiveEND end;
2305 uint32_t end_esmask;
2306 uint8_t pq;
2307 uint64_t ret = -1;
2308
2309 /*
2310 * The block id should be deduced from the load address on the END
2311 * ESB MMIO but our model only supports a single block per XIVE chip.
2312 */
2313 end_blk = xive_router_get_block_id(xsrc->xrtr);
2314 end_idx = addr >> (xsrc->esb_shift + 1);
2315
2316 trace_xive_end_source_read(end_blk, end_idx, addr);
2317
2318 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
2319 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
2320 end_idx);
2321 return -1;
2322 }
2323
2324 if (!xive_end_is_valid(&end)) {
2325 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
2326 end_blk, end_idx);
2327 return -1;
2328 }
2329
2330 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe;
2331 pq = xive_get_field32(end_esmask, end.w1);
2332
2333 switch (offset) {
2334 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
2335 ret = xive_esb_eoi(&pq);
2336
2337 /* Forward the source event notification for routing ?? */
2338 break;
2339
2340 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
2341 ret = pq;
2342 break;
2343
2344 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
2345 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
2346 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
2347 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
2348 ret = xive_esb_set(&pq, (offset >> 8) & 0x3);
2349 break;
2350 default:
2351 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n",
2352 offset);
2353 return -1;
2354 }
2355
2356 if (pq != xive_get_field32(end_esmask, end.w1)) {
2357 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
2358 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
2359 }
2360
2361 return ret;
2362 }
2363
2364 /*
2365 * END ESB MMIO stores are invalid
2366 */
2367 static void xive_end_source_write(void *opaque, hwaddr addr,
2368 uint64_t value, unsigned size)
2369 {
2370 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%"
2371 HWADDR_PRIx"\n", addr);
2372 }
2373
2374 static const MemoryRegionOps xive_end_source_ops = {
2375 .read = xive_end_source_read,
2376 .write = xive_end_source_write,
2377 .endianness = DEVICE_BIG_ENDIAN,
2378 .valid = {
2379 .min_access_size = 1,
2380 .max_access_size = 8,
2381 },
2382 .impl = {
2383 .min_access_size = 1,
2384 .max_access_size = 8,
2385 },
2386 };
2387
2388 static void xive_end_source_realize(DeviceState *dev, Error **errp)
2389 {
2390 XiveENDSource *xsrc = XIVE_END_SOURCE(dev);
2391
2392 assert(xsrc->xrtr);
2393
2394 if (!xsrc->nr_ends) {
2395 error_setg(errp, "Number of interrupt needs to be greater than 0");
2396 return;
2397 }
2398
2399 if (xsrc->esb_shift != XIVE_ESB_4K &&
2400 xsrc->esb_shift != XIVE_ESB_64K) {
2401 error_setg(errp, "Invalid ESB shift setting");
2402 return;
2403 }
2404
2405 /*
2406 * Each END is assigned an even/odd pair of MMIO pages, the even page
2407 * manages the ESn field while the odd page manages the ESe field.
2408 */
2409 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc),
2410 &xive_end_source_ops, xsrc, "xive.end",
2411 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends);
2412 }
2413
2414 static const Property xive_end_source_properties[] = {
2415 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
2416 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
2417 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
2418 XiveRouter *),
2419 };
2420
2421 static void xive_end_source_class_init(ObjectClass *klass, const void *data)
2422 {
2423 DeviceClass *dc = DEVICE_CLASS(klass);
2424
2425 dc->desc = "XIVE END Source";
2426 device_class_set_props(dc, xive_end_source_properties);
2427 dc->realize = xive_end_source_realize;
2428 /*
2429 * Reason: part of XIVE interrupt controller, needs to be wired up,
2430 * e.g. by spapr_xive_instance_init().
2431 */
2432 dc->user_creatable = false;
2433 }
2434
2435 static const TypeInfo xive_end_source_info = {
2436 .name = TYPE_XIVE_END_SOURCE,
2437 .parent = TYPE_DEVICE,
2438 .instance_size = sizeof(XiveENDSource),
2439 .class_init = xive_end_source_class_init,
2440 };
2441
2442 /*
2443 * XIVE Notifier
2444 */
2445 static const TypeInfo xive_notifier_info = {
2446 .name = TYPE_XIVE_NOTIFIER,
2447 .parent = TYPE_INTERFACE,
2448 .class_size = sizeof(XiveNotifierClass),
2449 };
2450
2451 /*
2452 * XIVE Presenter
2453 */
2454 static const TypeInfo xive_presenter_info = {
2455 .name = TYPE_XIVE_PRESENTER,
2456 .parent = TYPE_INTERFACE,
2457 .class_size = sizeof(XivePresenterClass),
2458 };
2459
2460 /*
2461 * XIVE Fabric
2462 */
2463 static const TypeInfo xive_fabric_info = {
2464 .name = TYPE_XIVE_FABRIC,
2465 .parent = TYPE_INTERFACE,
2466 .class_size = sizeof(XiveFabricClass),
2467 };
2468
2469 static void xive_register_types(void)
2470 {
2471 type_register_static(&xive_fabric_info);
2472 type_register_static(&xive_source_info);
2473 type_register_static(&xive_notifier_info);
2474 type_register_static(&xive_presenter_info);
2475 type_register_static(&xive_router_info);
2476 type_register_static(&xive_end_source_info);
2477 type_register_static(&xive_tctx_info);
2478 }
2479
2480 type_init(xive_register_types)