| 1 | /* |
| 2 | * QEMU ICH9 Emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * Copyright (c) 2009, 2010, 2011 |
| 6 | * Isaku Yamahata <yamahata at valinux co jp> |
| 7 | * VA Linux Systems Japan K.K. |
| 8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> |
| 9 | * |
| 10 | * This is based on piix.c, but heavily modified. |
| 11 | * |
| 12 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 13 | * of this software and associated documentation files (the "Software"), to deal |
| 14 | * in the Software without restriction, including without limitation the rights |
| 15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 16 | * copies of the Software, and to permit persons to whom the Software is |
| 17 | * furnished to do so, subject to the following conditions: |
| 18 | * |
| 19 | * The above copyright notice and this permission notice shall be included in |
| 20 | * all copies or substantial portions of the Software. |
| 21 | * |
| 22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 28 | * THE SOFTWARE. |
| 29 | */ |
| 30 | |
| 31 | #include "qemu/osdep.h" |
| 32 | #include "qemu/log.h" |
| 33 | #include "target/i386/cpu.h" |
| 34 | #include "qapi/error.h" |
| 35 | #include "qapi/visitor.h" |
| 36 | #include "qemu/range.h" |
| 37 | #include "hw/dma/i8257.h" |
| 38 | #include "hw/isa/isa.h" |
| 39 | #include "migration/vmstate.h" |
| 40 | #include "hw/core/irq.h" |
| 41 | #include "hw/isa/apm.h" |
| 42 | #include "hw/pci/pci.h" |
| 43 | #include "hw/southbridge/ich9.h" |
| 44 | #include "hw/acpi/acpi.h" |
| 45 | #include "hw/acpi/ich9.h" |
| 46 | #include "hw/acpi/ich9_timer.h" |
| 47 | #include "hw/pci/pci_bus.h" |
| 48 | #include "hw/core/qdev-properties.h" |
| 49 | #include "system/runstate.h" |
| 50 | #include "system/system.h" |
| 51 | #include "hw/core/cpu.h" |
| 52 | #include "hw/nvram/fw_cfg.h" |
| 53 | #include "qemu/cutils.h" |
| 54 | #include "hw/acpi/acpi_aml_interface.h" |
| 55 | #include "trace.h" |
| 56 | |
| 57 | /*****************************************************************************/ |
| 58 | /* ICH9 LPC PCI to ISA bridge */ |
| 59 | |
| 60 | /* chipset configuration register |
| 61 | * to access chipset configuration registers, pci_[sg]et_{byte, word, long} |
| 62 | * are used. |
| 63 | * Although it's not pci configuration space, it's little endian as Intel. |
| 64 | */ |
| 65 | |
| 66 | static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) |
| 67 | { |
| 68 | int intx; |
| 69 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { |
| 70 | irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | static void ich9_cc_update(ICH9LPCState *lpc) |
| 75 | { |
| 76 | int slot; |
| 77 | int pci_intx; |
| 78 | |
| 79 | const int reg_offsets[] = { |
| 80 | ICH9_CC_D25IR, |
| 81 | ICH9_CC_D26IR, |
| 82 | ICH9_CC_D27IR, |
| 83 | ICH9_CC_D28IR, |
| 84 | ICH9_CC_D29IR, |
| 85 | ICH9_CC_D30IR, |
| 86 | ICH9_CC_D31IR, |
| 87 | }; |
| 88 | const int *offset; |
| 89 | |
| 90 | /* D{25 - 31}IR, but D30IR is read only to 0. */ |
| 91 | for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { |
| 92 | if (slot == 30) { |
| 93 | continue; |
| 94 | } |
| 95 | ich9_cc_update_ir(lpc->irr[slot], |
| 96 | pci_get_word(lpc->chip_config + *offset)); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * D30: DMI2PCI bridge |
| 101 | * It is arbitrarily decided how INTx lines of PCI devices behind |
| 102 | * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. |
| 103 | * INT[A-D] are connected to PIRQ[E-H] |
| 104 | */ |
| 105 | for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { |
| 106 | lpc->irr[30][pci_intx] = pci_intx + 4; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | static void ich9_cc_init(ICH9LPCState *lpc) |
| 111 | { |
| 112 | int slot; |
| 113 | int intx; |
| 114 | |
| 115 | /* the default irq routing is arbitrary as long as it matches with |
| 116 | * acpi irq routing table. |
| 117 | * The one that is incompatible with piix_pci(= bochs) one is |
| 118 | * intentionally chosen to let the users know that the different |
| 119 | * board is used. |
| 120 | * |
| 121 | * int[A-D] -> pirq[E-F] |
| 122 | * avoid pirq A-D because they are used for pci express port |
| 123 | */ |
| 124 | for (slot = 0; slot < PCI_SLOT_MAX; slot++) { |
| 125 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { |
| 126 | lpc->irr[slot][intx] = (slot + intx) % 4 + 4; |
| 127 | } |
| 128 | } |
| 129 | ich9_cc_update(lpc); |
| 130 | } |
| 131 | |
| 132 | static void ich9_cc_reset(ICH9LPCState *lpc) |
| 133 | { |
| 134 | uint8_t *c = lpc->chip_config; |
| 135 | uint32_t gcs = ICH9_CC_GCS_DEFAULT; |
| 136 | |
| 137 | if (lpc->pin_strap.spkr_hi) { |
| 138 | gcs |= ICH9_CC_GCS_NO_REBOOT; |
| 139 | } |
| 140 | |
| 141 | memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); |
| 142 | |
| 143 | pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); |
| 144 | pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); |
| 145 | pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); |
| 146 | pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); |
| 147 | pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); |
| 148 | pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); |
| 149 | pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); |
| 150 | pci_set_long(c + ICH9_CC_GCS, gcs); |
| 151 | |
| 152 | ich9_cc_update(lpc); |
| 153 | } |
| 154 | |
| 155 | static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) |
| 156 | { |
| 157 | *addr &= ICH9_CC_ADDR_MASK; |
| 158 | if (*addr + *len >= ICH9_CC_SIZE) { |
| 159 | *len = ICH9_CC_SIZE - *addr; |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | /* val: little endian */ |
| 164 | static void ich9_cc_write(void *opaque, hwaddr addr, |
| 165 | uint64_t val, unsigned len) |
| 166 | { |
| 167 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; |
| 168 | |
| 169 | trace_ich9_cc_write(addr, val, len); |
| 170 | ich9_cc_addr_len(&addr, &len); |
| 171 | memcpy(lpc->chip_config + addr, &val, len); |
| 172 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); |
| 173 | ich9_cc_update(lpc); |
| 174 | } |
| 175 | |
| 176 | /* return value: little endian */ |
| 177 | static uint64_t ich9_cc_read(void *opaque, hwaddr addr, |
| 178 | unsigned len) |
| 179 | { |
| 180 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; |
| 181 | |
| 182 | uint32_t val = 0; |
| 183 | ich9_cc_addr_len(&addr, &len); |
| 184 | memcpy(&val, lpc->chip_config + addr, len); |
| 185 | trace_ich9_cc_read(addr, val, len); |
| 186 | return val; |
| 187 | } |
| 188 | |
| 189 | /* IRQ routing */ |
| 190 | static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) |
| 191 | { |
| 192 | *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; |
| 193 | *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; |
| 194 | } |
| 195 | |
| 196 | static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, |
| 197 | int *pic_irq, int *pic_dis) |
| 198 | { |
| 199 | switch (pirq_num) { |
| 200 | case 0 ... 3: /* A-D */ |
| 201 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], |
| 202 | pic_irq, pic_dis); |
| 203 | return; |
| 204 | case 4 ... 7: /* E-H */ |
| 205 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], |
| 206 | pic_irq, pic_dis); |
| 207 | return; |
| 208 | default: |
| 209 | break; |
| 210 | } |
| 211 | abort(); |
| 212 | } |
| 213 | |
| 214 | /* gsi: i8259+ioapic irq 0-15, otherwise assert */ |
| 215 | static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) |
| 216 | { |
| 217 | int i, pic_level; |
| 218 | |
| 219 | assert(gsi < ICH9_LPC_PIC_NUM_PINS); |
| 220 | |
| 221 | /* The pic level is the logical OR of all the PCI irqs mapped to it */ |
| 222 | pic_level = 0; |
| 223 | for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { |
| 224 | int tmp_irq; |
| 225 | int tmp_dis; |
| 226 | ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); |
| 227 | if (!tmp_dis && tmp_irq == gsi) { |
| 228 | pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); |
| 229 | } |
| 230 | } |
| 231 | if (gsi == lpc->sci_gsi) { |
| 232 | pic_level |= lpc->sci_level; |
| 233 | } |
| 234 | |
| 235 | qemu_set_irq(lpc->gsi[gsi], pic_level); |
| 236 | } |
| 237 | |
| 238 | /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ |
| 239 | static int ich9_pirq_to_gsi(int pirq) |
| 240 | { |
| 241 | return pirq + ICH9_LPC_PIC_NUM_PINS; |
| 242 | } |
| 243 | |
| 244 | static int ich9_gsi_to_pirq(int gsi) |
| 245 | { |
| 246 | return gsi - ICH9_LPC_PIC_NUM_PINS; |
| 247 | } |
| 248 | |
| 249 | /* gsi: ioapic irq 16-23, otherwise assert */ |
| 250 | static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) |
| 251 | { |
| 252 | int level = 0; |
| 253 | |
| 254 | assert(gsi >= ICH9_LPC_PIC_NUM_PINS); |
| 255 | |
| 256 | level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); |
| 257 | if (gsi == lpc->sci_gsi) { |
| 258 | level |= lpc->sci_level; |
| 259 | } |
| 260 | |
| 261 | qemu_set_irq(lpc->gsi[gsi], level); |
| 262 | } |
| 263 | |
| 264 | static void ich9_lpc_set_irq(void *opaque, int pirq, int level) |
| 265 | { |
| 266 | ICH9LPCState *lpc = opaque; |
| 267 | int pic_irq, pic_dis; |
| 268 | |
| 269 | assert(0 <= pirq); |
| 270 | assert(pirq < ICH9_LPC_NB_PIRQS); |
| 271 | |
| 272 | ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); |
| 273 | ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); |
| 274 | ich9_lpc_update_pic(lpc, pic_irq); |
| 275 | } |
| 276 | |
| 277 | /* return the pirq number (PIRQ[A-H]:0-7) corresponding to |
| 278 | * a given device irq pin. |
| 279 | */ |
| 280 | static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) |
| 281 | { |
| 282 | BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); |
| 283 | PCIBus *pci_bus = PCI_BUS(bus); |
| 284 | PCIDevice *lpc_pdev = |
| 285 | pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; |
| 286 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); |
| 287 | |
| 288 | return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; |
| 289 | } |
| 290 | |
| 291 | static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) |
| 292 | { |
| 293 | ICH9LPCState *lpc = opaque; |
| 294 | PCIINTxRoute route; |
| 295 | int pic_irq; |
| 296 | int pic_dis; |
| 297 | |
| 298 | assert(0 <= pirq_pin); |
| 299 | assert(pirq_pin < ICH9_LPC_NB_PIRQS); |
| 300 | |
| 301 | route.mode = PCI_INTX_ENABLED; |
| 302 | ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); |
| 303 | if (!pic_dis) { |
| 304 | if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { |
| 305 | route.irq = pic_irq; |
| 306 | } else { |
| 307 | route.mode = PCI_INTX_DISABLED; |
| 308 | route.irq = -1; |
| 309 | } |
| 310 | } else { |
| 311 | /* |
| 312 | * Strictly speaking, this is wrong. The PIRQ should be routed |
| 313 | * to *both* the I/O APIC and the PIC, on different pins. The |
| 314 | * I/O APIC has a fixed mapping to IRQ16-23, while the PIC is |
| 315 | * routed according to the PIRQx_ROUT configuration. But QEMU |
| 316 | * doesn't (yet) cope with the concept of pin numbers differing |
| 317 | * between PIC and I/O APIC, and neither does the in-kernel KVM |
| 318 | * irqchip support. So we route to the I/O APIC *only* if the |
| 319 | * routing to the PIC is disabled in the PIRQx_ROUT settings. |
| 320 | * |
| 321 | * This seems to work even if we boot a Linux guest with 'noapic' |
| 322 | * to make it use the legacy PIC, and then kexec directly into a |
| 323 | * new kernel which uses the I/O APIC. The new kernel explicitly |
| 324 | * disables the PIRQ routing even though it doesn't need to care. |
| 325 | */ |
| 326 | route.irq = ich9_pirq_to_gsi(pirq_pin); |
| 327 | } |
| 328 | |
| 329 | return route; |
| 330 | } |
| 331 | |
| 332 | void ich9_generate_smi(void) |
| 333 | { |
| 334 | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
| 335 | } |
| 336 | |
| 337 | /* Returns -1 on error, IRQ number on success */ |
| 338 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc) |
| 339 | { |
| 340 | uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & |
| 341 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK; |
| 342 | switch (sel) { |
| 343 | case ICH9_LPC_ACPI_CTRL_9: |
| 344 | return 9; |
| 345 | case ICH9_LPC_ACPI_CTRL_10: |
| 346 | return 10; |
| 347 | case ICH9_LPC_ACPI_CTRL_11: |
| 348 | return 11; |
| 349 | case ICH9_LPC_ACPI_CTRL_20: |
| 350 | return 20; |
| 351 | case ICH9_LPC_ACPI_CTRL_21: |
| 352 | return 21; |
| 353 | default: |
| 354 | /* reserved */ |
| 355 | qemu_log_mask(LOG_GUEST_ERROR, |
| 356 | "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel); |
| 357 | break; |
| 358 | } |
| 359 | return -1; |
| 360 | } |
| 361 | |
| 362 | static void ich9_set_sci(void *opaque, int irq_num, int level) |
| 363 | { |
| 364 | ICH9LPCState *lpc = opaque; |
| 365 | int irq; |
| 366 | |
| 367 | assert(irq_num == 0); |
| 368 | level = !!level; |
| 369 | if (level == lpc->sci_level) { |
| 370 | return; |
| 371 | } |
| 372 | lpc->sci_level = level; |
| 373 | |
| 374 | irq = lpc->sci_gsi; |
| 375 | if (irq < 0) { |
| 376 | return; |
| 377 | } |
| 378 | |
| 379 | if (irq >= ICH9_LPC_PIC_NUM_PINS) { |
| 380 | ich9_lpc_update_apic(lpc, irq); |
| 381 | } else { |
| 382 | ich9_lpc_update_pic(lpc, irq); |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | static void smi_features_ok_callback(void *opaque) |
| 387 | { |
| 388 | ICH9LPCState *lpc = opaque; |
| 389 | uint64_t guest_features; |
| 390 | uint64_t guest_cpu_hotplug_features; |
| 391 | |
| 392 | if (lpc->smi_features_ok) { |
| 393 | /* negotiation already complete, features locked */ |
| 394 | return; |
| 395 | } |
| 396 | |
| 397 | memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); |
| 398 | le64_to_cpus(&guest_features); |
| 399 | if (guest_features & ~lpc->smi_host_features) { |
| 400 | /* guest requests invalid features, leave @features_ok at zero */ |
| 401 | return; |
| 402 | } |
| 403 | |
| 404 | guest_cpu_hotplug_features = guest_features & |
| 405 | (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | |
| 406 | BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); |
| 407 | if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && |
| 408 | guest_cpu_hotplug_features) { |
| 409 | /* |
| 410 | * cpu hot-[un]plug with SMI requires SMI broadcast, |
| 411 | * leave @features_ok at zero |
| 412 | */ |
| 413 | return; |
| 414 | } |
| 415 | |
| 416 | if (guest_cpu_hotplug_features == |
| 417 | BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) { |
| 418 | /* cpu hot-unplug is unsupported without cpu-hotplug */ |
| 419 | return; |
| 420 | } |
| 421 | |
| 422 | /* valid feature subset requested, lock it down, report success */ |
| 423 | lpc->smi_negotiated_features = guest_features; |
| 424 | lpc->smi_features_ok = 1; |
| 425 | } |
| 426 | |
| 427 | static void ich9_lpc_pm_init(ICH9LPCState *lpc) |
| 428 | { |
| 429 | qemu_irq sci_irq; |
| 430 | FWCfgState *fw_cfg = fw_cfg_find(); |
| 431 | |
| 432 | sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); |
| 433 | ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq); |
| 434 | |
| 435 | if (lpc->smi_host_features && fw_cfg) { |
| 436 | uint64_t host_features_le; |
| 437 | |
| 438 | host_features_le = cpu_to_le64(lpc->smi_host_features); |
| 439 | memcpy(lpc->smi_host_features_le, &host_features_le, |
| 440 | sizeof host_features_le); |
| 441 | fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", |
| 442 | lpc->smi_host_features_le, |
| 443 | sizeof lpc->smi_host_features_le); |
| 444 | |
| 445 | /* The other two guest-visible fields are cleared on device reset, we |
| 446 | * just link them into fw_cfg here. |
| 447 | */ |
| 448 | fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", |
| 449 | NULL, NULL, NULL, |
| 450 | lpc->smi_guest_features_le, |
| 451 | sizeof lpc->smi_guest_features_le, |
| 452 | false); |
| 453 | fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", |
| 454 | smi_features_ok_callback, NULL, lpc, |
| 455 | &lpc->smi_features_ok, |
| 456 | sizeof lpc->smi_features_ok, |
| 457 | true); |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | /* APM */ |
| 462 | |
| 463 | static void ich9_apm_ctrl_changed(uint32_t val, void *arg) |
| 464 | { |
| 465 | ICH9LPCState *lpc = arg; |
| 466 | |
| 467 | /* ACPI specs 3.0, 4.7.2.5 */ |
| 468 | acpi_pm1_cnt_update(&lpc->pm.acpi_regs, |
| 469 | val == ICH9_APM_ACPI_ENABLE, |
| 470 | val == ICH9_APM_ACPI_DISABLE); |
| 471 | if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { |
| 472 | return; |
| 473 | } |
| 474 | |
| 475 | /* SMI_EN = PMBASE + 30. SMI control and enable register */ |
| 476 | if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { |
| 477 | if (lpc->smi_negotiated_features & |
| 478 | (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { |
| 479 | CPUState *cs; |
| 480 | CPU_FOREACH(cs) { |
| 481 | cpu_interrupt(cs, CPU_INTERRUPT_SMI); |
| 482 | } |
| 483 | } else { |
| 484 | cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); |
| 485 | } |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | /* config:PMBASE */ |
| 490 | static void |
| 491 | ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) |
| 492 | { |
| 493 | uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); |
| 494 | uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); |
| 495 | int new_gsi; |
| 496 | |
| 497 | if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { |
| 498 | pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; |
| 499 | } else { |
| 500 | pm_io_base = 0; |
| 501 | } |
| 502 | |
| 503 | ich9_pm_iospace_update(&lpc->pm, pm_io_base); |
| 504 | |
| 505 | new_gsi = ich9_lpc_sci_irq(lpc); |
| 506 | if (new_gsi == -1) { |
| 507 | return; |
| 508 | } |
| 509 | if (lpc->sci_level && new_gsi != lpc->sci_gsi) { |
| 510 | qemu_set_irq(lpc->pm.irq, 0); |
| 511 | lpc->sci_gsi = new_gsi; |
| 512 | qemu_set_irq(lpc->pm.irq, 1); |
| 513 | } |
| 514 | lpc->sci_gsi = new_gsi; |
| 515 | } |
| 516 | |
| 517 | /* config:RCBA */ |
| 518 | static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) |
| 519 | { |
| 520 | uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); |
| 521 | |
| 522 | if (rcba_old & ICH9_LPC_RCBA_EN) { |
| 523 | memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); |
| 524 | } |
| 525 | if (rcba & ICH9_LPC_RCBA_EN) { |
| 526 | memory_region_add_subregion_overlap(get_system_memory(), |
| 527 | rcba & ICH9_LPC_RCBA_BA_MASK, |
| 528 | &lpc->rcrb_mem, 1); |
| 529 | } |
| 530 | } |
| 531 | |
| 532 | /* config:GEN_PMCON* */ |
| 533 | static void |
| 534 | ich9_lpc_pmcon_update(ICH9LPCState *lpc) |
| 535 | { |
| 536 | uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); |
| 537 | uint16_t wmask; |
| 538 | |
| 539 | if (lpc->pm.swsmi_timer_enabled) { |
| 540 | ich9_pm_update_swsmi_timer( |
| 541 | &lpc->pm, lpc->pm.smi_en & ICH9_PMIO_SMI_EN_SWSMI_EN); |
| 542 | } |
| 543 | if (lpc->pm.periodic_timer_enabled) { |
| 544 | ich9_pm_update_periodic_timer( |
| 545 | &lpc->pm, lpc->pm.smi_en & ICH9_PMIO_SMI_EN_PERIODIC_EN); |
| 546 | } |
| 547 | |
| 548 | if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { |
| 549 | wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); |
| 550 | wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; |
| 551 | pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); |
| 552 | lpc->pm.smi_en_wmask &= ~1; |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | static int ich9_lpc_post_load(void *opaque, int version_id) |
| 557 | { |
| 558 | ICH9LPCState *lpc = opaque; |
| 559 | |
| 560 | ich9_lpc_pmbase_sci_update(lpc); |
| 561 | ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); |
| 562 | ich9_lpc_pmcon_update(lpc); |
| 563 | return 0; |
| 564 | } |
| 565 | |
| 566 | static void ich9_lpc_config_write(PCIDevice *d, |
| 567 | uint32_t addr, uint32_t val, int len) |
| 568 | { |
| 569 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); |
| 570 | uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); |
| 571 | |
| 572 | pci_default_write_config(d, addr, val, len); |
| 573 | if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || |
| 574 | ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { |
| 575 | ich9_lpc_pmbase_sci_update(lpc); |
| 576 | } |
| 577 | if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { |
| 578 | ich9_lpc_rcba_update(lpc, rcba_old); |
| 579 | } |
| 580 | if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { |
| 581 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); |
| 582 | } |
| 583 | if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { |
| 584 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); |
| 585 | } |
| 586 | if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { |
| 587 | ich9_lpc_pmcon_update(lpc); |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | static void ich9_lpc_reset(DeviceState *qdev) |
| 592 | { |
| 593 | PCIDevice *d = PCI_DEVICE(qdev); |
| 594 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); |
| 595 | uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); |
| 596 | int i; |
| 597 | |
| 598 | for (i = 0; i < 4; i++) { |
| 599 | pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, |
| 600 | ICH9_LPC_PIRQ_ROUT_DEFAULT); |
| 601 | } |
| 602 | for (i = 0; i < 4; i++) { |
| 603 | pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, |
| 604 | ICH9_LPC_PIRQ_ROUT_DEFAULT); |
| 605 | } |
| 606 | pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); |
| 607 | |
| 608 | pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); |
| 609 | pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); |
| 610 | |
| 611 | ich9_cc_reset(lpc); |
| 612 | |
| 613 | ich9_lpc_pmbase_sci_update(lpc); |
| 614 | ich9_lpc_rcba_update(lpc, rcba_old); |
| 615 | |
| 616 | lpc->sci_level = 0; |
| 617 | lpc->rst_cnt = 0; |
| 618 | |
| 619 | memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); |
| 620 | lpc->smi_features_ok = 0; |
| 621 | lpc->smi_negotiated_features = 0; |
| 622 | } |
| 623 | |
| 624 | /* root complex register block is mapped into memory space */ |
| 625 | static const MemoryRegionOps rcrb_mmio_ops = { |
| 626 | .read = ich9_cc_read, |
| 627 | .write = ich9_cc_write, |
| 628 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 629 | }; |
| 630 | |
| 631 | static void ich9_lpc_machine_ready(Notifier *n, void *opaque) |
| 632 | { |
| 633 | ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); |
| 634 | MemoryRegion *io_as = pci_address_space_io(&s->d); |
| 635 | uint8_t *pci_conf; |
| 636 | |
| 637 | pci_conf = s->d.config; |
| 638 | if (memory_region_present(io_as, 0x3f8)) { |
| 639 | /* com1 */ |
| 640 | pci_conf[0x82] |= 0x01; |
| 641 | } |
| 642 | if (memory_region_present(io_as, 0x2f8)) { |
| 643 | /* com2 */ |
| 644 | pci_conf[0x82] |= 0x02; |
| 645 | } |
| 646 | if (memory_region_present(io_as, 0x378)) { |
| 647 | /* lpt */ |
| 648 | pci_conf[0x82] |= 0x04; |
| 649 | } |
| 650 | if (memory_region_present(io_as, 0x3f2)) { |
| 651 | /* floppy */ |
| 652 | pci_conf[0x82] |= 0x08; |
| 653 | } |
| 654 | } |
| 655 | |
| 656 | /* reset control */ |
| 657 | static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, |
| 658 | unsigned len) |
| 659 | { |
| 660 | ICH9LPCState *lpc = opaque; |
| 661 | |
| 662 | if (val & 4) { |
| 663 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 664 | return; |
| 665 | } |
| 666 | lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ |
| 667 | } |
| 668 | |
| 669 | static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) |
| 670 | { |
| 671 | ICH9LPCState *lpc = opaque; |
| 672 | |
| 673 | return lpc->rst_cnt; |
| 674 | } |
| 675 | |
| 676 | static const MemoryRegionOps ich9_rst_cnt_ops = { |
| 677 | .read = ich9_rst_cnt_read, |
| 678 | .write = ich9_rst_cnt_write, |
| 679 | .endianness = DEVICE_LITTLE_ENDIAN |
| 680 | }; |
| 681 | |
| 682 | static void ich9_lpc_initfn(Object *obj) |
| 683 | { |
| 684 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); |
| 685 | |
| 686 | object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); |
| 687 | |
| 688 | qdev_init_gpio_out_named(DEVICE(lpc), lpc->gsi, ICH9_GPIO_GSI, |
| 689 | IOAPIC_NUM_PINS); |
| 690 | |
| 691 | ich9_pm_reset_properties(&lpc->pm); |
| 692 | } |
| 693 | |
| 694 | static void ich9_lpc_realize(PCIDevice *d, Error **errp) |
| 695 | { |
| 696 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); |
| 697 | PCIBus *pci_bus = pci_get_bus(d); |
| 698 | ISABus *isa_bus; |
| 699 | uint32_t irq; |
| 700 | |
| 701 | if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) && |
| 702 | !(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) { |
| 703 | /* |
| 704 | * smi_features_ok_callback() throws an error on this. |
| 705 | * |
| 706 | * So bail out here instead of advertizing the invalid |
| 707 | * configuration and get obscure firmware failures from that. |
| 708 | */ |
| 709 | error_setg(errp, "cpu hot-unplug requires cpu hot-plug"); |
| 710 | return; |
| 711 | } |
| 712 | |
| 713 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), |
| 714 | errp); |
| 715 | if (!isa_bus) { |
| 716 | return; |
| 717 | } |
| 718 | |
| 719 | pci_set_long(d->wmask + ICH9_LPC_PMBASE, |
| 720 | ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); |
| 721 | pci_set_byte(d->wmask + ICH9_LPC_PMBASE, |
| 722 | ICH9_LPC_ACPI_CTRL_ACPI_EN | |
| 723 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); |
| 724 | |
| 725 | memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, |
| 726 | "lpc-rcrb-mmio", ICH9_CC_SIZE); |
| 727 | |
| 728 | ich9_cc_init(lpc); |
| 729 | apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); |
| 730 | |
| 731 | lpc->machine_ready.notify = ich9_lpc_machine_ready; |
| 732 | qemu_add_machine_init_done_notifier(&lpc->machine_ready); |
| 733 | |
| 734 | memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, |
| 735 | "lpc-reset-control", 1); |
| 736 | memory_region_add_subregion_overlap(pci_address_space_io(d), |
| 737 | ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, |
| 738 | 1); |
| 739 | |
| 740 | isa_bus_register_input_irqs(isa_bus, lpc->gsi); |
| 741 | |
| 742 | i8257_dma_init(OBJECT(d), isa_bus, 0); |
| 743 | |
| 744 | /* RTC */ |
| 745 | qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); |
| 746 | if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { |
| 747 | return; |
| 748 | } |
| 749 | irq = object_property_get_uint(OBJECT(&lpc->rtc), "irq", &error_fatal); |
| 750 | isa_connect_gpio_out(ISA_DEVICE(&lpc->rtc), 0, irq); |
| 751 | |
| 752 | pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); |
| 753 | pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); |
| 754 | pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); |
| 755 | |
| 756 | ich9_lpc_pm_init(lpc); |
| 757 | } |
| 758 | |
| 759 | static bool ich9_rst_cnt_needed(void *opaque) |
| 760 | { |
| 761 | ICH9LPCState *lpc = opaque; |
| 762 | |
| 763 | return (lpc->rst_cnt != 0); |
| 764 | } |
| 765 | |
| 766 | static const VMStateDescription vmstate_ich9_rst_cnt = { |
| 767 | .name = "ICH9LPC/rst_cnt", |
| 768 | .version_id = 1, |
| 769 | .minimum_version_id = 1, |
| 770 | .needed = ich9_rst_cnt_needed, |
| 771 | .fields = (const VMStateField[]) { |
| 772 | VMSTATE_UINT8(rst_cnt, ICH9LPCState), |
| 773 | VMSTATE_END_OF_LIST() |
| 774 | } |
| 775 | }; |
| 776 | |
| 777 | static bool ich9_smi_feat_needed(void *opaque) |
| 778 | { |
| 779 | ICH9LPCState *lpc = opaque; |
| 780 | |
| 781 | return !buffer_is_zero(lpc->smi_guest_features_le, |
| 782 | sizeof lpc->smi_guest_features_le) || |
| 783 | lpc->smi_features_ok; |
| 784 | } |
| 785 | |
| 786 | static const VMStateDescription vmstate_ich9_smi_feat = { |
| 787 | .name = "ICH9LPC/smi_feat", |
| 788 | .version_id = 1, |
| 789 | .minimum_version_id = 1, |
| 790 | .needed = ich9_smi_feat_needed, |
| 791 | .fields = (const VMStateField[]) { |
| 792 | VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, |
| 793 | sizeof(uint64_t)), |
| 794 | VMSTATE_UINT8(smi_features_ok, ICH9LPCState), |
| 795 | VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), |
| 796 | VMSTATE_END_OF_LIST() |
| 797 | } |
| 798 | }; |
| 799 | |
| 800 | static const VMStateDescription vmstate_ich9_lpc = { |
| 801 | .name = "ICH9LPC", |
| 802 | .version_id = 1, |
| 803 | .minimum_version_id = 1, |
| 804 | .post_load = ich9_lpc_post_load, |
| 805 | .fields = (const VMStateField[]) { |
| 806 | VMSTATE_PCI_DEVICE(d, ICH9LPCState), |
| 807 | VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), |
| 808 | VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), |
| 809 | VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), |
| 810 | VMSTATE_UINT32(sci_level, ICH9LPCState), |
| 811 | VMSTATE_END_OF_LIST() |
| 812 | }, |
| 813 | .subsections = (const VMStateDescription * const []) { |
| 814 | &vmstate_ich9_rst_cnt, |
| 815 | &vmstate_ich9_smi_feat, |
| 816 | NULL |
| 817 | } |
| 818 | }; |
| 819 | |
| 820 | static const Property ich9_lpc_properties[] = { |
| 821 | DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false), |
| 822 | DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), |
| 823 | DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false), |
| 824 | DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, |
| 825 | ICH9_LPC_SMI_F_BROADCAST_BIT, true), |
| 826 | DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, |
| 827 | ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), |
| 828 | DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, |
| 829 | ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true), |
| 830 | DEFINE_PROP_BOOL("x-smi-swsmi-timer", ICH9LPCState, |
| 831 | pm.swsmi_timer_enabled, true), |
| 832 | DEFINE_PROP_BOOL("x-smi-periodic-timer", ICH9LPCState, |
| 833 | pm.periodic_timer_enabled, true), |
| 834 | }; |
| 835 | |
| 836 | static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) |
| 837 | { |
| 838 | ICH9LPCState *s = ICH9_LPC_DEVICE(adev); |
| 839 | |
| 840 | acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); |
| 841 | } |
| 842 | |
| 843 | static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) |
| 844 | { |
| 845 | Aml *field; |
| 846 | BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); |
| 847 | Aml *sb_scope = aml_scope("\\_SB"); |
| 848 | |
| 849 | /* ICH9 PCI to ISA irq remapping */ |
| 850 | aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, |
| 851 | aml_int(0x60), 0x0C)); |
| 852 | /* Fields declarion has to happen *after* operation region */ |
| 853 | field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
| 854 | aml_append(field, aml_named_field("PRQA", 8)); |
| 855 | aml_append(field, aml_named_field("PRQB", 8)); |
| 856 | aml_append(field, aml_named_field("PRQC", 8)); |
| 857 | aml_append(field, aml_named_field("PRQD", 8)); |
| 858 | aml_append(field, aml_reserved_field(0x20)); |
| 859 | aml_append(field, aml_named_field("PRQE", 8)); |
| 860 | aml_append(field, aml_named_field("PRQF", 8)); |
| 861 | aml_append(field, aml_named_field("PRQG", 8)); |
| 862 | aml_append(field, aml_named_field("PRQH", 8)); |
| 863 | aml_append(sb_scope, field); |
| 864 | aml_append(scope, sb_scope); |
| 865 | |
| 866 | qbus_build_aml(bus, scope); |
| 867 | } |
| 868 | |
| 869 | static void ich9_lpc_class_init(ObjectClass *klass, const void *data) |
| 870 | { |
| 871 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 872 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 873 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
| 874 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
| 875 | AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass); |
| 876 | |
| 877 | static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; |
| 878 | static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; |
| 879 | |
| 880 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 881 | device_class_set_legacy_reset(dc, ich9_lpc_reset); |
| 882 | k->realize = ich9_lpc_realize; |
| 883 | dc->vmsd = &vmstate_ich9_lpc; |
| 884 | device_class_set_props(dc, ich9_lpc_properties); |
| 885 | k->config_write = ich9_lpc_config_write; |
| 886 | dc->desc = "ICH9 LPC bridge"; |
| 887 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 888 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; |
| 889 | k->revision = ICH9_A2_LPC_REVISION; |
| 890 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
| 891 | /* |
| 892 | * Reason: part of ICH9 southbridge, needs to be wired up by |
| 893 | * pc_q35_init() |
| 894 | */ |
| 895 | dc->user_creatable = false; |
| 896 | hc->pre_plug = ich9_pm_device_pre_plug_cb; |
| 897 | hc->plug = ich9_pm_device_plug_cb; |
| 898 | hc->unplug_request = ich9_pm_device_unplug_request_cb; |
| 899 | hc->unplug = ich9_pm_device_unplug_cb; |
| 900 | hc->is_hotpluggable_bus = ich9_pm_is_hotpluggable_bus; |
| 901 | adevc->ospm_status = ich9_pm_ospm_status; |
| 902 | adevc->send_event = ich9_send_gpe; |
| 903 | amldevc->build_dev_aml = build_ich9_isa_aml; |
| 904 | |
| 905 | object_class_property_add_uint8_ptr(klass, ACPI_PM_PROP_SCI_INT, |
| 906 | offsetof(ICH9LPCState, sci_gsi), |
| 907 | OBJ_PROP_FLAG_READ); |
| 908 | object_class_property_add_uint64_ptr(klass, |
| 909 | ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, |
| 910 | offsetof(ICH9LPCState, |
| 911 | smi_negotiated_features), |
| 912 | OBJ_PROP_FLAG_READ); |
| 913 | object_class_static_property_add_uint8_ptr(klass, |
| 914 | ACPI_PM_PROP_ACPI_ENABLE_CMD, |
| 915 | &acpi_enable_cmd, |
| 916 | OBJ_PROP_FLAG_READ); |
| 917 | object_class_static_property_add_uint8_ptr(klass, |
| 918 | ACPI_PM_PROP_ACPI_DISABLE_CMD, |
| 919 | &acpi_disable_cmd, |
| 920 | OBJ_PROP_FLAG_READ); |
| 921 | |
| 922 | ich9_pm_add_class_properties(klass, offsetof(ICH9LPCState, pm)); |
| 923 | } |
| 924 | |
| 925 | static const TypeInfo ich9_lpc_info = { |
| 926 | .name = TYPE_ICH9_LPC_DEVICE, |
| 927 | .parent = TYPE_PCI_DEVICE, |
| 928 | .instance_size = sizeof(ICH9LPCState), |
| 929 | .instance_init = ich9_lpc_initfn, |
| 930 | .class_init = ich9_lpc_class_init, |
| 931 | .interfaces = (const InterfaceInfo[]) { |
| 932 | { TYPE_HOTPLUG_HANDLER }, |
| 933 | { TYPE_ACPI_DEVICE_IF }, |
| 934 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 935 | { TYPE_ACPI_DEV_AML_IF }, |
| 936 | { } |
| 937 | } |
| 938 | }; |
| 939 | |
| 940 | static void ich9_lpc_register(void) |
| 941 | { |
| 942 | type_register_static(&ich9_lpc_info); |
| 943 | } |
| 944 | |
| 945 | type_init(ich9_lpc_register); |