| 1 | /* |
| 2 | * QEMU National Semiconductor PC87312 (Super I/O) |
| 3 | * |
| 4 | * Copyright (c) 2010-2012 Herve Poussineau |
| 5 | * Copyright (c) 2011-2012 Andreas Färber |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "hw/isa/pc87312.h" |
| 28 | #include "hw/core/qdev-properties.h" |
| 29 | #include "migration/vmstate.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | #include "qemu/module.h" |
| 33 | #include "trace.h" |
| 34 | |
| 35 | |
| 36 | #define REG_FER 0 |
| 37 | #define REG_FAR 1 |
| 38 | #define REG_PTR 2 |
| 39 | |
| 40 | #define FER_PARALLEL_EN 0x01 |
| 41 | #define FER_UART1_EN 0x02 |
| 42 | #define FER_UART2_EN 0x04 |
| 43 | #define FER_FDC_EN 0x08 |
| 44 | #define FER_FDC_4 0x10 |
| 45 | #define FER_FDC_ADDR 0x20 |
| 46 | #define FER_IDE_EN 0x40 |
| 47 | #define FER_IDE_ADDR 0x80 |
| 48 | |
| 49 | #define FAR_PARALLEL_ADDR 0x03 |
| 50 | #define FAR_UART1_ADDR 0x0C |
| 51 | #define FAR_UART2_ADDR 0x30 |
| 52 | #define FAR_UART_3_4 0xC0 |
| 53 | |
| 54 | #define PTR_POWER_DOWN 0x01 |
| 55 | #define PTR_CLOCK_DOWN 0x02 |
| 56 | #define PTR_PWDN 0x04 |
| 57 | #define PTR_IRQ_5_7 0x08 |
| 58 | #define PTR_UART1_TEST 0x10 |
| 59 | #define PTR_UART2_TEST 0x20 |
| 60 | #define PTR_LOCK_CONF 0x40 |
| 61 | #define PTR_EPP_MODE 0x80 |
| 62 | |
| 63 | |
| 64 | /* Parallel port */ |
| 65 | |
| 66 | static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index) |
| 67 | { |
| 68 | PC87312State *s = PC87312(sio); |
| 69 | return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN; |
| 70 | } |
| 71 | |
| 72 | static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 }; |
| 73 | |
| 74 | static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index) |
| 75 | { |
| 76 | PC87312State *s = PC87312(sio); |
| 77 | return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR]; |
| 78 | } |
| 79 | |
| 80 | static const unsigned int parallel_irq[] = { 5, 7, 5, 0 }; |
| 81 | |
| 82 | static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index) |
| 83 | { |
| 84 | PC87312State *s = PC87312(sio); |
| 85 | int idx; |
| 86 | idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR); |
| 87 | if (idx == 0) { |
| 88 | return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5; |
| 89 | } else { |
| 90 | return parallel_irq[idx]; |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | |
| 95 | /* UARTs */ |
| 96 | |
| 97 | static const uint16_t uart_base[2][4] = { |
| 98 | { 0x3e8, 0x338, 0x2e8, 0x220 }, |
| 99 | { 0x2e8, 0x238, 0x2e0, 0x228 } |
| 100 | }; |
| 101 | |
| 102 | static uint16_t get_uart_iobase(ISASuperIODevice *sio, uint8_t i) |
| 103 | { |
| 104 | PC87312State *s = PC87312(sio); |
| 105 | int idx; |
| 106 | idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; |
| 107 | if (idx == 0) { |
| 108 | return 0x3f8; |
| 109 | } else if (idx == 1) { |
| 110 | return 0x2f8; |
| 111 | } else { |
| 112 | return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6]; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static unsigned int get_uart_irq(ISASuperIODevice *sio, uint8_t i) |
| 117 | { |
| 118 | PC87312State *s = PC87312(sio); |
| 119 | int idx; |
| 120 | idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; |
| 121 | return (idx & 1) ? 3 : 4; |
| 122 | } |
| 123 | |
| 124 | static bool is_uart_enabled(ISASuperIODevice *sio, uint8_t i) |
| 125 | { |
| 126 | PC87312State *s = PC87312(sio); |
| 127 | return s->regs[REG_FER] & (FER_UART1_EN << i); |
| 128 | } |
| 129 | |
| 130 | |
| 131 | /* Floppy controller */ |
| 132 | |
| 133 | static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index) |
| 134 | { |
| 135 | PC87312State *s = PC87312(sio); |
| 136 | assert(!index); |
| 137 | return s->regs[REG_FER] & FER_FDC_EN; |
| 138 | } |
| 139 | |
| 140 | static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index) |
| 141 | { |
| 142 | PC87312State *s = PC87312(sio); |
| 143 | assert(!index); |
| 144 | return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0; |
| 145 | } |
| 146 | |
| 147 | static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index) |
| 148 | { |
| 149 | assert(!index); |
| 150 | return 6; |
| 151 | } |
| 152 | |
| 153 | |
| 154 | /* IDE controller */ |
| 155 | |
| 156 | static bool is_ide_enabled(ISASuperIODevice *sio, uint8_t index) |
| 157 | { |
| 158 | PC87312State *s = PC87312(sio); |
| 159 | |
| 160 | return s->regs[REG_FER] & FER_IDE_EN; |
| 161 | } |
| 162 | |
| 163 | static uint16_t get_ide_iobase(ISASuperIODevice *sio, uint8_t index) |
| 164 | { |
| 165 | PC87312State *s = PC87312(sio); |
| 166 | |
| 167 | if (index == 1) { |
| 168 | return get_ide_iobase(sio, 0) + 0x206; |
| 169 | } |
| 170 | return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0; |
| 171 | } |
| 172 | |
| 173 | static unsigned int get_ide_irq(ISASuperIODevice *sio, uint8_t index) |
| 174 | { |
| 175 | assert(index == 0); |
| 176 | return 14; |
| 177 | } |
| 178 | |
| 179 | static void reconfigure_devices(PC87312State *s) |
| 180 | { |
| 181 | error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)", |
| 182 | s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]); |
| 183 | } |
| 184 | |
| 185 | static void pc87312_soft_reset(PC87312State *s) |
| 186 | { |
| 187 | static const uint8_t fer_init[] = { |
| 188 | 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, |
| 189 | 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, |
| 190 | 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, |
| 191 | 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, |
| 192 | }; |
| 193 | static const uint8_t far_init[] = { |
| 194 | 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, |
| 195 | 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, |
| 196 | 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, |
| 197 | 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, |
| 198 | }; |
| 199 | static const uint8_t ptr_init[] = { |
| 200 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 201 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 202 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 203 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, |
| 204 | }; |
| 205 | |
| 206 | s->read_id_step = 0; |
| 207 | s->selected_index = REG_FER; |
| 208 | |
| 209 | s->regs[REG_FER] = fer_init[s->config & 0x1f]; |
| 210 | s->regs[REG_FAR] = far_init[s->config & 0x1f]; |
| 211 | s->regs[REG_PTR] = ptr_init[s->config & 0x1f]; |
| 212 | } |
| 213 | |
| 214 | static void pc87312_hard_reset(PC87312State *s) |
| 215 | { |
| 216 | pc87312_soft_reset(s); |
| 217 | } |
| 218 | |
| 219 | static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val, |
| 220 | unsigned int size) |
| 221 | { |
| 222 | PC87312State *s = opaque; |
| 223 | |
| 224 | trace_pc87312_io_write(addr, val); |
| 225 | |
| 226 | if ((addr & 1) == 0) { |
| 227 | /* Index register */ |
| 228 | s->read_id_step = 2; |
| 229 | s->selected_index = val; |
| 230 | } else { |
| 231 | /* Data register */ |
| 232 | if (s->selected_index < 3) { |
| 233 | s->regs[s->selected_index] = val; |
| 234 | reconfigure_devices(s); |
| 235 | } |
| 236 | } |
| 237 | } |
| 238 | |
| 239 | static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size) |
| 240 | { |
| 241 | PC87312State *s = opaque; |
| 242 | uint32_t val; |
| 243 | |
| 244 | if ((addr & 1) == 0) { |
| 245 | /* Index register */ |
| 246 | if (s->read_id_step++ == 0) { |
| 247 | val = 0x88; |
| 248 | } else if (s->read_id_step++ == 1) { |
| 249 | val = 0; |
| 250 | } else { |
| 251 | val = s->selected_index; |
| 252 | } |
| 253 | } else { |
| 254 | /* Data register */ |
| 255 | if (s->selected_index < 3) { |
| 256 | val = s->regs[s->selected_index]; |
| 257 | } else { |
| 258 | /* Invalid selected index */ |
| 259 | val = 0; |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | trace_pc87312_io_read(addr, val); |
| 264 | return val; |
| 265 | } |
| 266 | |
| 267 | static const MemoryRegionOps pc87312_io_ops = { |
| 268 | .read = pc87312_io_read, |
| 269 | .write = pc87312_io_write, |
| 270 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 271 | .valid = { |
| 272 | .min_access_size = 1, |
| 273 | .max_access_size = 1, |
| 274 | }, |
| 275 | }; |
| 276 | |
| 277 | static int pc87312_post_load(void *opaque, int version_id) |
| 278 | { |
| 279 | PC87312State *s = opaque; |
| 280 | |
| 281 | reconfigure_devices(s); |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | static void pc87312_reset(DeviceState *d) |
| 286 | { |
| 287 | PC87312State *s = PC87312(d); |
| 288 | |
| 289 | pc87312_soft_reset(s); |
| 290 | } |
| 291 | |
| 292 | static void pc87312_realize(DeviceState *dev, Error **errp) |
| 293 | { |
| 294 | PC87312State *s; |
| 295 | ISADevice *isa; |
| 296 | Error *local_err = NULL; |
| 297 | |
| 298 | s = PC87312(dev); |
| 299 | isa = ISA_DEVICE(dev); |
| 300 | isa_register_ioport(isa, &s->io, s->iobase); |
| 301 | pc87312_hard_reset(s); |
| 302 | |
| 303 | ISA_SUPERIO_GET_CLASS(dev)->parent_realize(dev, &local_err); |
| 304 | if (local_err) { |
| 305 | error_propagate(errp, local_err); |
| 306 | return; |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | static void pc87312_initfn(Object *obj) |
| 311 | { |
| 312 | PC87312State *s = PC87312(obj); |
| 313 | |
| 314 | memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2); |
| 315 | } |
| 316 | |
| 317 | static const VMStateDescription vmstate_pc87312 = { |
| 318 | .name = "pc87312", |
| 319 | .version_id = 1, |
| 320 | .minimum_version_id = 1, |
| 321 | .post_load = pc87312_post_load, |
| 322 | .fields = (const VMStateField[]) { |
| 323 | VMSTATE_UINT8(read_id_step, PC87312State), |
| 324 | VMSTATE_UINT8(selected_index, PC87312State), |
| 325 | VMSTATE_UINT8_ARRAY(regs, PC87312State, 3), |
| 326 | VMSTATE_END_OF_LIST() |
| 327 | } |
| 328 | }; |
| 329 | |
| 330 | static const Property pc87312_properties[] = { |
| 331 | DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398), |
| 332 | DEFINE_PROP_UINT8("config", PC87312State, config, 1), |
| 333 | }; |
| 334 | |
| 335 | static void pc87312_class_init(ObjectClass *klass, const void *data) |
| 336 | { |
| 337 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 338 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); |
| 339 | |
| 340 | device_class_set_legacy_reset(dc, pc87312_reset); |
| 341 | dc->vmsd = &vmstate_pc87312; |
| 342 | device_class_set_parent_realize(dc, pc87312_realize, |
| 343 | &sc->parent_realize); |
| 344 | device_class_set_props(dc, pc87312_properties); |
| 345 | |
| 346 | sc->parallel = (ISASuperIOFuncs){ |
| 347 | .count = 1, |
| 348 | .is_enabled = is_parallel_enabled, |
| 349 | .get_iobase = get_parallel_iobase, |
| 350 | .get_irq = get_parallel_irq, |
| 351 | }; |
| 352 | sc->serial = (ISASuperIOFuncs){ |
| 353 | .count = 2, |
| 354 | .is_enabled = is_uart_enabled, |
| 355 | .get_iobase = get_uart_iobase, |
| 356 | .get_irq = get_uart_irq, |
| 357 | }; |
| 358 | sc->floppy = (ISASuperIOFuncs){ |
| 359 | .count = 1, |
| 360 | .is_enabled = is_fdc_enabled, |
| 361 | .get_iobase = get_fdc_iobase, |
| 362 | .get_irq = get_fdc_irq, |
| 363 | }; |
| 364 | sc->ide = (ISASuperIOFuncs){ |
| 365 | .count = 1, |
| 366 | .is_enabled = is_ide_enabled, |
| 367 | .get_iobase = get_ide_iobase, |
| 368 | .get_irq = get_ide_irq, |
| 369 | }; |
| 370 | } |
| 371 | |
| 372 | static const TypeInfo pc87312_type_info = { |
| 373 | .name = TYPE_PC87312, |
| 374 | .parent = TYPE_ISA_SUPERIO, |
| 375 | .instance_size = sizeof(PC87312State), |
| 376 | .instance_init = pc87312_initfn, |
| 377 | .class_init = pc87312_class_init, |
| 378 | /* FIXME use a qdev drive property instead of drive_get() */ |
| 379 | }; |
| 380 | |
| 381 | static void pc87312_register_types(void) |
| 382 | { |
| 383 | type_register_static(&pc87312_type_info); |
| 384 | } |
| 385 | |
| 386 | type_init(pc87312_register_types) |