| 1 | /* |
| 2 | * VT82C686B south bridge support |
| 3 | * |
| 4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) |
| 5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) |
| 6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) |
| 7 | * This code is licensed under the GNU GPL v2. |
| 8 | * |
| 9 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 10 | * GNU GPL, version 2 or (at your option) any later version. |
| 11 | * |
| 12 | * VT8231 south bridge support and general clean up to allow it |
| 13 | * Copyright (c) 2018-2020 BALATON Zoltan |
| 14 | */ |
| 15 | |
| 16 | #include "qemu/osdep.h" |
| 17 | #include "hw/isa/vt82c686.h" |
| 18 | #include "hw/block/fdc.h" |
| 19 | #include "hw/char/parallel-isa.h" |
| 20 | #include "hw/char/serial-isa.h" |
| 21 | #include "hw/pci/pci.h" |
| 22 | #include "hw/core/qdev-properties.h" |
| 23 | #include "hw/ide/pci.h" |
| 24 | #include "hw/isa/isa.h" |
| 25 | #include "hw/isa/superio.h" |
| 26 | #include "hw/intc/i8259.h" |
| 27 | #include "hw/core/irq.h" |
| 28 | #include "hw/dma/i8257.h" |
| 29 | #include "hw/usb/hcd-uhci.h" |
| 30 | #include "hw/timer/i8254.h" |
| 31 | #include "hw/rtc/mc146818rtc.h" |
| 32 | #include "migration/vmstate.h" |
| 33 | #include "hw/isa/apm.h" |
| 34 | #include "hw/acpi/acpi.h" |
| 35 | #include "hw/i2c/pm_smbus.h" |
| 36 | #include "qapi/error.h" |
| 37 | #include "qemu/log.h" |
| 38 | #include "qemu/module.h" |
| 39 | #include "qemu/range.h" |
| 40 | #include "qemu/timer.h" |
| 41 | #include "trace.h" |
| 42 | |
| 43 | #define TYPE_VIA_PM "via-pm" |
| 44 | OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) |
| 45 | |
| 46 | struct ViaPMState { |
| 47 | PCIDevice dev; |
| 48 | MemoryRegion io; |
| 49 | ACPIREGS ar; |
| 50 | APMState apm; |
| 51 | PMSMBus smb; |
| 52 | }; |
| 53 | |
| 54 | static void pm_io_space_update(ViaPMState *s) |
| 55 | { |
| 56 | uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; |
| 57 | |
| 58 | memory_region_transaction_begin(); |
| 59 | memory_region_set_address(&s->io, pmbase); |
| 60 | memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); |
| 61 | memory_region_transaction_commit(); |
| 62 | } |
| 63 | |
| 64 | static void smb_io_space_update(ViaPMState *s) |
| 65 | { |
| 66 | uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; |
| 67 | |
| 68 | memory_region_transaction_begin(); |
| 69 | memory_region_set_address(&s->smb.io, smbase); |
| 70 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); |
| 71 | memory_region_transaction_commit(); |
| 72 | } |
| 73 | |
| 74 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
| 75 | { |
| 76 | ViaPMState *s = opaque; |
| 77 | |
| 78 | pm_io_space_update(s); |
| 79 | smb_io_space_update(s); |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static const VMStateDescription vmstate_acpi = { |
| 84 | .name = "vt82c686b_pm", |
| 85 | .version_id = 1, |
| 86 | .minimum_version_id = 1, |
| 87 | .post_load = vmstate_acpi_post_load, |
| 88 | .fields = (const VMStateField[]) { |
| 89 | VMSTATE_PCI_DEVICE(dev, ViaPMState), |
| 90 | VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), |
| 91 | VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), |
| 92 | VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), |
| 93 | VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), |
| 94 | VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), |
| 95 | VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), |
| 96 | VMSTATE_END_OF_LIST() |
| 97 | } |
| 98 | }; |
| 99 | |
| 100 | static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) |
| 101 | { |
| 102 | ViaPMState *s = VIA_PM(d); |
| 103 | |
| 104 | trace_via_pm_write(addr, val, len); |
| 105 | pci_default_write_config(d, addr, val, len); |
| 106 | if (ranges_overlap(addr, len, 0x48, 4)) { |
| 107 | uint32_t v = pci_get_long(s->dev.config + 0x48); |
| 108 | pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); |
| 109 | } |
| 110 | if (range_covers_byte(addr, len, 0x41)) { |
| 111 | pm_io_space_update(s); |
| 112 | } |
| 113 | if (ranges_overlap(addr, len, 0x90, 4)) { |
| 114 | uint32_t v = pci_get_long(s->dev.config + 0x90); |
| 115 | pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); |
| 116 | } |
| 117 | if (range_covers_byte(addr, len, 0xd2)) { |
| 118 | s->dev.config[0xd2] &= 0xf; |
| 119 | smb_io_space_update(s); |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) |
| 124 | { |
| 125 | trace_via_pm_io_write(addr, data, size); |
| 126 | } |
| 127 | |
| 128 | static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) |
| 129 | { |
| 130 | trace_via_pm_io_read(addr, 0, size); |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | static const MemoryRegionOps pm_io_ops = { |
| 135 | .read = pm_io_read, |
| 136 | .write = pm_io_write, |
| 137 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 138 | .impl = { |
| 139 | .min_access_size = 1, |
| 140 | .max_access_size = 1, |
| 141 | }, |
| 142 | }; |
| 143 | |
| 144 | static void pm_update_sci(ViaPMState *s) |
| 145 | { |
| 146 | int sci_level, pmsts; |
| 147 | |
| 148 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
| 149 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
| 150 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
| 151 | ACPI_BITMASK_POWER_BUTTON_ENABLE | |
| 152 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
| 153 | ACPI_BITMASK_TIMER_ENABLE)) != 0); |
| 154 | if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) { |
| 155 | /* |
| 156 | * FIXME: |
| 157 | * Fix device model that realizes this PM device and remove |
| 158 | * this work around. |
| 159 | * The device model should wire SCI and setup |
| 160 | * PCI_INTERRUPT_PIN properly. |
| 161 | * If PIN# = 0(interrupt pin isn't used), don't raise SCI as |
| 162 | * work around. |
| 163 | */ |
| 164 | pci_set_irq(&s->dev, sci_level); |
| 165 | } |
| 166 | /* schedule a timer interruption if needed */ |
| 167 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
| 168 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
| 169 | } |
| 170 | |
| 171 | static void pm_tmr_timer(ACPIREGS *ar) |
| 172 | { |
| 173 | ViaPMState *s = container_of(ar, ViaPMState, ar); |
| 174 | pm_update_sci(s); |
| 175 | } |
| 176 | |
| 177 | static void via_pm_reset(DeviceState *d) |
| 178 | { |
| 179 | ViaPMState *s = VIA_PM(d); |
| 180 | |
| 181 | memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, |
| 182 | PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); |
| 183 | /* Power Management IO base */ |
| 184 | pci_set_long(s->dev.config + 0x48, 1); |
| 185 | /* SMBus IO base */ |
| 186 | pci_set_long(s->dev.config + 0x90, 1); |
| 187 | |
| 188 | acpi_pm1_evt_reset(&s->ar); |
| 189 | acpi_pm1_cnt_reset(&s->ar); |
| 190 | acpi_pm_tmr_reset(&s->ar); |
| 191 | pm_update_sci(s); |
| 192 | |
| 193 | pm_io_space_update(s); |
| 194 | smb_io_space_update(s); |
| 195 | } |
| 196 | |
| 197 | static void via_pm_realize(PCIDevice *dev, Error **errp) |
| 198 | { |
| 199 | ViaPMState *s = VIA_PM(dev); |
| 200 | |
| 201 | pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | |
| 202 | PCI_STATUS_DEVSEL_MEDIUM); |
| 203 | |
| 204 | pm_smbus_init(DEVICE(s), &s->smb, false); |
| 205 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); |
| 206 | memory_region_set_enabled(&s->smb.io, false); |
| 207 | |
| 208 | apm_init(dev, &s->apm, NULL, s); |
| 209 | |
| 210 | memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); |
| 211 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); |
| 212 | memory_region_set_enabled(&s->io, false); |
| 213 | |
| 214 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
| 215 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
| 216 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); |
| 217 | } |
| 218 | |
| 219 | typedef struct via_pm_init_info { |
| 220 | uint16_t device_id; |
| 221 | } ViaPMInitInfo; |
| 222 | |
| 223 | static void via_pm_class_init(ObjectClass *klass, const void *data) |
| 224 | { |
| 225 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 226 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 227 | const ViaPMInitInfo *info = data; |
| 228 | |
| 229 | k->realize = via_pm_realize; |
| 230 | k->config_write = pm_write_config; |
| 231 | k->vendor_id = PCI_VENDOR_ID_VIA; |
| 232 | k->device_id = info->device_id; |
| 233 | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
| 234 | k->revision = 0x40; |
| 235 | device_class_set_legacy_reset(dc, via_pm_reset); |
| 236 | /* Reason: part of VIA south bridge, does not exist stand alone */ |
| 237 | dc->user_creatable = false; |
| 238 | dc->vmsd = &vmstate_acpi; |
| 239 | } |
| 240 | |
| 241 | static const TypeInfo via_pm_info = { |
| 242 | .name = TYPE_VIA_PM, |
| 243 | .parent = TYPE_PCI_DEVICE, |
| 244 | .instance_size = sizeof(ViaPMState), |
| 245 | .abstract = true, |
| 246 | .interfaces = (const InterfaceInfo[]) { |
| 247 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 248 | { }, |
| 249 | }, |
| 250 | }; |
| 251 | |
| 252 | static const ViaPMInitInfo vt82c686b_pm_init_info = { |
| 253 | .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, |
| 254 | }; |
| 255 | |
| 256 | #define TYPE_VT82C686B_PM "vt82c686b-pm" |
| 257 | |
| 258 | static const TypeInfo vt82c686b_pm_info = { |
| 259 | .name = TYPE_VT82C686B_PM, |
| 260 | .parent = TYPE_VIA_PM, |
| 261 | .class_init = via_pm_class_init, |
| 262 | .class_data = &vt82c686b_pm_init_info, |
| 263 | }; |
| 264 | |
| 265 | static const ViaPMInitInfo vt8231_pm_init_info = { |
| 266 | .device_id = PCI_DEVICE_ID_VIA_8231_PM, |
| 267 | }; |
| 268 | |
| 269 | #define TYPE_VT8231_PM "vt8231-pm" |
| 270 | |
| 271 | static const TypeInfo vt8231_pm_info = { |
| 272 | .name = TYPE_VT8231_PM, |
| 273 | .parent = TYPE_VIA_PM, |
| 274 | .class_init = via_pm_class_init, |
| 275 | .class_data = &vt8231_pm_init_info, |
| 276 | }; |
| 277 | |
| 278 | |
| 279 | #define TYPE_VIA_SUPERIO "via-superio" |
| 280 | OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) |
| 281 | |
| 282 | struct ViaSuperIOState { |
| 283 | ISASuperIODevice superio; |
| 284 | uint8_t regs[0x100]; |
| 285 | const MemoryRegionOps *io_ops; |
| 286 | MemoryRegion io; |
| 287 | }; |
| 288 | |
| 289 | static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) |
| 290 | { |
| 291 | memory_region_set_enabled(&s->io, enable); |
| 292 | } |
| 293 | |
| 294 | static void via_superio_realize(DeviceState *d, Error **errp) |
| 295 | { |
| 296 | ViaSuperIOState *s = VIA_SUPERIO(d); |
| 297 | ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s); |
| 298 | Error *local_err = NULL; |
| 299 | |
| 300 | assert(s->io_ops); |
| 301 | ic->parent_realize(d, &local_err); |
| 302 | if (local_err) { |
| 303 | error_propagate(errp, local_err); |
| 304 | return; |
| 305 | } |
| 306 | memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2); |
| 307 | memory_region_set_enabled(&s->io, false); |
| 308 | /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */ |
| 309 | memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, |
| 310 | &s->io); |
| 311 | } |
| 312 | |
| 313 | static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size) |
| 314 | { |
| 315 | ViaSuperIOState *sc = opaque; |
| 316 | uint8_t idx = sc->regs[0]; |
| 317 | uint8_t val = sc->regs[idx]; |
| 318 | |
| 319 | if (addr == 0) { |
| 320 | return idx; |
| 321 | } |
| 322 | if (addr == 1 && idx == 0) { |
| 323 | val = 0; /* reading reg 0 where we store index value */ |
| 324 | } |
| 325 | trace_via_superio_read(idx, val); |
| 326 | return val; |
| 327 | } |
| 328 | |
| 329 | static void via_superio_devices_enable(ViaSuperIOState *s, uint8_t data) |
| 330 | { |
| 331 | ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s); |
| 332 | |
| 333 | isa_parallel_set_enabled(s->superio.parallel[0], (data & 0x3) != 3); |
| 334 | for (int i = 0; i < ic->serial.count; i++) { |
| 335 | isa_serial_set_enabled(s->superio.serial[i], data & BIT(i + 2)); |
| 336 | } |
| 337 | isa_fdc_set_enabled(s->superio.floppy, data & BIT(4)); |
| 338 | } |
| 339 | |
| 340 | static void via_superio_class_init(ObjectClass *klass, const void *data) |
| 341 | { |
| 342 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 343 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); |
| 344 | |
| 345 | device_class_set_parent_realize(dc, via_superio_realize, |
| 346 | &sc->parent_realize); |
| 347 | } |
| 348 | |
| 349 | static const TypeInfo via_superio_info = { |
| 350 | .name = TYPE_VIA_SUPERIO, |
| 351 | .parent = TYPE_ISA_SUPERIO, |
| 352 | .instance_size = sizeof(ViaSuperIOState), |
| 353 | .class_size = sizeof(ISASuperIOClass), |
| 354 | .class_init = via_superio_class_init, |
| 355 | .abstract = true, |
| 356 | }; |
| 357 | |
| 358 | #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" |
| 359 | |
| 360 | static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, |
| 361 | uint64_t data, unsigned size) |
| 362 | { |
| 363 | ViaSuperIOState *sc = opaque; |
| 364 | uint8_t idx = sc->regs[0]; |
| 365 | |
| 366 | if (addr == 0) { /* config index register */ |
| 367 | sc->regs[0] = data; |
| 368 | return; |
| 369 | } |
| 370 | |
| 371 | /* config data register */ |
| 372 | trace_via_superio_write(idx, data); |
| 373 | switch (idx) { |
| 374 | case 0x00 ... 0xdf: |
| 375 | case 0xe4: |
| 376 | case 0xe5: |
| 377 | case 0xe9 ... 0xed: |
| 378 | case 0xf3: |
| 379 | case 0xf5: |
| 380 | case 0xf7: |
| 381 | case 0xf9 ... 0xfb: |
| 382 | case 0xfd ... 0xff: |
| 383 | /* ignore write to read only registers */ |
| 384 | return; |
| 385 | case 0xe2: |
| 386 | data &= 0x1f; |
| 387 | via_superio_devices_enable(sc, data); |
| 388 | break; |
| 389 | case 0xe3: |
| 390 | data &= 0xfc; |
| 391 | isa_fdc_set_iobase(sc->superio.floppy, data << 2); |
| 392 | break; |
| 393 | case 0xe6: |
| 394 | isa_parallel_set_iobase(sc->superio.parallel[0], data << 2); |
| 395 | break; |
| 396 | case 0xe7: |
| 397 | data &= 0xfe; |
| 398 | isa_serial_set_iobase(sc->superio.serial[0], data << 2); |
| 399 | break; |
| 400 | case 0xe8: |
| 401 | data &= 0xfe; |
| 402 | isa_serial_set_iobase(sc->superio.serial[1], data << 2); |
| 403 | break; |
| 404 | default: |
| 405 | qemu_log_mask(LOG_UNIMP, |
| 406 | "via_superio_cfg: unimplemented register 0x%x\n", idx); |
| 407 | break; |
| 408 | } |
| 409 | sc->regs[idx] = data; |
| 410 | } |
| 411 | |
| 412 | static const MemoryRegionOps vt82c686b_superio_cfg_ops = { |
| 413 | .read = via_superio_cfg_read, |
| 414 | .write = vt82c686b_superio_cfg_write, |
| 415 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 416 | .impl = { |
| 417 | .min_access_size = 1, |
| 418 | .max_access_size = 1, |
| 419 | }, |
| 420 | }; |
| 421 | |
| 422 | static void vt82c686b_superio_reset(DeviceState *dev) |
| 423 | { |
| 424 | ViaSuperIOState *s = VIA_SUPERIO(dev); |
| 425 | |
| 426 | memset(s->regs, 0, sizeof(s->regs)); |
| 427 | /* Device ID */ |
| 428 | vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); |
| 429 | vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); |
| 430 | /* |
| 431 | * Function select - only serial enabled |
| 432 | * Fuloong 2e's rescue-yl prints to the serial console w/o enabling it. This |
| 433 | * suggests that the serial ports are enabled by default, so override the |
| 434 | * datasheet. |
| 435 | */ |
| 436 | vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); |
| 437 | vt82c686b_superio_cfg_write(s, 1, 0x0f, 1); |
| 438 | /* Floppy ctrl base addr 0x3f0-7 */ |
| 439 | vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); |
| 440 | vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); |
| 441 | /* Parallel port base addr 0x378-f */ |
| 442 | vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); |
| 443 | vt82c686b_superio_cfg_write(s, 1, 0xde, 1); |
| 444 | /* Serial port 1 base addr 0x3f8-f */ |
| 445 | vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); |
| 446 | vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); |
| 447 | /* Serial port 2 base addr 0x2f8-f */ |
| 448 | vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); |
| 449 | vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); |
| 450 | |
| 451 | vt82c686b_superio_cfg_write(s, 0, 0, 1); |
| 452 | } |
| 453 | |
| 454 | static void vt82c686b_superio_init(Object *obj) |
| 455 | { |
| 456 | VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops; |
| 457 | } |
| 458 | |
| 459 | static void vt82c686b_superio_class_init(ObjectClass *klass, const void *data) |
| 460 | { |
| 461 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 462 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); |
| 463 | |
| 464 | device_class_set_legacy_reset(dc, vt82c686b_superio_reset); |
| 465 | sc->serial.count = 2; |
| 466 | sc->parallel.count = 1; |
| 467 | sc->ide.count = 0; /* emulated by via-ide */ |
| 468 | sc->floppy.count = 1; |
| 469 | } |
| 470 | |
| 471 | static const TypeInfo vt82c686b_superio_info = { |
| 472 | .name = TYPE_VT82C686B_SUPERIO, |
| 473 | .parent = TYPE_VIA_SUPERIO, |
| 474 | .instance_size = sizeof(ViaSuperIOState), |
| 475 | .instance_init = vt82c686b_superio_init, |
| 476 | .class_size = sizeof(ISASuperIOClass), |
| 477 | .class_init = vt82c686b_superio_class_init, |
| 478 | }; |
| 479 | |
| 480 | |
| 481 | #define TYPE_VT8231_SUPERIO "vt8231-superio" |
| 482 | |
| 483 | static void vt8231_superio_cfg_write(void *opaque, hwaddr addr, |
| 484 | uint64_t data, unsigned size) |
| 485 | { |
| 486 | ViaSuperIOState *sc = opaque; |
| 487 | uint8_t idx = sc->regs[0]; |
| 488 | |
| 489 | if (addr == 0) { /* config index register */ |
| 490 | sc->regs[0] = data; |
| 491 | return; |
| 492 | } |
| 493 | |
| 494 | /* config data register */ |
| 495 | trace_via_superio_write(idx, data); |
| 496 | switch (idx) { |
| 497 | case 0x00 ... 0xdf: |
| 498 | case 0xe7 ... 0xef: |
| 499 | case 0xf0 ... 0xf1: |
| 500 | case 0xf5: |
| 501 | case 0xf8: |
| 502 | case 0xfd: |
| 503 | /* ignore write to read only registers */ |
| 504 | return; |
| 505 | case 0xf2: |
| 506 | data &= 0x17; |
| 507 | via_superio_devices_enable(sc, data); |
| 508 | break; |
| 509 | case 0xf4: |
| 510 | data &= 0xfe; |
| 511 | isa_serial_set_iobase(sc->superio.serial[0], data << 2); |
| 512 | break; |
| 513 | case 0xf6: |
| 514 | isa_parallel_set_iobase(sc->superio.parallel[0], data << 2); |
| 515 | break; |
| 516 | case 0xf7: |
| 517 | data &= 0xfc; |
| 518 | isa_fdc_set_iobase(sc->superio.floppy, data << 2); |
| 519 | break; |
| 520 | default: |
| 521 | qemu_log_mask(LOG_UNIMP, |
| 522 | "via_superio_cfg: unimplemented register 0x%x\n", idx); |
| 523 | break; |
| 524 | } |
| 525 | sc->regs[idx] = data; |
| 526 | } |
| 527 | |
| 528 | static const MemoryRegionOps vt8231_superio_cfg_ops = { |
| 529 | .read = via_superio_cfg_read, |
| 530 | .write = vt8231_superio_cfg_write, |
| 531 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 532 | .impl = { |
| 533 | .min_access_size = 1, |
| 534 | .max_access_size = 1, |
| 535 | }, |
| 536 | }; |
| 537 | |
| 538 | static void vt8231_superio_reset(DeviceState *dev) |
| 539 | { |
| 540 | ViaSuperIOState *s = VIA_SUPERIO(dev); |
| 541 | |
| 542 | memset(s->regs, 0, sizeof(s->regs)); |
| 543 | /* Device ID */ |
| 544 | s->regs[0xf0] = 0x3c; |
| 545 | /* Device revision */ |
| 546 | s->regs[0xf1] = 0x01; |
| 547 | /* Function select - all disabled */ |
| 548 | vt8231_superio_cfg_write(s, 0, 0xf2, 1); |
| 549 | vt8231_superio_cfg_write(s, 1, 0x03, 1); |
| 550 | /* Serial port base addr */ |
| 551 | vt8231_superio_cfg_write(s, 0, 0xf4, 1); |
| 552 | vt8231_superio_cfg_write(s, 1, 0xfe, 1); |
| 553 | /* Parallel port base addr */ |
| 554 | vt8231_superio_cfg_write(s, 0, 0xf6, 1); |
| 555 | vt8231_superio_cfg_write(s, 1, 0xde, 1); |
| 556 | /* Floppy ctrl base addr */ |
| 557 | vt8231_superio_cfg_write(s, 0, 0xf7, 1); |
| 558 | vt8231_superio_cfg_write(s, 1, 0xfc, 1); |
| 559 | |
| 560 | vt8231_superio_cfg_write(s, 0, 0, 1); |
| 561 | } |
| 562 | |
| 563 | static void vt8231_superio_init(Object *obj) |
| 564 | { |
| 565 | VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops; |
| 566 | } |
| 567 | |
| 568 | static void vt8231_superio_class_init(ObjectClass *klass, const void *data) |
| 569 | { |
| 570 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 571 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); |
| 572 | |
| 573 | device_class_set_legacy_reset(dc, vt8231_superio_reset); |
| 574 | sc->serial.count = 1; |
| 575 | sc->parallel.count = 1; |
| 576 | sc->ide.count = 0; /* emulated by via-ide */ |
| 577 | sc->floppy.count = 1; |
| 578 | } |
| 579 | |
| 580 | static const TypeInfo vt8231_superio_info = { |
| 581 | .name = TYPE_VT8231_SUPERIO, |
| 582 | .parent = TYPE_VIA_SUPERIO, |
| 583 | .instance_size = sizeof(ViaSuperIOState), |
| 584 | .instance_init = vt8231_superio_init, |
| 585 | .class_size = sizeof(ISASuperIOClass), |
| 586 | .class_init = vt8231_superio_class_init, |
| 587 | }; |
| 588 | |
| 589 | |
| 590 | #define TYPE_VIA_ISA "via-isa" |
| 591 | OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA) |
| 592 | |
| 593 | struct ViaISAState { |
| 594 | PCIDevice dev; |
| 595 | |
| 596 | IRQState i8259_irq; |
| 597 | qemu_irq cpu_intr; |
| 598 | qemu_irq *isa_irqs_in; |
| 599 | uint16_t irq_state[ISA_NUM_IRQS]; |
| 600 | ViaSuperIOState via_sio; |
| 601 | MC146818RtcState rtc; |
| 602 | PCIIDEState ide; |
| 603 | UHCIState uhci[2]; |
| 604 | ViaPMState pm; |
| 605 | ViaAC97State ac97; |
| 606 | PCIDevice mc97; |
| 607 | }; |
| 608 | |
| 609 | static const VMStateDescription vmstate_via = { |
| 610 | .name = "via-isa", |
| 611 | .version_id = 1, |
| 612 | .minimum_version_id = 1, |
| 613 | .fields = (const VMStateField[]) { |
| 614 | VMSTATE_PCI_DEVICE(dev, ViaISAState), |
| 615 | VMSTATE_END_OF_LIST() |
| 616 | } |
| 617 | }; |
| 618 | |
| 619 | static void via_isa_init(Object *obj) |
| 620 | { |
| 621 | ViaISAState *s = VIA_ISA(obj); |
| 622 | |
| 623 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); |
| 624 | object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE); |
| 625 | object_initialize_child(obj, "uhci1", &s->uhci[0], TYPE_VT82C686B_USB_UHCI); |
| 626 | object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_UHCI); |
| 627 | object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97); |
| 628 | object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97); |
| 629 | } |
| 630 | |
| 631 | static const TypeInfo via_isa_info = { |
| 632 | .name = TYPE_VIA_ISA, |
| 633 | .parent = TYPE_PCI_DEVICE, |
| 634 | .instance_size = sizeof(ViaISAState), |
| 635 | .instance_init = via_isa_init, |
| 636 | .abstract = true, |
| 637 | .interfaces = (const InterfaceInfo[]) { |
| 638 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 639 | { }, |
| 640 | }, |
| 641 | }; |
| 642 | |
| 643 | static int via_isa_get_pci_irq(const ViaISAState *s, int pin) |
| 644 | { |
| 645 | switch (pin) { |
| 646 | case 0: |
| 647 | return s->dev.config[0x55] >> 4; |
| 648 | case 1: |
| 649 | return s->dev.config[0x56] & 0xf; |
| 650 | case 2: |
| 651 | return s->dev.config[0x56] >> 4; |
| 652 | case 3: |
| 653 | return s->dev.config[0x57] >> 4; |
| 654 | } |
| 655 | return 0; |
| 656 | } |
| 657 | |
| 658 | void via_isa_set_irq(PCIDevice *d, int pin, int level) |
| 659 | { |
| 660 | ViaISAState *s = VIA_ISA(pci_get_function_0(d)); |
| 661 | uint8_t irq = d->config[PCI_INTERRUPT_LINE], max_irq = 15; |
| 662 | int f = PCI_FUNC(d->devfn); |
| 663 | uint16_t mask; |
| 664 | |
| 665 | switch (f) { |
| 666 | case 0: /* PIRQ/PINT inputs */ |
| 667 | irq = via_isa_get_pci_irq(s, pin); |
| 668 | f = 8 + pin; /* Use function 8-11 for PCI interrupt inputs */ |
| 669 | break; |
| 670 | case 2: /* USB ports 0-1 */ |
| 671 | case 3: /* USB ports 2-3 */ |
| 672 | case 5: /* AC97 audio */ |
| 673 | max_irq = 14; |
| 674 | break; |
| 675 | } |
| 676 | |
| 677 | /* Keep track of the state of all sources */ |
| 678 | mask = BIT(f); |
| 679 | if (level) { |
| 680 | s->irq_state[0] |= mask; |
| 681 | } else { |
| 682 | s->irq_state[0] &= ~mask; |
| 683 | } |
| 684 | if (irq == 0 || irq == 0xff) { |
| 685 | return; /* disabled */ |
| 686 | } |
| 687 | if (unlikely(irq > max_irq || irq == 2)) { |
| 688 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d", |
| 689 | irq, f); |
| 690 | return; |
| 691 | } |
| 692 | /* Record source state at mapped IRQ */ |
| 693 | if (level) { |
| 694 | s->irq_state[irq] |= mask; |
| 695 | } else { |
| 696 | s->irq_state[irq] &= ~mask; |
| 697 | } |
| 698 | /* Make sure there are no stuck bits if mapping has changed */ |
| 699 | s->irq_state[irq] &= s->irq_state[0]; |
| 700 | /* ISA IRQ level is the OR of all sources routed to it */ |
| 701 | qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]); |
| 702 | } |
| 703 | |
| 704 | static void via_isa_pirq(void *opaque, int pin, int level) |
| 705 | { |
| 706 | via_isa_set_irq(opaque, pin, level); |
| 707 | } |
| 708 | |
| 709 | static void via_isa_request_i8259_irq(void *opaque, int irq, int level) |
| 710 | { |
| 711 | ViaISAState *s = opaque; |
| 712 | qemu_set_irq(s->cpu_intr, level); |
| 713 | } |
| 714 | |
| 715 | static void via_isa_realize(PCIDevice *d, Error **errp) |
| 716 | { |
| 717 | ViaISAState *s = VIA_ISA(d); |
| 718 | DeviceState *dev = DEVICE(d); |
| 719 | PCIBus *pci_bus = pci_get_bus(d); |
| 720 | ISABus *isa_bus; |
| 721 | int i; |
| 722 | |
| 723 | qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1); |
| 724 | qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS); |
| 725 | qemu_init_irq(&s->i8259_irq, via_isa_request_i8259_irq, s, 0); |
| 726 | isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d), |
| 727 | errp); |
| 728 | |
| 729 | if (!isa_bus) { |
| 730 | return; |
| 731 | } |
| 732 | |
| 733 | s->isa_irqs_in = i8259_init(isa_bus, &s->i8259_irq); |
| 734 | isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in); |
| 735 | i8254_pit_init(isa_bus, 0x40, 0, NULL); |
| 736 | i8257_dma_init(OBJECT(d), isa_bus, 0); |
| 737 | |
| 738 | /* RTC */ |
| 739 | qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); |
| 740 | if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { |
| 741 | return; |
| 742 | } |
| 743 | isa_connect_gpio_out(ISA_DEVICE(&s->rtc), 0, s->rtc.isairq); |
| 744 | |
| 745 | for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { |
| 746 | if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { |
| 747 | d->wmask[i] = 0; |
| 748 | } |
| 749 | } |
| 750 | |
| 751 | /* Super I/O */ |
| 752 | if (!qdev_realize(DEVICE(&s->via_sio), BUS(isa_bus), errp)) { |
| 753 | return; |
| 754 | } |
| 755 | |
| 756 | /* Function 1: IDE */ |
| 757 | qdev_prop_set_int32(DEVICE(&s->ide), "addr", d->devfn + 1); |
| 758 | if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { |
| 759 | return; |
| 760 | } |
| 761 | for (i = 0; i < 2; i++) { |
| 762 | qdev_connect_gpio_out_named(DEVICE(&s->ide), "isa-irq", i, |
| 763 | s->isa_irqs_in[14 + i]); |
| 764 | } |
| 765 | |
| 766 | /* Functions 2-3: USB Ports */ |
| 767 | for (i = 0; i < ARRAY_SIZE(s->uhci); i++) { |
| 768 | qdev_prop_set_int32(DEVICE(&s->uhci[i]), "addr", d->devfn + 2 + i); |
| 769 | if (!qdev_realize(DEVICE(&s->uhci[i]), BUS(pci_bus), errp)) { |
| 770 | return; |
| 771 | } |
| 772 | } |
| 773 | |
| 774 | /* Function 4: Power Management */ |
| 775 | qdev_prop_set_int32(DEVICE(&s->pm), "addr", d->devfn + 4); |
| 776 | if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { |
| 777 | return; |
| 778 | } |
| 779 | |
| 780 | /* Function 5: AC97 Audio */ |
| 781 | qdev_prop_set_int32(DEVICE(&s->ac97), "addr", d->devfn + 5); |
| 782 | if (!qdev_realize(DEVICE(&s->ac97), BUS(pci_bus), errp)) { |
| 783 | return; |
| 784 | } |
| 785 | |
| 786 | /* Function 6: MC97 Modem */ |
| 787 | qdev_prop_set_int32(DEVICE(&s->mc97), "addr", d->devfn + 6); |
| 788 | if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) { |
| 789 | return; |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | /* TYPE_VT82C686B_ISA */ |
| 794 | |
| 795 | static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, |
| 796 | uint32_t val, int len) |
| 797 | { |
| 798 | ViaISAState *s = VIA_ISA(d); |
| 799 | |
| 800 | trace_via_isa_write(addr, val, len); |
| 801 | pci_default_write_config(d, addr, val, len); |
| 802 | if (addr == 0x85) { |
| 803 | /* BIT(1): enable or disable superio config io ports */ |
| 804 | via_superio_io_enable(&s->via_sio, val & BIT(1)); |
| 805 | } |
| 806 | } |
| 807 | |
| 808 | static void vt82c686b_isa_reset(DeviceState *dev) |
| 809 | { |
| 810 | ViaISAState *s = VIA_ISA(dev); |
| 811 | uint8_t *pci_conf = s->dev.config; |
| 812 | |
| 813 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); |
| 814 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 815 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
| 816 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
| 817 | |
| 818 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ |
| 819 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ |
| 820 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ |
| 821 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ |
| 822 | pci_conf[0x59] = 0x04; |
| 823 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ |
| 824 | pci_conf[0x5f] = 0x04; |
| 825 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ |
| 826 | } |
| 827 | |
| 828 | static void vt82c686b_init(Object *obj) |
| 829 | { |
| 830 | ViaISAState *s = VIA_ISA(obj); |
| 831 | |
| 832 | object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERIO); |
| 833 | object_initialize_child(obj, "pm", &s->pm, TYPE_VT82C686B_PM); |
| 834 | } |
| 835 | |
| 836 | static void vt82c686b_class_init(ObjectClass *klass, const void *data) |
| 837 | { |
| 838 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 839 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 840 | |
| 841 | k->realize = via_isa_realize; |
| 842 | k->config_write = vt82c686b_write_config; |
| 843 | k->vendor_id = PCI_VENDOR_ID_VIA; |
| 844 | k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; |
| 845 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
| 846 | k->revision = 0x40; |
| 847 | device_class_set_legacy_reset(dc, vt82c686b_isa_reset); |
| 848 | dc->desc = "ISA bridge"; |
| 849 | dc->vmsd = &vmstate_via; |
| 850 | /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ |
| 851 | dc->user_creatable = false; |
| 852 | } |
| 853 | |
| 854 | static const TypeInfo vt82c686b_isa_info = { |
| 855 | .name = TYPE_VT82C686B_ISA, |
| 856 | .parent = TYPE_VIA_ISA, |
| 857 | .instance_size = sizeof(ViaISAState), |
| 858 | .instance_init = vt82c686b_init, |
| 859 | .class_init = vt82c686b_class_init, |
| 860 | }; |
| 861 | |
| 862 | /* TYPE_VT8231_ISA */ |
| 863 | |
| 864 | static void vt8231_write_config(PCIDevice *d, uint32_t addr, |
| 865 | uint32_t val, int len) |
| 866 | { |
| 867 | ViaISAState *s = VIA_ISA(d); |
| 868 | |
| 869 | trace_via_isa_write(addr, val, len); |
| 870 | pci_default_write_config(d, addr, val, len); |
| 871 | if (addr == 0x50) { |
| 872 | /* BIT(2): enable or disable superio config io ports */ |
| 873 | via_superio_io_enable(&s->via_sio, val & BIT(2)); |
| 874 | } |
| 875 | } |
| 876 | |
| 877 | static void vt8231_isa_reset(DeviceState *dev) |
| 878 | { |
| 879 | ViaISAState *s = VIA_ISA(dev); |
| 880 | uint8_t *pci_conf = s->dev.config; |
| 881 | |
| 882 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); |
| 883 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 884 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
| 885 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
| 886 | |
| 887 | pci_conf[0x4c] = 0x04; /* IDE interrupt Routing */ |
| 888 | pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */ |
| 889 | pci_conf[0x67] = 0x08; /* Fast IR Config */ |
| 890 | pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ |
| 891 | } |
| 892 | |
| 893 | static void vt8231_init(Object *obj) |
| 894 | { |
| 895 | ViaISAState *s = VIA_ISA(obj); |
| 896 | |
| 897 | object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO); |
| 898 | object_initialize_child(obj, "pm", &s->pm, TYPE_VT8231_PM); |
| 899 | } |
| 900 | |
| 901 | static void vt8231_class_init(ObjectClass *klass, const void *data) |
| 902 | { |
| 903 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 904 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 905 | |
| 906 | k->realize = via_isa_realize; |
| 907 | k->config_write = vt8231_write_config; |
| 908 | k->vendor_id = PCI_VENDOR_ID_VIA; |
| 909 | k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; |
| 910 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
| 911 | k->revision = 0x10; |
| 912 | device_class_set_legacy_reset(dc, vt8231_isa_reset); |
| 913 | dc->desc = "ISA bridge"; |
| 914 | dc->vmsd = &vmstate_via; |
| 915 | /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ |
| 916 | dc->user_creatable = false; |
| 917 | } |
| 918 | |
| 919 | static const TypeInfo vt8231_isa_info = { |
| 920 | .name = TYPE_VT8231_ISA, |
| 921 | .parent = TYPE_VIA_ISA, |
| 922 | .instance_size = sizeof(ViaISAState), |
| 923 | .instance_init = vt8231_init, |
| 924 | .class_init = vt8231_class_init, |
| 925 | }; |
| 926 | |
| 927 | |
| 928 | static void vt82c686b_register_types(void) |
| 929 | { |
| 930 | type_register_static(&via_pm_info); |
| 931 | type_register_static(&vt82c686b_pm_info); |
| 932 | type_register_static(&vt8231_pm_info); |
| 933 | type_register_static(&via_superio_info); |
| 934 | type_register_static(&vt82c686b_superio_info); |
| 935 | type_register_static(&vt8231_superio_info); |
| 936 | type_register_static(&via_isa_info); |
| 937 | type_register_static(&vt82c686b_isa_info); |
| 938 | type_register_static(&vt8231_isa_info); |
| 939 | } |
| 940 | |
| 941 | type_init(vt82c686b_register_types) |