| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * QEMU loongson 3a5000 develop board emulation |
| 4 | * |
| 5 | * Copyright (c) 2021 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | #include "qemu/osdep.h" |
| 8 | #include "qemu/units.h" |
| 9 | #include "qemu/datadir.h" |
| 10 | #include "qemu/cutils.h" |
| 11 | #include "qapi/error.h" |
| 12 | #include "exec/target_page.h" |
| 13 | #include "hw/core/boards.h" |
| 14 | #include "hw/char/serial-mm.h" |
| 15 | #include "system/kvm.h" |
| 16 | #include "system/tcg.h" |
| 17 | #include "system/system.h" |
| 18 | #include "system/qtest.h" |
| 19 | #include "system/runstate.h" |
| 20 | #include "system/reset.h" |
| 21 | #include "system/rtc.h" |
| 22 | #include "hw/loongarch/virt.h" |
| 23 | #include "system/address-spaces.h" |
| 24 | #include "hw/core/irq.h" |
| 25 | #include "net/net.h" |
| 26 | #include "hw/core/loader.h" |
| 27 | #include "elf.h" |
| 28 | #include "hw/intc/loongarch_ipi.h" |
| 29 | #include "hw/intc/loongarch_extioi.h" |
| 30 | #include "hw/intc/loongarch_pch_pic.h" |
| 31 | #include "hw/intc/loongarch_pch_msi.h" |
| 32 | #include "hw/intc/loongarch_dintc.h" |
| 33 | #include "hw/pci-host/gpex.h" |
| 34 | #include "hw/misc/unimp.h" |
| 35 | #include "hw/loongarch/fw_cfg.h" |
| 36 | #include "target/loongarch/cpu.h" |
| 37 | #include "target/loongarch/cpu-mmu.h" |
| 38 | #include "hw/firmware/smbios.h" |
| 39 | #include "qapi/qapi-visit-common.h" |
| 40 | #include "hw/acpi/generic_event_device.h" |
| 41 | #include "hw/mem/nvdimm.h" |
| 42 | #include "hw/core/platform-bus.h" |
| 43 | #include "hw/display/ramfb.h" |
| 44 | #include "hw/uefi/var-service-api.h" |
| 45 | #include "hw/mem/pc-dimm.h" |
| 46 | #include "system/tpm.h" |
| 47 | #include "system/block-backend.h" |
| 48 | #include "hw/block/flash.h" |
| 49 | #include "hw/virtio/virtio-iommu.h" |
| 50 | #include "qemu/error-report.h" |
| 51 | #include "qemu/log.h" |
| 52 | #include "kvm/kvm_loongarch.h" |
| 53 | |
| 54 | static void virt_get_dmsi(Object *obj, Visitor *v, const char *name, |
| 55 | void *opaque, Error **errp) |
| 56 | { |
| 57 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 58 | OnOffAuto dmsi = lvms->dmsi; |
| 59 | |
| 60 | visit_type_OnOffAuto(v, name, &dmsi, errp); |
| 61 | |
| 62 | } |
| 63 | static void virt_set_dmsi(Object *obj, Visitor *v, const char *name, |
| 64 | void *opaque, Error **errp) |
| 65 | { |
| 66 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 67 | |
| 68 | visit_type_OnOffAuto(v, name, &lvms->dmsi, errp); |
| 69 | |
| 70 | if (lvms->dmsi == ON_OFF_AUTO_OFF) { |
| 71 | lvms->misc_feature &= ~BIT(IOCSRF_DMSI); |
| 72 | lvms->misc_status &= ~BIT_ULL(IOCSRM_DMSI_EN); |
| 73 | } else if (lvms->dmsi == ON_OFF_AUTO_ON) { |
| 74 | lvms->misc_feature = BIT(IOCSRF_DMSI); |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 64 |
| 79 | #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) |
| 80 | |
| 81 | static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, |
| 82 | void *opaque, Error **errp) |
| 83 | { |
| 84 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 85 | OnOffAuto veiointc = lvms->veiointc; |
| 86 | |
| 87 | visit_type_OnOffAuto(v, name, &veiointc, errp); |
| 88 | } |
| 89 | |
| 90 | static void virt_set_veiointc(Object *obj, Visitor *v, const char *name, |
| 91 | void *opaque, Error **errp) |
| 92 | { |
| 93 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 94 | |
| 95 | visit_type_OnOffAuto(v, name, &lvms->veiointc, errp); |
| 96 | } |
| 97 | |
| 98 | static bool virt_get_highmem_mmio(Object *obj, Error **errp) |
| 99 | { |
| 100 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 101 | |
| 102 | return lvms->highmem_mmio; |
| 103 | } |
| 104 | |
| 105 | static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) |
| 106 | { |
| 107 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 108 | |
| 109 | lvms->highmem_mmio = value; |
| 110 | } |
| 111 | |
| 112 | static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, |
| 113 | const char *name, void *opaque, |
| 114 | Error **errp) |
| 115 | { |
| 116 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 117 | uint64_t size = lvms->gpex.mmio64.size; |
| 118 | |
| 119 | visit_type_size(v, name, &size, errp); |
| 120 | } |
| 121 | |
| 122 | static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, |
| 123 | const char *name, void *opaque, |
| 124 | Error **errp) |
| 125 | { |
| 126 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 127 | uint64_t size; |
| 128 | |
| 129 | if (!visit_type_size(v, name, &size, errp)) { |
| 130 | return; |
| 131 | } |
| 132 | |
| 133 | if (!is_power_of_2(size)) { |
| 134 | error_setg(errp, "highmem-mmio-size is not a power of 2"); |
| 135 | return; |
| 136 | } |
| 137 | |
| 138 | if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { |
| 139 | char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); |
| 140 | error_setg(errp, "highmem-mmio-size cannot be set to a lower value " |
| 141 | "than the default (%s)", sz); |
| 142 | g_free(sz); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | lvms->gpex.mmio64.size = size; |
| 147 | } |
| 148 | |
| 149 | static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, |
| 150 | const char *name, |
| 151 | const char *alias_prop_name) |
| 152 | { |
| 153 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
| 154 | |
| 155 | qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); |
| 156 | qdev_prop_set_uint8(dev, "width", 4); |
| 157 | qdev_prop_set_uint8(dev, "device-width", 2); |
| 158 | qdev_prop_set_bit(dev, "big-endian", false); |
| 159 | qdev_prop_set_uint16(dev, "id0", 0x89); |
| 160 | qdev_prop_set_uint16(dev, "id1", 0x18); |
| 161 | qdev_prop_set_uint16(dev, "id2", 0x00); |
| 162 | qdev_prop_set_uint16(dev, "id3", 0x00); |
| 163 | qdev_prop_set_string(dev, "name", name); |
| 164 | object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); |
| 165 | object_property_add_alias(OBJECT(lvms), alias_prop_name, |
| 166 | OBJECT(dev), "drive"); |
| 167 | return PFLASH_CFI01(dev); |
| 168 | } |
| 169 | |
| 170 | static void virt_flash_create(LoongArchVirtMachineState *lvms) |
| 171 | { |
| 172 | lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); |
| 173 | lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); |
| 174 | } |
| 175 | |
| 176 | static void virt_flash_map1(PFlashCFI01 *flash, |
| 177 | hwaddr base, hwaddr size, |
| 178 | MemoryRegion *sysmem) |
| 179 | { |
| 180 | DeviceState *dev = DEVICE(flash); |
| 181 | BlockBackend *blk; |
| 182 | hwaddr real_size = size; |
| 183 | |
| 184 | blk = pflash_cfi01_get_blk(flash); |
| 185 | if (blk) { |
| 186 | real_size = blk_getlength(blk); |
| 187 | assert(real_size && real_size <= size); |
| 188 | } |
| 189 | |
| 190 | assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); |
| 191 | assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); |
| 192 | |
| 193 | qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); |
| 194 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 195 | memory_region_add_subregion(sysmem, base, |
| 196 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); |
| 197 | } |
| 198 | |
| 199 | static void virt_flash_map(LoongArchVirtMachineState *lvms, |
| 200 | MemoryRegion *sysmem) |
| 201 | { |
| 202 | PFlashCFI01 *flash0 = lvms->flash[0]; |
| 203 | PFlashCFI01 *flash1 = lvms->flash[1]; |
| 204 | |
| 205 | virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); |
| 206 | virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); |
| 207 | } |
| 208 | |
| 209 | static void virt_build_smbios(LoongArchVirtMachineState *lvms) |
| 210 | { |
| 211 | MachineState *ms = MACHINE(lvms); |
| 212 | MachineClass *mc = MACHINE_GET_CLASS(lvms); |
| 213 | uint8_t *smbios_tables, *smbios_anchor; |
| 214 | size_t smbios_tables_len, smbios_anchor_len; |
| 215 | const char *product = "QEMU Virtual Machine"; |
| 216 | |
| 217 | if (!lvms->fw_cfg) { |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | if (kvm_enabled()) { |
| 222 | product = "KVM Virtual Machine"; |
| 223 | } |
| 224 | |
| 225 | smbios_set_defaults("QEMU", product, mc->name); |
| 226 | |
| 227 | smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, |
| 228 | NULL, 0, |
| 229 | &smbios_tables, &smbios_tables_len, |
| 230 | &smbios_anchor, &smbios_anchor_len, &error_fatal); |
| 231 | |
| 232 | if (smbios_anchor) { |
| 233 | fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", |
| 234 | smbios_tables, smbios_tables_len); |
| 235 | fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", |
| 236 | smbios_anchor, smbios_anchor_len); |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | static void virt_done(Notifier *notifier, void *data) |
| 241 | { |
| 242 | LoongArchVirtMachineState *lvms = container_of(notifier, |
| 243 | LoongArchVirtMachineState, machine_done); |
| 244 | virt_build_smbios(lvms); |
| 245 | virt_acpi_setup(lvms); |
| 246 | virt_fdt_setup(lvms); |
| 247 | } |
| 248 | |
| 249 | static void virt_powerdown_req(Notifier *notifier, void *opaque) |
| 250 | { |
| 251 | LoongArchVirtMachineState *s; |
| 252 | |
| 253 | s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); |
| 254 | acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); |
| 255 | } |
| 256 | |
| 257 | static void memmap_add_entry(MachineState *ms, uint64_t address, |
| 258 | uint64_t length, uint32_t type) |
| 259 | { |
| 260 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(ms); |
| 261 | struct memmap_entry *memmap_table; |
| 262 | unsigned int memmap_entries; |
| 263 | |
| 264 | memmap_table = lvms->memmap_table; |
| 265 | memmap_entries = lvms->memmap_entries; |
| 266 | /* Ensure there are no duplicate entries. */ |
| 267 | for (unsigned i = 0; i < memmap_entries; i++) { |
| 268 | assert(memmap_table[i].address != address); |
| 269 | } |
| 270 | |
| 271 | memmap_table = g_renew(struct memmap_entry, memmap_table, |
| 272 | memmap_entries + 1); |
| 273 | memmap_table[memmap_entries].address = cpu_to_le64(address); |
| 274 | memmap_table[memmap_entries].length = cpu_to_le64(length); |
| 275 | memmap_table[memmap_entries].type = cpu_to_le32(type); |
| 276 | memmap_table[memmap_entries].reserved = 0; |
| 277 | memmap_entries++; |
| 278 | lvms->memmap_table = memmap_table; |
| 279 | lvms->memmap_entries = memmap_entries; |
| 280 | } |
| 281 | |
| 282 | static DeviceState *create_acpi_ged(DeviceState *pch_pic, |
| 283 | LoongArchVirtMachineState *lvms) |
| 284 | { |
| 285 | DeviceState *dev; |
| 286 | MachineState *ms = MACHINE(lvms); |
| 287 | MachineClass *mc = MACHINE_GET_CLASS(lvms); |
| 288 | uint32_t event = ACPI_GED_PWR_DOWN_EVT; |
| 289 | |
| 290 | if (ms->ram_slots) { |
| 291 | event |= ACPI_GED_MEM_HOTPLUG_EVT; |
| 292 | } |
| 293 | |
| 294 | if (mc->has_hotpluggable_cpus) { |
| 295 | event |= ACPI_GED_CPU_HOTPLUG_EVT; |
| 296 | } |
| 297 | |
| 298 | dev = qdev_new(TYPE_ACPI_GED); |
| 299 | qdev_prop_set_uint32(dev, "ged-event", event); |
| 300 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 301 | |
| 302 | /* ged event */ |
| 303 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); |
| 304 | /* memory hotplug */ |
| 305 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); |
| 306 | /* ged regs used for reset and power down */ |
| 307 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); |
| 308 | |
| 309 | if (mc->has_hotpluggable_cpus) { |
| 310 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 3, VIRT_GED_CPUHP_ADDR); |
| 311 | } |
| 312 | |
| 313 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, |
| 314 | qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); |
| 315 | return dev; |
| 316 | } |
| 317 | |
| 318 | static DeviceState *create_platform_bus(DeviceState *pch_pic) |
| 319 | { |
| 320 | DeviceState *dev; |
| 321 | SysBusDevice *sysbus; |
| 322 | int i, irq; |
| 323 | MemoryRegion *sysmem = get_system_memory(); |
| 324 | |
| 325 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); |
| 326 | dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); |
| 327 | qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); |
| 328 | qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); |
| 329 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 330 | |
| 331 | sysbus = SYS_BUS_DEVICE(dev); |
| 332 | for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { |
| 333 | irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; |
| 334 | sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); |
| 335 | } |
| 336 | |
| 337 | memory_region_add_subregion(sysmem, |
| 338 | VIRT_PLATFORM_BUS_BASEADDRESS, |
| 339 | sysbus_mmio_get_region(sysbus, 0)); |
| 340 | return dev; |
| 341 | } |
| 342 | |
| 343 | static void virt_set_highmmio(LoongArchVirtMachineState *lvms) |
| 344 | { |
| 345 | LoongArchCPU *cpu = LOONGARCH_CPU(first_cpu); |
| 346 | CPULoongArchState *env = &cpu->env; |
| 347 | struct GPEXConfig *gpex; |
| 348 | int vaddr_bits, phys_bits; |
| 349 | |
| 350 | vaddr_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, VALEN) + 1; |
| 351 | phys_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN) + 1; |
| 352 | if (phys_bits <= 32) { |
| 353 | return; |
| 354 | } |
| 355 | |
| 356 | gpex = &lvms->gpex; |
| 357 | if (gpex->mmio64.size == 0) { |
| 358 | gpex->mmio64.size = DEFAULT_HIGH_PCIE_MMIO_SIZE; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * UEFI BIOS uses 1:1 identified mapping PCI high mmio space, and |
| 363 | * virtual address space is low end through PGDL page table. |
| 364 | * |
| 365 | * Max physical address bit cannot exceed vaddr_bits - 1 |
| 366 | */ |
| 367 | if (phys_bits > (vaddr_bits - 1)) { |
| 368 | phys_bits = vaddr_bits - 1; |
| 369 | } |
| 370 | |
| 371 | /* |
| 372 | * GPEX base address starts from end of physical address |
| 373 | */ |
| 374 | gpex->mmio64.base = BIT_ULL(phys_bits) - BIT_ULL(phys_bits - 3); |
| 375 | if (gpex->mmio64.base + gpex->mmio64.size > BIT_ULL(phys_bits)) { |
| 376 | error_report("GPEX region base %" PRIu64 " size %" PRIu64 |
| 377 | " exceeds %d physical bits", |
| 378 | gpex->mmio64.base, gpex->mmio64.size, |
| 379 | phys_bits); |
| 380 | exit(EXIT_FAILURE); |
| 381 | } |
| 382 | |
| 383 | if (lvms->ram_end > gpex->mmio64.base) { |
| 384 | error_report("DRAM end address %" PRIu64 |
| 385 | " exceeds GPEX region base %" PRIu64, |
| 386 | lvms->ram_end, gpex->mmio64.base); |
| 387 | exit(EXIT_FAILURE); |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | static void virt_devices_init(DeviceState *pch_pic, |
| 392 | LoongArchVirtMachineState *lvms) |
| 393 | { |
| 394 | MachineClass *mc = MACHINE_GET_CLASS(lvms); |
| 395 | DeviceState *gpex_dev; |
| 396 | SysBusDevice *d; |
| 397 | PCIBus *pci_bus; |
| 398 | MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; |
| 399 | MemoryRegion *mmio_alias, *mmio_reg; |
| 400 | hwaddr mmio_base, mmio_size; |
| 401 | int i, irq; |
| 402 | |
| 403 | gpex_dev = qdev_new(TYPE_GPEX_HOST); |
| 404 | d = SYS_BUS_DEVICE(gpex_dev); |
| 405 | sysbus_realize_and_unref(d, &error_fatal); |
| 406 | pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; |
| 407 | lvms->gpex.pio.base = VIRT_PCI_IO_BASE; |
| 408 | lvms->gpex.pio.size = VIRT_PCI_IO_SIZE; |
| 409 | lvms->gpex.ecam.base = VIRT_PCI_CFG_BASE; |
| 410 | lvms->gpex.ecam.size = VIRT_PCI_CFG_SIZE; |
| 411 | lvms->gpex.irq = VIRT_GSI_BASE + VIRT_DEVICE_IRQS; |
| 412 | lvms->gpex.bus = pci_bus; |
| 413 | mmio_base = lvms->gpex.mmio64.base; |
| 414 | mmio_size = lvms->gpex.mmio64.size; |
| 415 | if (lvms->highmem_mmio) { |
| 416 | virt_set_highmmio(lvms); |
| 417 | lvms->gpex.mmio32.base = VIRT_PCI_MEM_BASE; |
| 418 | lvms->gpex.mmio32.size = VIRT_PCI_MEM_SIZE; |
| 419 | mmio_base = lvms->gpex.mmio32.base; |
| 420 | mmio_size = lvms->gpex.mmio32.size; |
| 421 | } else { |
| 422 | lvms->gpex.mmio64.base = VIRT_PCI_MEM_BASE; |
| 423 | lvms->gpex.mmio64.size = VIRT_PCI_MEM_SIZE; |
| 424 | mmio_base = lvms->gpex.mmio64.base; |
| 425 | mmio_size = lvms->gpex.mmio64.size; |
| 426 | } |
| 427 | |
| 428 | /* Map only part size_ecam bytes of ECAM space */ |
| 429 | ecam_alias = g_new0(MemoryRegion, 1); |
| 430 | ecam_reg = sysbus_mmio_get_region(d, 0); |
| 431 | memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", |
| 432 | ecam_reg, 0, lvms->gpex.ecam.size); |
| 433 | memory_region_add_subregion(get_system_memory(), lvms->gpex.ecam.base, |
| 434 | ecam_alias); |
| 435 | |
| 436 | /* Map PCI mem space */ |
| 437 | mmio_alias = g_new0(MemoryRegion, 1); |
| 438 | mmio_reg = sysbus_mmio_get_region(d, 1); |
| 439 | memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", |
| 440 | mmio_reg, mmio_base, mmio_size); |
| 441 | memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); |
| 442 | if (lvms->highmem_mmio) { |
| 443 | /* Map high MMIO space */ |
| 444 | mmio_alias = g_new0(MemoryRegion, 1); |
| 445 | mmio_base = lvms->gpex.mmio64.base; |
| 446 | mmio_size = lvms->gpex.mmio64.size; |
| 447 | memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), |
| 448 | "pcie-mmio-high", mmio_reg, |
| 449 | mmio_base, mmio_size); |
| 450 | memory_region_add_subregion(get_system_memory(), mmio_base, |
| 451 | mmio_alias); |
| 452 | } |
| 453 | |
| 454 | /* Map PCI IO port space. */ |
| 455 | pio_alias = g_new0(MemoryRegion, 1); |
| 456 | pio_reg = sysbus_mmio_get_region(d, 2); |
| 457 | memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, |
| 458 | VIRT_PCI_IO_OFFSET, lvms->gpex.pio.size); |
| 459 | memory_region_add_subregion(get_system_memory(), lvms->gpex.pio.base, |
| 460 | pio_alias); |
| 461 | |
| 462 | for (i = 0; i < PCI_NUM_PINS; i++) { |
| 463 | irq = lvms->gpex.irq + i - VIRT_GSI_BASE; |
| 464 | sysbus_connect_irq(d, i, qdev_get_gpio_in(pch_pic, irq)); |
| 465 | gpex_set_irq_num(GPEX_HOST(gpex_dev), i, irq); |
| 466 | } |
| 467 | |
| 468 | /* |
| 469 | * Create uart fdt node in reverse order so that they appear |
| 470 | * in the finished device tree lowest address first |
| 471 | */ |
| 472 | for (i = VIRT_UART_COUNT; i-- > 0;) { |
| 473 | hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE; |
| 474 | irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE; |
| 475 | serial_mm_init(get_system_memory(), base, 0, |
| 476 | qdev_get_gpio_in(pch_pic, irq), |
| 477 | 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); |
| 478 | } |
| 479 | |
| 480 | /* Network init */ |
| 481 | pci_init_nic_devices(pci_bus, mc->default_nic); |
| 482 | |
| 483 | /* |
| 484 | * There are some invalid guest memory access. |
| 485 | * Create some unimplemented devices to emulate this. |
| 486 | */ |
| 487 | create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); |
| 488 | sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, |
| 489 | qdev_get_gpio_in(pch_pic, |
| 490 | VIRT_RTC_IRQ - VIRT_GSI_BASE)); |
| 491 | |
| 492 | /* acpi ged */ |
| 493 | lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); |
| 494 | /* platform bus */ |
| 495 | lvms->platform_bus_dev = create_platform_bus(pch_pic); |
| 496 | } |
| 497 | |
| 498 | static void virt_cpu_irq_init(LoongArchVirtMachineState *lvms) |
| 499 | { |
| 500 | int num; |
| 501 | MachineState *ms = MACHINE(lvms); |
| 502 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
| 503 | const CPUArchIdList *possible_cpus; |
| 504 | CPUState *cs; |
| 505 | |
| 506 | /* cpu nodes */ |
| 507 | possible_cpus = mc->possible_cpu_arch_ids(ms); |
| 508 | for (num = 0; num < possible_cpus->len; num++) { |
| 509 | cs = possible_cpus->cpus[num].cpu; |
| 510 | if (cs == NULL) { |
| 511 | continue; |
| 512 | } |
| 513 | |
| 514 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->ipi), DEVICE(cs), |
| 515 | &error_abort); |
| 516 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->extioi), DEVICE(cs), |
| 517 | &error_abort); |
| 518 | if (lvms->dintc) { |
| 519 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->dintc), DEVICE(cs), |
| 520 | &error_abort); |
| 521 | } |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | static void virt_irq_init(LoongArchVirtMachineState *lvms) |
| 526 | { |
| 527 | DeviceState *pch_pic, *pch_msi; |
| 528 | DeviceState *ipi, *extioi, *dintc; |
| 529 | SysBusDevice *d; |
| 530 | int i, start, num; |
| 531 | |
| 532 | /* |
| 533 | * Extended IRQ model. |
| 534 | * | |
| 535 | * +-----------+ +-------------|--------+ +-----------+ |
| 536 | * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer | |
| 537 | * +-----------+ +-------------|--------+ +-----------+ |
| 538 | * ^ | |
| 539 | * | |
| 540 | * +---------+ |
| 541 | * | EIOINTC | |
| 542 | * +---------+ |
| 543 | * ^ ^ |
| 544 | * | | |
| 545 | * +---------+ +---------+ |
| 546 | * | PCH-PIC | | PCH-MSI | |
| 547 | * +---------+ +---------+ |
| 548 | * ^ ^ ^ |
| 549 | * | | | |
| 550 | * +--------+ +---------+ +---------+ |
| 551 | * | UARTs | | Devices | | Devices | |
| 552 | * +--------+ +---------+ +---------+ |
| 553 | * |
| 554 | * Virt extended IRQ model. |
| 555 | * |
| 556 | * +-----+ +---------------+ +-------+ |
| 557 | * | IPI |--> | CPUINTC(0-255)| <-- | Timer | |
| 558 | * +-----+ +---------------+ +-------+ |
| 559 | * ^ |
| 560 | * | |
| 561 | * +-----------+ |
| 562 | * | V-EIOINTC | |
| 563 | * +-----------+ |
| 564 | * ^ ^ |
| 565 | * | | |
| 566 | * +---------+ +---------+ |
| 567 | * | PCH-PIC | | PCH-MSI | |
| 568 | * +---------+ +---------+ |
| 569 | * ^ ^ ^ |
| 570 | * | | | |
| 571 | * +--------+ +---------+ +---------+ |
| 572 | * | UARTs | | Devices | | Devices | |
| 573 | * +--------+ +---------+ +---------+ |
| 574 | * |
| 575 | * |
| 576 | * Advanced Extended IRQ model |
| 577 | * |
| 578 | * +-----+ +---------------------------------+ +-------+ |
| 579 | * | IPI | --> | CPUINTC | <-- | Timer | |
| 580 | * +-----+ +---------------------------------+ +-------+ |
| 581 | * ^ ^ ^ |
| 582 | * | | | |
| 583 | * +-------------+ +----------+ +---------+ +-------+ |
| 584 | * | EIOINTC | | DINTC | | LIOINTC | <-- | UARTs | |
| 585 | * +-------------+ +----------+ +---------+ +-------+ |
| 586 | * ^ ^ ^ |
| 587 | * | | | |
| 588 | * +---------+ +---------+ | |
| 589 | * | PCH-PIC | | PCH-MSI | | |
| 590 | * +---------+ +---------+ | |
| 591 | * ^ ^ ^ | |
| 592 | * | | | | |
| 593 | * +---------+ +---------+ +---------+ |
| 594 | * | Devices | | PCH-LPC | | Devices | |
| 595 | * +---------+ +---------+ +---------+ |
| 596 | * ^ |
| 597 | * | |
| 598 | * +---------+ |
| 599 | * | Devices | |
| 600 | * +---------+ |
| 601 | */ |
| 602 | |
| 603 | /* Create IPI device */ |
| 604 | ipi = qdev_new(TYPE_LOONGARCH_IPI); |
| 605 | lvms->ipi = ipi; |
| 606 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); |
| 607 | |
| 608 | /* Create DINTC device*/ |
| 609 | if (virt_has_dmsi(lvms)) { |
| 610 | dintc = qdev_new(TYPE_LOONGARCH_DINTC); |
| 611 | lvms->dintc = dintc; |
| 612 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dintc), &error_fatal); |
| 613 | sysbus_mmio_map(SYS_BUS_DEVICE(dintc), 0, VIRT_DINTC_BASE); |
| 614 | } |
| 615 | |
| 616 | /* Create EXTIOI device */ |
| 617 | extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); |
| 618 | lvms->extioi = extioi; |
| 619 | if (virt_is_veiointc_enabled(lvms)) { |
| 620 | qdev_prop_set_bit(extioi, "has-virtualization-extension", true); |
| 621 | } |
| 622 | sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); |
| 623 | |
| 624 | virt_cpu_irq_init(lvms); |
| 625 | pch_pic = qdev_new(TYPE_LOONGARCH_PIC); |
| 626 | num = VIRT_PCH_PIC_IRQ_NUM; |
| 627 | qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); |
| 628 | d = SYS_BUS_DEVICE(pch_pic); |
| 629 | sysbus_realize_and_unref(d, &error_fatal); |
| 630 | |
| 631 | pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); |
| 632 | start = num; |
| 633 | num = EXTIOI_IRQS - start; |
| 634 | qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); |
| 635 | qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); |
| 636 | d = SYS_BUS_DEVICE(pch_msi); |
| 637 | sysbus_realize_and_unref(d, &error_fatal); |
| 638 | sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); |
| 639 | |
| 640 | if (kvm_irqchip_in_kernel()) { |
| 641 | kvm_loongarch_init_irq_routing(); |
| 642 | } else { |
| 643 | /* IPI iocsr memory region */ |
| 644 | memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, |
| 645 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); |
| 646 | memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, |
| 647 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); |
| 648 | |
| 649 | /* EXTIOI iocsr memory region */ |
| 650 | memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, |
| 651 | sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); |
| 652 | if (virt_is_veiointc_enabled(lvms)) { |
| 653 | memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE, |
| 654 | sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); |
| 655 | } |
| 656 | |
| 657 | /* PCH_PIC memory region */ |
| 658 | memory_region_add_subregion(get_system_memory(), VIRT_PCH_REG_BASE, |
| 659 | sysbus_mmio_get_region(SYS_BUS_DEVICE(pch_pic), 0)); |
| 660 | |
| 661 | /* Connect pch_pic irqs to extioi */ |
| 662 | for (i = 0; i < VIRT_PCH_PIC_IRQ_NUM; i++) { |
| 663 | qdev_connect_gpio_out(DEVICE(pch_pic), i, |
| 664 | qdev_get_gpio_in(extioi, i)); |
| 665 | } |
| 666 | |
| 667 | for (i = VIRT_PCH_PIC_IRQ_NUM; i < EXTIOI_IRQS; i++) { |
| 668 | /* Connect pch_msi irqs to extioi */ |
| 669 | qdev_connect_gpio_out(DEVICE(pch_msi), i - VIRT_PCH_PIC_IRQ_NUM, |
| 670 | qdev_get_gpio_in(extioi, i)); |
| 671 | } |
| 672 | } |
| 673 | virt_devices_init(pch_pic, lvms); |
| 674 | } |
| 675 | |
| 676 | static void virt_firmware_init(LoongArchVirtMachineState *lvms) |
| 677 | { |
| 678 | char *filename = MACHINE(lvms)->firmware; |
| 679 | char *bios_name = NULL; |
| 680 | int bios_size, i; |
| 681 | BlockBackend *pflash_blk0; |
| 682 | MemoryRegion *mr; |
| 683 | |
| 684 | lvms->bios_loaded = false; |
| 685 | |
| 686 | /* Map legacy -drive if=pflash to machine properties */ |
| 687 | for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { |
| 688 | pflash_cfi01_legacy_drive(lvms->flash[i], |
| 689 | drive_get(IF_PFLASH, 0, i)); |
| 690 | } |
| 691 | |
| 692 | virt_flash_map(lvms, get_system_memory()); |
| 693 | |
| 694 | pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); |
| 695 | |
| 696 | if (pflash_blk0) { |
| 697 | if (filename) { |
| 698 | error_report("cannot use both '-bios' and '-drive if=pflash'" |
| 699 | "options at once"); |
| 700 | exit(1); |
| 701 | } |
| 702 | lvms->bios_loaded = true; |
| 703 | return; |
| 704 | } |
| 705 | |
| 706 | if (filename) { |
| 707 | bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); |
| 708 | if (!bios_name) { |
| 709 | error_report("Could not find ROM image '%s'", filename); |
| 710 | exit(1); |
| 711 | } |
| 712 | |
| 713 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); |
| 714 | bios_size = load_image_mr(bios_name, mr); |
| 715 | if (bios_size < 0) { |
| 716 | error_report("Could not load ROM image '%s'", bios_name); |
| 717 | exit(1); |
| 718 | } |
| 719 | g_free(bios_name); |
| 720 | lvms->bios_loaded = true; |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr, |
| 725 | uint64_t val, unsigned size, |
| 726 | MemTxAttrs attrs) |
| 727 | { |
| 728 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); |
| 729 | uint64_t features; |
| 730 | |
| 731 | switch (addr) { |
| 732 | case MISC_FUNC_REG: |
| 733 | if (kvm_irqchip_in_kernel()) { |
| 734 | return MEMTX_OK; |
| 735 | } |
| 736 | |
| 737 | if (!virt_is_veiointc_enabled(lvms)) { |
| 738 | return MEMTX_OK; |
| 739 | } |
| 740 | |
| 741 | if (virt_has_dmsi(lvms) && val & BIT_ULL(IOCSRM_DMSI_EN)) { |
| 742 | lvms->misc_status |= BIT_ULL(IOCSRM_DMSI_EN); |
| 743 | } |
| 744 | |
| 745 | features = address_space_ldl_le(&lvms->as_iocsr, |
| 746 | EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, |
| 747 | attrs, NULL); |
| 748 | if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) { |
| 749 | features |= BIT(EXTIOI_ENABLE); |
| 750 | } |
| 751 | if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) { |
| 752 | features |= BIT(EXTIOI_ENABLE_INT_ENCODE); |
| 753 | } |
| 754 | |
| 755 | address_space_stl_le(&lvms->as_iocsr, |
| 756 | EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, |
| 757 | features, attrs, NULL); |
| 758 | break; |
| 759 | case VERSION_REG: |
| 760 | case FEATURE_REG: |
| 761 | case VENDOR_REG: |
| 762 | case CPUNAME_REG: |
| 763 | break; |
| 764 | default: |
| 765 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented IOCSR 0x%" HWADDR_PRIx "\n", |
| 766 | __func__, addr); |
| 767 | break; |
| 768 | } |
| 769 | |
| 770 | return MEMTX_OK; |
| 771 | } |
| 772 | |
| 773 | static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, |
| 774 | uint64_t *data, |
| 775 | unsigned size, MemTxAttrs attrs) |
| 776 | { |
| 777 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); |
| 778 | uint64_t ret = 0; |
| 779 | int features; |
| 780 | CPULoongArchState *env; |
| 781 | |
| 782 | env = &LOONGARCH_CPU(first_cpu)->env; |
| 783 | switch (addr) { |
| 784 | case VERSION_REG: |
| 785 | ret = 0x11ULL; |
| 786 | break; |
| 787 | case FEATURE_REG: |
| 788 | ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); |
| 789 | if (virt_has_dmsi(lvms)) { |
| 790 | ret |= BIT(IOCSRF_DMSI); |
| 791 | } |
| 792 | if (kvm_enabled()) { |
| 793 | ret |= BIT(IOCSRF_VM); |
| 794 | } |
| 795 | break; |
| 796 | case VENDOR_REG: |
| 797 | ret = env->vendor_id; |
| 798 | break; |
| 799 | case CPUNAME_REG: |
| 800 | ret = env->cpu_id; |
| 801 | break; |
| 802 | case MISC_FUNC_REG: |
| 803 | if (kvm_irqchip_in_kernel()) { |
| 804 | return MEMTX_OK; |
| 805 | } |
| 806 | |
| 807 | if (!virt_is_veiointc_enabled(lvms)) { |
| 808 | ret |= BIT_ULL(IOCSRM_EXTIOI_EN); |
| 809 | break; |
| 810 | } |
| 811 | |
| 812 | features = address_space_ldl_le(&lvms->as_iocsr, |
| 813 | EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, |
| 814 | attrs, NULL); |
| 815 | if (features & BIT(EXTIOI_ENABLE)) { |
| 816 | ret |= BIT_ULL(IOCSRM_EXTIOI_EN); |
| 817 | } |
| 818 | if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { |
| 819 | ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); |
| 820 | } |
| 821 | if (virt_has_dmsi(lvms) && |
| 822 | (lvms->misc_status & BIT_ULL(IOCSRM_DMSI_EN))) { |
| 823 | ret |= BIT_ULL(IOCSRM_DMSI_EN); |
| 824 | } |
| 825 | break; |
| 826 | default: |
| 827 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented IOCSR 0x%" HWADDR_PRIx "\n", |
| 828 | __func__, addr); |
| 829 | break; |
| 830 | } |
| 831 | |
| 832 | *data = ret; |
| 833 | return MEMTX_OK; |
| 834 | } |
| 835 | |
| 836 | static const MemoryRegionOps virt_iocsr_misc_ops = { |
| 837 | .read_with_attrs = virt_iocsr_misc_read, |
| 838 | .write_with_attrs = virt_iocsr_misc_write, |
| 839 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 840 | .valid = { |
| 841 | .min_access_size = 4, |
| 842 | .max_access_size = 8, |
| 843 | }, |
| 844 | .impl = { |
| 845 | .min_access_size = 8, |
| 846 | .max_access_size = 8, |
| 847 | }, |
| 848 | }; |
| 849 | |
| 850 | static void fw_cfg_add_memory(MachineState *ms) |
| 851 | { |
| 852 | hwaddr base, size, ram_size, gap; |
| 853 | int nb_numa_nodes, nodes; |
| 854 | NodeInfo *numa_info; |
| 855 | |
| 856 | ram_size = ms->ram_size; |
| 857 | base = VIRT_LOWMEM_BASE; |
| 858 | gap = VIRT_LOWMEM_SIZE; |
| 859 | nodes = nb_numa_nodes = ms->numa_state->num_nodes; |
| 860 | numa_info = ms->numa_state->nodes; |
| 861 | if (!nodes) { |
| 862 | nodes = 1; |
| 863 | } |
| 864 | |
| 865 | /* add fw_cfg memory map of node0 */ |
| 866 | if (nb_numa_nodes) { |
| 867 | size = numa_info[0].node_mem; |
| 868 | } else { |
| 869 | size = ram_size; |
| 870 | } |
| 871 | |
| 872 | if (size >= gap) { |
| 873 | memmap_add_entry(ms, base, gap, 1); |
| 874 | size -= gap; |
| 875 | base = VIRT_HIGHMEM_BASE; |
| 876 | } |
| 877 | |
| 878 | if (size) { |
| 879 | memmap_add_entry(ms, base, size, 1); |
| 880 | base += size; |
| 881 | } |
| 882 | |
| 883 | if (nodes < 2) { |
| 884 | return; |
| 885 | } |
| 886 | |
| 887 | /* add fw_cfg memory map of other nodes */ |
| 888 | if (numa_info[0].node_mem < gap && ram_size > gap) { |
| 889 | /* |
| 890 | * memory map for the maining nodes splited into two part |
| 891 | * lowram: [base, +(gap - numa_info[0].node_mem)) |
| 892 | * highram: [VIRT_HIGHMEM_BASE, +(ram_size - gap)) |
| 893 | */ |
| 894 | memmap_add_entry(ms, base, gap - numa_info[0].node_mem, 1); |
| 895 | size = ram_size - gap; |
| 896 | base = VIRT_HIGHMEM_BASE; |
| 897 | } else { |
| 898 | size = ram_size - numa_info[0].node_mem; |
| 899 | } |
| 900 | |
| 901 | if (size) { |
| 902 | memmap_add_entry(ms, base, size, 1); |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | static void virt_check_dmsi(MachineState *machine) |
| 907 | { |
| 908 | LoongArchCPU *cpu; |
| 909 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); |
| 910 | |
| 911 | cpu = LOONGARCH_CPU(first_cpu); |
| 912 | if (lvms->dmsi == ON_OFF_AUTO_AUTO) { |
| 913 | if (cpu->msgint != ON_OFF_AUTO_OFF) { |
| 914 | lvms->misc_feature = BIT(IOCSRF_DMSI); |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | if (lvms->dmsi == ON_OFF_AUTO_ON && cpu->msgint == ON_OFF_AUTO_OFF) { |
| 919 | error_report("Fail to enable dmsi , cpu msgint is off " |
| 920 | "pleass add cpu feature mesgint=on."); |
| 921 | exit(EXIT_FAILURE); |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | static void virt_init(MachineState *machine) |
| 926 | { |
| 927 | const char *cpu_model = machine->cpu_type; |
| 928 | MemoryRegion *address_space_mem = get_system_memory(); |
| 929 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); |
| 930 | int i; |
| 931 | hwaddr base, size, ram_size = machine->ram_size; |
| 932 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 933 | Object *cpuobj; |
| 934 | uint64_t phys_addr_mask = 0; |
| 935 | |
| 936 | if (!cpu_model) { |
| 937 | cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); |
| 938 | } |
| 939 | |
| 940 | /* Create IOCSR space */ |
| 941 | memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, |
| 942 | machine, "iocsr", UINT64_MAX); |
| 943 | address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); |
| 944 | memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), |
| 945 | &virt_iocsr_misc_ops, |
| 946 | machine, "iocsr_misc", 0x428); |
| 947 | memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); |
| 948 | |
| 949 | /* Init CPUs */ |
| 950 | mc->possible_cpu_arch_ids(machine); |
| 951 | for (i = 0; i < machine->smp.cpus; i++) { |
| 952 | cpuobj = object_new(machine->cpu_type); |
| 953 | if (cpuobj == NULL) { |
| 954 | error_report("Fail to create object with type %s ", |
| 955 | machine->cpu_type); |
| 956 | exit(EXIT_FAILURE); |
| 957 | } |
| 958 | qdev_realize_and_unref(DEVICE(cpuobj), NULL, &error_fatal); |
| 959 | } |
| 960 | virt_check_dmsi(machine); |
| 961 | fw_cfg_add_memory(machine); |
| 962 | |
| 963 | /* Node0 memory */ |
| 964 | size = ram_size; |
| 965 | base = VIRT_LOWMEM_BASE; |
| 966 | if (size > VIRT_LOWMEM_SIZE) { |
| 967 | size = VIRT_LOWMEM_SIZE; |
| 968 | } |
| 969 | |
| 970 | memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram", |
| 971 | machine->ram, base, size); |
| 972 | memory_region_add_subregion(address_space_mem, base, &lvms->lowmem); |
| 973 | base += size; |
| 974 | if (ram_size - size) { |
| 975 | base = VIRT_HIGHMEM_BASE; |
| 976 | memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram", |
| 977 | machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size); |
| 978 | memory_region_add_subregion(address_space_mem, base, &lvms->highmem); |
| 979 | base += ram_size - size; |
| 980 | } |
| 981 | |
| 982 | /* initialize device memory address space */ |
| 983 | if (machine->ram_size < machine->maxram_size) { |
| 984 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
| 985 | |
| 986 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
| 987 | error_report("unsupported amount of memory slots: %"PRIu64, |
| 988 | machine->ram_slots); |
| 989 | exit(EXIT_FAILURE); |
| 990 | } |
| 991 | |
| 992 | if (QEMU_ALIGN_UP(machine->maxram_size, |
| 993 | TARGET_PAGE_SIZE) != machine->maxram_size) { |
| 994 | error_report("maximum memory size must by aligned to multiple of " |
| 995 | "%d bytes", TARGET_PAGE_SIZE); |
| 996 | exit(EXIT_FAILURE); |
| 997 | } |
| 998 | machine_memory_devices_init(machine, base, device_mem_size); |
| 999 | base += device_mem_size; |
| 1000 | } |
| 1001 | |
| 1002 | lvms->ram_end = base; |
| 1003 | /* load the BIOS image. */ |
| 1004 | virt_firmware_init(lvms); |
| 1005 | |
| 1006 | /* fw_cfg init */ |
| 1007 | lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); |
| 1008 | rom_set_fw(lvms->fw_cfg); |
| 1009 | if (lvms->fw_cfg != NULL) { |
| 1010 | fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", |
| 1011 | lvms->memmap_table, |
| 1012 | sizeof(struct memmap_entry) * lvms->memmap_entries); |
| 1013 | } |
| 1014 | |
| 1015 | /* Initialize the IO interrupt subsystem */ |
| 1016 | virt_irq_init(lvms); |
| 1017 | lvms->machine_done.notify = virt_done; |
| 1018 | qemu_add_machine_init_done_notifier(&lvms->machine_done); |
| 1019 | /* connect powerdown request */ |
| 1020 | lvms->powerdown_notifier.notify = virt_powerdown_req; |
| 1021 | qemu_register_powerdown_notifier(&lvms->powerdown_notifier); |
| 1022 | |
| 1023 | lvms->bootinfo.ram_size = ram_size; |
| 1024 | phys_addr_mask = loongarch_palen_mask(&LOONGARCH_CPU(first_cpu)->env); |
| 1025 | loongarch_load_kernel(machine, &lvms->bootinfo, phys_addr_mask); |
| 1026 | } |
| 1027 | |
| 1028 | static void virt_get_acpi(Object *obj, Visitor *v, const char *name, |
| 1029 | void *opaque, Error **errp) |
| 1030 | { |
| 1031 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1032 | OnOffAuto acpi = lvms->acpi; |
| 1033 | |
| 1034 | visit_type_OnOffAuto(v, name, &acpi, errp); |
| 1035 | } |
| 1036 | |
| 1037 | static void virt_set_acpi(Object *obj, Visitor *v, const char *name, |
| 1038 | void *opaque, Error **errp) |
| 1039 | { |
| 1040 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1041 | |
| 1042 | visit_type_OnOffAuto(v, name, &lvms->acpi, errp); |
| 1043 | } |
| 1044 | |
| 1045 | static char *virt_get_oem_id(Object *obj, Error **errp) |
| 1046 | { |
| 1047 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1048 | |
| 1049 | return g_strdup(lvms->oem_id); |
| 1050 | } |
| 1051 | |
| 1052 | static void virt_set_oem_id(Object *obj, const char *value, Error **errp) |
| 1053 | { |
| 1054 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1055 | size_t len = strlen(value); |
| 1056 | |
| 1057 | if (len > 6) { |
| 1058 | error_setg(errp, |
| 1059 | "User specified oem-id value is bigger than 6 bytes in size"); |
| 1060 | return; |
| 1061 | } |
| 1062 | |
| 1063 | strncpy(lvms->oem_id, value, 6); |
| 1064 | } |
| 1065 | |
| 1066 | static char *virt_get_oem_table_id(Object *obj, Error **errp) |
| 1067 | { |
| 1068 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1069 | |
| 1070 | return g_strdup(lvms->oem_table_id); |
| 1071 | } |
| 1072 | |
| 1073 | static void virt_set_oem_table_id(Object *obj, const char *value, |
| 1074 | Error **errp) |
| 1075 | { |
| 1076 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1077 | size_t len = strlen(value); |
| 1078 | |
| 1079 | if (len > 8) { |
| 1080 | error_setg(errp, |
| 1081 | "User specified oem-table-id value is bigger than 8 bytes in size"); |
| 1082 | return; |
| 1083 | } |
| 1084 | strncpy(lvms->oem_table_id, value, 8); |
| 1085 | } |
| 1086 | |
| 1087 | static void virt_initfn(Object *obj) |
| 1088 | { |
| 1089 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1090 | |
| 1091 | if (tcg_enabled()) { |
| 1092 | lvms->veiointc = ON_OFF_AUTO_OFF; |
| 1093 | } |
| 1094 | |
| 1095 | lvms->dmsi = ON_OFF_AUTO_AUTO; |
| 1096 | lvms->acpi = ON_OFF_AUTO_AUTO; |
| 1097 | lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); |
| 1098 | lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); |
| 1099 | virt_flash_create(lvms); |
| 1100 | } |
| 1101 | |
| 1102 | static void virt_get_topo_from_index(MachineState *ms, |
| 1103 | LoongArchCPUTopo *topo, int index) |
| 1104 | { |
| 1105 | topo->socket_id = index / (ms->smp.cores * ms->smp.threads); |
| 1106 | topo->core_id = index / ms->smp.threads % ms->smp.cores; |
| 1107 | topo->thread_id = index % ms->smp.threads; |
| 1108 | } |
| 1109 | |
| 1110 | static unsigned int topo_align_up(unsigned int count) |
| 1111 | { |
| 1112 | g_assert(count >= 1); |
| 1113 | count -= 1; |
| 1114 | return BIT(count ? 32 - clz32(count) : 0); |
| 1115 | } |
| 1116 | |
| 1117 | /* |
| 1118 | * LoongArch Reference Manual Vol1, Chapter 7.4.12 CPU Identity |
| 1119 | * For CPU architecture, bit0 .. bit8 is valid for CPU id, max cpuid is 512 |
| 1120 | * However for IPI/Eiointc interrupt controller, max supported cpu id for |
| 1121 | * irq routingis 256 |
| 1122 | * |
| 1123 | * Here max cpu id is 256 for virt machine |
| 1124 | */ |
| 1125 | static int virt_get_arch_id_from_topo(MachineState *ms, LoongArchCPUTopo *topo) |
| 1126 | { |
| 1127 | int arch_id, threads, cores, sockets; |
| 1128 | |
| 1129 | threads = topo_align_up(ms->smp.threads); |
| 1130 | cores = topo_align_up(ms->smp.cores); |
| 1131 | sockets = topo_align_up(ms->smp.sockets); |
| 1132 | if ((threads * cores * sockets) > 256) { |
| 1133 | error_report("Exceeding max cpuid 256 with sockets[%d] cores[%d]" |
| 1134 | " threads[%d]", ms->smp.sockets, ms->smp.cores, |
| 1135 | ms->smp.threads); |
| 1136 | exit(1); |
| 1137 | } |
| 1138 | |
| 1139 | arch_id = topo->thread_id + topo->core_id * threads; |
| 1140 | arch_id += topo->socket_id * threads * cores; |
| 1141 | return arch_id; |
| 1142 | } |
| 1143 | |
| 1144 | /* Find cpu slot in machine->possible_cpus by arch_id */ |
| 1145 | static CPUArchId *virt_find_cpu_slot(MachineState *ms, int arch_id) |
| 1146 | { |
| 1147 | int n; |
| 1148 | for (n = 0; n < ms->possible_cpus->len; n++) { |
| 1149 | if (ms->possible_cpus->cpus[n].arch_id == arch_id) { |
| 1150 | return &ms->possible_cpus->cpus[n]; |
| 1151 | } |
| 1152 | } |
| 1153 | |
| 1154 | return NULL; |
| 1155 | } |
| 1156 | |
| 1157 | /* Find cpu slot for cold-plut CPU object where cpu is NULL */ |
| 1158 | static CPUArchId *virt_find_empty_cpu_slot(MachineState *ms) |
| 1159 | { |
| 1160 | int n; |
| 1161 | for (n = 0; n < ms->possible_cpus->len; n++) { |
| 1162 | if (ms->possible_cpus->cpus[n].cpu == NULL) { |
| 1163 | return &ms->possible_cpus->cpus[n]; |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | return NULL; |
| 1168 | } |
| 1169 | |
| 1170 | static void virt_cpu_pre_plug(HotplugHandler *hotplug_dev, |
| 1171 | DeviceState *dev, Error **errp) |
| 1172 | { |
| 1173 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1174 | MachineState *ms = MACHINE(OBJECT(hotplug_dev)); |
| 1175 | LoongArchCPU *cpu = LOONGARCH_CPU(dev); |
| 1176 | CPUState *cs = CPU(dev); |
| 1177 | CPUArchId *cpu_slot; |
| 1178 | LoongArchCPUTopo topo; |
| 1179 | int arch_id; |
| 1180 | |
| 1181 | if (lvms->acpi_ged) { |
| 1182 | if ((cpu->thread_id < 0) || (cpu->thread_id >= ms->smp.threads)) { |
| 1183 | error_setg(errp, |
| 1184 | "Invalid thread-id %u specified, must be in range 1:%u", |
| 1185 | cpu->thread_id, ms->smp.threads - 1); |
| 1186 | return; |
| 1187 | } |
| 1188 | |
| 1189 | if ((cpu->core_id < 0) || (cpu->core_id >= ms->smp.cores)) { |
| 1190 | error_setg(errp, |
| 1191 | "Invalid core-id %u specified, must be in range 1:%u", |
| 1192 | cpu->core_id, ms->smp.cores - 1); |
| 1193 | return; |
| 1194 | } |
| 1195 | |
| 1196 | if ((cpu->socket_id < 0) || (cpu->socket_id >= ms->smp.sockets)) { |
| 1197 | error_setg(errp, |
| 1198 | "Invalid socket-id %u specified, must be in range 1:%u", |
| 1199 | cpu->socket_id, ms->smp.sockets - 1); |
| 1200 | return; |
| 1201 | } |
| 1202 | |
| 1203 | topo.socket_id = cpu->socket_id; |
| 1204 | topo.core_id = cpu->core_id; |
| 1205 | topo.thread_id = cpu->thread_id; |
| 1206 | arch_id = virt_get_arch_id_from_topo(ms, &topo); |
| 1207 | cpu_slot = virt_find_cpu_slot(ms, arch_id); |
| 1208 | if (CPU(cpu_slot->cpu)) { |
| 1209 | error_setg(errp, |
| 1210 | "cpu(id%d=%d:%d:%d) with arch-id %" PRIu64 " exists", |
| 1211 | cs->cpu_index, cpu->socket_id, cpu->core_id, |
| 1212 | cpu->thread_id, cpu_slot->arch_id); |
| 1213 | return; |
| 1214 | } |
| 1215 | } else { |
| 1216 | /* For cold-add cpu, find empty cpu slot */ |
| 1217 | cpu_slot = virt_find_empty_cpu_slot(ms); |
| 1218 | topo.socket_id = cpu_slot->props.socket_id; |
| 1219 | topo.core_id = cpu_slot->props.core_id; |
| 1220 | topo.thread_id = cpu_slot->props.thread_id; |
| 1221 | object_property_set_int(OBJECT(dev), "socket-id", topo.socket_id, NULL); |
| 1222 | object_property_set_int(OBJECT(dev), "core-id", topo.core_id, NULL); |
| 1223 | object_property_set_int(OBJECT(dev), "thread-id", topo.thread_id, NULL); |
| 1224 | } |
| 1225 | |
| 1226 | cpu->env.address_space_iocsr = &lvms->as_iocsr; |
| 1227 | cpu->phy_id = cpu_slot->arch_id; |
| 1228 | cs->cpu_index = cpu_slot - ms->possible_cpus->cpus; |
| 1229 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
| 1230 | } |
| 1231 | |
| 1232 | static void virt_cpu_unplug_request(HotplugHandler *hotplug_dev, |
| 1233 | DeviceState *dev, Error **errp) |
| 1234 | { |
| 1235 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1236 | LoongArchCPU *cpu = LOONGARCH_CPU(dev); |
| 1237 | CPUState *cs = CPU(dev); |
| 1238 | |
| 1239 | if (cs->cpu_index == 0) { |
| 1240 | error_setg(errp, "hot-unplug of boot cpu(id%d=%d:%d:%d) not supported", |
| 1241 | cs->cpu_index, cpu->socket_id, |
| 1242 | cpu->core_id, cpu->thread_id); |
| 1243 | return; |
| 1244 | } |
| 1245 | |
| 1246 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); |
| 1247 | } |
| 1248 | |
| 1249 | static void virt_cpu_unplug(HotplugHandler *hotplug_dev, |
| 1250 | DeviceState *dev, Error **errp) |
| 1251 | { |
| 1252 | CPUArchId *cpu_slot; |
| 1253 | LoongArchCPU *cpu = LOONGARCH_CPU(dev); |
| 1254 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1255 | |
| 1256 | /* Notify ipi and extioi irqchip to remove interrupt routing to CPU */ |
| 1257 | hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->ipi), dev, &error_abort); |
| 1258 | hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->extioi), dev, &error_abort); |
| 1259 | if (lvms->dintc) { |
| 1260 | hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->dintc), dev, &error_abort); |
| 1261 | } |
| 1262 | |
| 1263 | /* Notify acpi ged CPU removed */ |
| 1264 | hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, &error_abort); |
| 1265 | |
| 1266 | qemu_unregister_resettable(OBJECT(dev)); |
| 1267 | cpu_slot = virt_find_cpu_slot(MACHINE(lvms), cpu->phy_id); |
| 1268 | cpu_slot->cpu = NULL; |
| 1269 | } |
| 1270 | |
| 1271 | static void virt_cpu_plug(HotplugHandler *hotplug_dev, |
| 1272 | DeviceState *dev, Error **errp) |
| 1273 | { |
| 1274 | CPUArchId *cpu_slot; |
| 1275 | LoongArchCPU *cpu = LOONGARCH_CPU(dev); |
| 1276 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1277 | |
| 1278 | if (lvms->ipi) { |
| 1279 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->ipi), dev, &error_abort); |
| 1280 | } |
| 1281 | |
| 1282 | if (lvms->extioi) { |
| 1283 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->extioi), dev, &error_abort); |
| 1284 | } |
| 1285 | |
| 1286 | if (lvms->dintc) { |
| 1287 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->dintc), dev, &error_abort); |
| 1288 | } |
| 1289 | |
| 1290 | if (lvms->acpi_ged) { |
| 1291 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, |
| 1292 | &error_abort); |
| 1293 | } |
| 1294 | |
| 1295 | qemu_register_resettable(OBJECT(dev)); |
| 1296 | cpu_slot = virt_find_cpu_slot(MACHINE(lvms), cpu->phy_id); |
| 1297 | cpu_slot->cpu = CPU(dev); |
| 1298 | } |
| 1299 | |
| 1300 | static bool memhp_type_supported(DeviceState *dev) |
| 1301 | { |
| 1302 | /* we only support pc dimm now */ |
| 1303 | return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && |
| 1304 | !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
| 1305 | } |
| 1306 | |
| 1307 | static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 1308 | Error **errp) |
| 1309 | { |
| 1310 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); |
| 1311 | } |
| 1312 | |
| 1313 | static void virt_device_pre_plug(HotplugHandler *hotplug_dev, |
| 1314 | DeviceState *dev, Error **errp) |
| 1315 | { |
| 1316 | if (memhp_type_supported(dev)) { |
| 1317 | virt_mem_pre_plug(hotplug_dev, dev, errp); |
| 1318 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) { |
| 1319 | virt_cpu_pre_plug(hotplug_dev, dev, errp); |
| 1320 | } |
| 1321 | } |
| 1322 | |
| 1323 | static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, |
| 1324 | DeviceState *dev, Error **errp) |
| 1325 | { |
| 1326 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1327 | |
| 1328 | /* the acpi ged is always exist */ |
| 1329 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, |
| 1330 | errp); |
| 1331 | } |
| 1332 | |
| 1333 | static void virt_device_unplug_request(HotplugHandler *hotplug_dev, |
| 1334 | DeviceState *dev, Error **errp) |
| 1335 | { |
| 1336 | if (memhp_type_supported(dev)) { |
| 1337 | virt_mem_unplug_request(hotplug_dev, dev, errp); |
| 1338 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) { |
| 1339 | virt_cpu_unplug_request(hotplug_dev, dev, errp); |
| 1340 | } |
| 1341 | } |
| 1342 | |
| 1343 | static void virt_mem_unplug(HotplugHandler *hotplug_dev, |
| 1344 | DeviceState *dev, Error **errp) |
| 1345 | { |
| 1346 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1347 | |
| 1348 | hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); |
| 1349 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); |
| 1350 | qdev_unrealize(dev); |
| 1351 | } |
| 1352 | |
| 1353 | static void virt_device_unplug(HotplugHandler *hotplug_dev, |
| 1354 | DeviceState *dev, Error **errp) |
| 1355 | { |
| 1356 | if (memhp_type_supported(dev)) { |
| 1357 | virt_mem_unplug(hotplug_dev, dev, errp); |
| 1358 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) { |
| 1359 | virt_cpu_unplug(hotplug_dev, dev, errp); |
| 1360 | } |
| 1361 | } |
| 1362 | |
| 1363 | static void virt_mem_plug(HotplugHandler *hotplug_dev, |
| 1364 | DeviceState *dev, Error **errp) |
| 1365 | { |
| 1366 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1367 | |
| 1368 | pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); |
| 1369 | hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), |
| 1370 | dev, &error_abort); |
| 1371 | } |
| 1372 | |
| 1373 | static void virt_device_plug_cb(HotplugHandler *hotplug_dev, |
| 1374 | DeviceState *dev, Error **errp) |
| 1375 | { |
| 1376 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); |
| 1377 | MachineClass *mc = MACHINE_GET_CLASS(lvms); |
| 1378 | PlatformBusDevice *pbus; |
| 1379 | |
| 1380 | if (device_is_dynamic_sysbus(mc, dev)) { |
| 1381 | if (lvms->platform_bus_dev) { |
| 1382 | pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); |
| 1383 | platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); |
| 1384 | } |
| 1385 | } else if (memhp_type_supported(dev)) { |
| 1386 | virt_mem_plug(hotplug_dev, dev, errp); |
| 1387 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) { |
| 1388 | virt_cpu_plug(hotplug_dev, dev, errp); |
| 1389 | } |
| 1390 | } |
| 1391 | |
| 1392 | static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, |
| 1393 | DeviceState *dev) |
| 1394 | { |
| 1395 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 1396 | |
| 1397 | if (device_is_dynamic_sysbus(mc, dev) || |
| 1398 | object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU) || |
| 1399 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || |
| 1400 | memhp_type_supported(dev)) { |
| 1401 | return HOTPLUG_HANDLER(machine); |
| 1402 | } |
| 1403 | return NULL; |
| 1404 | } |
| 1405 | |
| 1406 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
| 1407 | { |
| 1408 | int n, arch_id; |
| 1409 | unsigned int max_cpus = ms->smp.max_cpus; |
| 1410 | LoongArchCPUTopo topo; |
| 1411 | |
| 1412 | if (ms->possible_cpus) { |
| 1413 | assert(ms->possible_cpus->len == max_cpus); |
| 1414 | return ms->possible_cpus; |
| 1415 | } |
| 1416 | |
| 1417 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
| 1418 | sizeof(CPUArchId) * max_cpus); |
| 1419 | ms->possible_cpus->len = max_cpus; |
| 1420 | for (n = 0; n < ms->possible_cpus->len; n++) { |
| 1421 | virt_get_topo_from_index(ms, &topo, n); |
| 1422 | arch_id = virt_get_arch_id_from_topo(ms, &topo); |
| 1423 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
| 1424 | ms->possible_cpus->cpus[n].arch_id = arch_id; |
| 1425 | ms->possible_cpus->cpus[n].vcpus_count = 1; |
| 1426 | ms->possible_cpus->cpus[n].props.has_socket_id = true; |
| 1427 | ms->possible_cpus->cpus[n].props.socket_id = topo.socket_id; |
| 1428 | ms->possible_cpus->cpus[n].props.has_core_id = true; |
| 1429 | ms->possible_cpus->cpus[n].props.core_id = topo.core_id; |
| 1430 | ms->possible_cpus->cpus[n].props.has_thread_id = true; |
| 1431 | ms->possible_cpus->cpus[n].props.thread_id = topo.thread_id; |
| 1432 | } |
| 1433 | return ms->possible_cpus; |
| 1434 | } |
| 1435 | |
| 1436 | static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, |
| 1437 | unsigned cpu_index) |
| 1438 | { |
| 1439 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
| 1440 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); |
| 1441 | |
| 1442 | assert(cpu_index < possible_cpus->len); |
| 1443 | return possible_cpus->cpus[cpu_index].props; |
| 1444 | } |
| 1445 | |
| 1446 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) |
| 1447 | { |
| 1448 | int64_t socket_id; |
| 1449 | |
| 1450 | if (ms->numa_state->num_nodes) { |
| 1451 | socket_id = ms->possible_cpus->cpus[idx].props.socket_id; |
| 1452 | return socket_id % ms->numa_state->num_nodes; |
| 1453 | } else { |
| 1454 | return 0; |
| 1455 | } |
| 1456 | } |
| 1457 | |
| 1458 | static void virt_class_init(ObjectClass *oc, const void *data) |
| 1459 | { |
| 1460 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1461 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
| 1462 | |
| 1463 | mc->init = virt_init; |
| 1464 | mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); |
| 1465 | mc->default_ram_id = "loongarch.ram"; |
| 1466 | mc->desc = "QEMU LoongArch Virtual Machine"; |
| 1467 | mc->max_cpus = LOONGARCH_MAX_CPUS; |
| 1468 | mc->default_kernel_irqchip_split = false; |
| 1469 | mc->block_default_type = IF_VIRTIO; |
| 1470 | mc->default_boot_order = "c"; |
| 1471 | mc->no_cdrom = 1; |
| 1472 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; |
| 1473 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; |
| 1474 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; |
| 1475 | mc->numa_mem_supported = true; |
| 1476 | mc->auto_enable_numa_with_memhp = true; |
| 1477 | mc->auto_enable_numa_with_memdev = true; |
| 1478 | mc->has_hotpluggable_cpus = true; |
| 1479 | mc->get_hotplug_handler = virt_get_hotplug_handler; |
| 1480 | mc->default_nic = "virtio-net-pci"; |
| 1481 | hc->plug = virt_device_plug_cb; |
| 1482 | hc->pre_plug = virt_device_pre_plug; |
| 1483 | hc->unplug_request = virt_device_unplug_request; |
| 1484 | hc->unplug = virt_device_unplug; |
| 1485 | |
| 1486 | object_class_property_add(oc, "acpi", "OnOffAuto", |
| 1487 | virt_get_acpi, virt_set_acpi, |
| 1488 | NULL, NULL); |
| 1489 | object_class_property_set_description(oc, "acpi", |
| 1490 | "Enable ACPI"); |
| 1491 | object_class_property_add(oc, "v-eiointc", "OnOffAuto", |
| 1492 | virt_get_veiointc, virt_set_veiointc, |
| 1493 | NULL, NULL); |
| 1494 | object_class_property_set_description(oc, "v-eiointc", |
| 1495 | "Enable Virt Extend I/O Interrupt Controller."); |
| 1496 | object_class_property_add(oc, "dmsi", "OnOffAuto", |
| 1497 | virt_get_dmsi, virt_set_dmsi, NULL, NULL); |
| 1498 | object_class_property_set_description(oc, "dmsi", |
| 1499 | "Enable direct Message-interrupts Controller."); |
| 1500 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); |
| 1501 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); |
| 1502 | #ifdef CONFIG_TPM |
| 1503 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); |
| 1504 | #endif |
| 1505 | object_class_property_add_str(oc, "x-oem-id", |
| 1506 | virt_get_oem_id, |
| 1507 | virt_set_oem_id); |
| 1508 | object_class_property_set_description(oc, "x-oem-id", |
| 1509 | "Override the default value of field OEMID " |
| 1510 | "in ACPI table header." |
| 1511 | "The string may be up to 6 bytes in size"); |
| 1512 | |
| 1513 | |
| 1514 | object_class_property_add_str(oc, "x-oem-table-id", |
| 1515 | virt_get_oem_table_id, |
| 1516 | virt_set_oem_table_id); |
| 1517 | object_class_property_set_description(oc, "x-oem-table-id", |
| 1518 | "Override the default value of field OEM Table ID " |
| 1519 | "in ACPI table header." |
| 1520 | "The string may be up to 8 bytes in size"); |
| 1521 | |
| 1522 | object_class_property_add_bool(oc, "highmem-mmio", |
| 1523 | virt_get_highmem_mmio, |
| 1524 | virt_set_highmem_mmio); |
| 1525 | object_class_property_set_description(oc, "highmem-mmio", |
| 1526 | "Set on/off to enable/disable high " |
| 1527 | "memory region for PCI MMIO"); |
| 1528 | object_class_property_add(oc, "highmem-mmio-size", "size", |
| 1529 | virt_get_highmem_mmio_size, |
| 1530 | virt_set_highmem_mmio_size, |
| 1531 | NULL, NULL); |
| 1532 | object_class_property_set_description(oc, "highmem-mmio-size", |
| 1533 | "Set the high memory region size " |
| 1534 | "for PCI MMIO"); |
| 1535 | } |
| 1536 | |
| 1537 | #define DEFINE_VIRT_MACHINE_VERSION(latest, ...) \ |
| 1538 | static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \ |
| 1539 | ObjectClass *oc, \ |
| 1540 | const void *data) \ |
| 1541 | { \ |
| 1542 | MachineClass *mc = MACHINE_CLASS(oc); \ |
| 1543 | MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ |
| 1544 | mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " LoongArch Virtual Machine"; \ |
| 1545 | MACHINE_VER_DEPRECATION(__VA_ARGS__); \ |
| 1546 | if (latest) { \ |
| 1547 | mc->alias = "virt"; \ |
| 1548 | mc->is_default = true; \ |
| 1549 | } \ |
| 1550 | } \ |
| 1551 | static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \ |
| 1552 | { \ |
| 1553 | .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ |
| 1554 | .parent = TYPE_LOONGARCH_VIRT_MACHINE, \ |
| 1555 | .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ |
| 1556 | }; \ |
| 1557 | static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ |
| 1558 | { \ |
| 1559 | MACHINE_VER_DELETION(__VA_ARGS__); \ |
| 1560 | type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \ |
| 1561 | } \ |
| 1562 | type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__)); |
| 1563 | |
| 1564 | #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ |
| 1565 | DEFINE_VIRT_MACHINE_VERSION(true, major, minor) |
| 1566 | #define DEFINE_VIRT_MACHINE(major, minor) \ |
| 1567 | DEFINE_VIRT_MACHINE_VERSION(false, major, minor) |
| 1568 | |
| 1569 | static void virt_instance_finalize(Object *obj) |
| 1570 | { |
| 1571 | LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); |
| 1572 | |
| 1573 | for (int i = 0; i < ARRAY_SIZE(lvms->flash); i++) { |
| 1574 | if (lvms->flash[i] && !qdev_is_realized(DEVICE(lvms->flash[i]))) { |
| 1575 | object_unref(OBJECT(lvms->flash[i])); |
| 1576 | } |
| 1577 | } |
| 1578 | g_free(lvms->oem_id); |
| 1579 | g_free(lvms->oem_table_id); |
| 1580 | } |
| 1581 | |
| 1582 | static const TypeInfo virt_machine_info = { |
| 1583 | .name = TYPE_LOONGARCH_VIRT_MACHINE, |
| 1584 | .parent = TYPE_MACHINE, |
| 1585 | .abstract = true, |
| 1586 | .instance_size = sizeof(LoongArchVirtMachineState), |
| 1587 | .class_init = virt_class_init, |
| 1588 | .instance_init = virt_initfn, |
| 1589 | .instance_finalize = virt_instance_finalize, |
| 1590 | .interfaces = (InterfaceInfo[]) { |
| 1591 | { TYPE_HOTPLUG_HANDLER }, |
| 1592 | { } |
| 1593 | }, |
| 1594 | }; |
| 1595 | |
| 1596 | static void machvirt_machine_init(void) |
| 1597 | { |
| 1598 | type_register_static(&virt_machine_info); |
| 1599 | } |
| 1600 | |
| 1601 | type_init(machvirt_machine_init); |
| 1602 | |
| 1603 | static void virt_machine_11_2_options(MachineClass *mc) |
| 1604 | { |
| 1605 | } |
| 1606 | DEFINE_VIRT_MACHINE_AS_LATEST(11, 2) |
| 1607 | |
| 1608 | static void virt_machine_11_1_options(MachineClass *mc) |
| 1609 | { |
| 1610 | virt_machine_11_2_options(mc); |
| 1611 | compat_props_add(mc->compat_props, hw_compat_11_1, hw_compat_11_1_len); |
| 1612 | } |
| 1613 | DEFINE_VIRT_MACHINE(11, 1) |