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1 /*
2 * NeXT Cube System Driver
3 *
4 * Copyright (c) 2011 Bryce Lanham
5 * Copyright (c) 2024 Mark Cave-Ayland
6 *
7 * This code is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation; either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13 #include "qemu/osdep.h"
14 #include "exec/hwaddr.h"
15 #include "exec/cpu-common.h"
16 #include "exec/cpu-interrupt.h"
17 #include "system/physmem.h"
18 #include "system/system.h"
19 #include "system/qtest.h"
20 #include "hw/core/irq.h"
21 #include "hw/m68k/next-cube.h"
22 #include "hw/core/boards.h"
23 #include "hw/core/loader.h"
24 #include "hw/scsi/esp.h"
25 #include "hw/core/sysbus.h"
26 #include "qom/object.h"
27 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
28 #include "hw/block/fdc.h"
29 #include "hw/misc/empty_slot.h"
30 #include "hw/core/qdev-properties.h"
31 #include "qapi/error.h"
32 #include "qemu/error-report.h"
33 #include "ui/console.h"
34 #include "target/m68k/cpu.h"
35 #include "migration/vmstate.h"
36
37 /* #define DEBUG_NEXT */
38 #ifdef DEBUG_NEXT
39 #define DPRINTF(fmt, ...) \
40 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
41 #else
42 #define DPRINTF(fmt, ...) do { } while (0)
43 #endif
44
45 #define ENTRY 0x0100001e
46 #define RAM_SIZE 0x4000000
47 #define ROM_FILE "Rev_2.5_v66.bin"
48
49
50 #define TYPE_NEXT_RTC "next-rtc"
51 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC)
52
53 struct NeXTRTC {
54 SysBusDevice parent_obj;
55
56 int8_t phase;
57 uint8_t ram[32];
58 uint8_t command;
59 uint8_t value;
60 uint8_t status;
61 uint8_t control;
62 uint8_t retval;
63
64 qemu_irq data_out_irq;
65 qemu_irq power_irq;
66 };
67
68 #define TYPE_NEXT_SCSI "next-scsi"
69 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI)
70
71 /* NeXT SCSI Controller */
72 struct NeXTSCSI {
73 SysBusDevice parent_obj;
74
75 MemoryRegion scsi_mem;
76
77 SysBusESPState sysbus_esp;
78
79 MemoryRegion scsi_csr_mem;
80 uint8_t scsi_csr_1;
81 uint8_t scsi_csr_2;
82 };
83
84 #define TYPE_NEXT_PC "next-pc"
85 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC)
86
87 /* NeXT Peripheral Controller */
88 struct NeXTPC {
89 SysBusDevice parent_obj;
90
91 M68kCPU *cpu;
92
93 MemoryRegion floppy_mem;
94 MemoryRegion timer_mem;
95 MemoryRegion dummyen_mem;
96 MemoryRegion mmiomem;
97 MemoryRegion scrmem;
98
99 uint32_t scr1;
100 uint32_t scr2;
101 uint32_t old_scr2;
102 uint32_t int_mask;
103 uint32_t int_status;
104 uint32_t led;
105
106 NeXTSCSI next_scsi;
107
108 qemu_irq scsi_reset;
109 qemu_irq scsi_dma;
110
111 ESCCState escc;
112
113 NeXTRTC rtc;
114 qemu_irq rtc_data_irq;
115 qemu_irq rtc_cmd_reset_irq;
116 };
117
118 typedef struct next_dma {
119 uint32_t csr;
120
121 uint32_t saved_next;
122 uint32_t saved_limit;
123 uint32_t saved_start;
124 uint32_t saved_stop;
125
126 uint32_t next;
127 uint32_t limit;
128 uint32_t start;
129 uint32_t stop;
130
131 uint32_t next_initbuf;
132 uint32_t size;
133 } next_dma;
134
135 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
136 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE)
137
138 struct NeXTState {
139 MachineState parent;
140
141 MemoryRegion rom;
142 MemoryRegion rom2;
143 MemoryRegion dmamem;
144 MemoryRegion bmapm1;
145 MemoryRegion bmapm2;
146
147 next_dma dma[10];
148 };
149
150 /* Thanks to NeXT forums for this */
151 /*
152 static const uint8_t rtc_ram3[32] = {
153 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
155 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
157 };
158 */
159 static const uint8_t rtc_ram2[32] = {
160 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
161 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
162 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
163 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
164 };
165
166 #define SCR2_RTCLK 0x2
167 #define SCR2_RTDATA 0x4
168 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
169
170 static void next_scr2_led_update(NeXTPC *s)
171 {
172 if (s->scr2 & 0x1) {
173 DPRINTF("fault!\n");
174 s->led++;
175 if (s->led == 10) {
176 DPRINTF("LED flashing, possible fault!\n");
177 s->led = 0;
178 }
179 }
180 }
181
182 static void next_scr2_rtc_update(NeXTPC *s)
183 {
184 uint8_t old_scr2_rtc, scr2_rtc;
185
186 old_scr2_rtc = extract32(s->old_scr2, 8, 8);
187 scr2_rtc = extract32(s->scr2, 8, 8);
188
189 if (scr2_rtc & 0x1) {
190 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */
191 /* If we are in going down clock... do something */
192 if (((old_scr2_rtc & SCR2_RTCLK) != (scr2_rtc & SCR2_RTCLK)) &&
193 ((scr2_rtc & SCR2_RTCLK) == 0)) {
194 if (scr2_rtc & SCR2_RTDATA) {
195 qemu_irq_raise(s->rtc_data_irq);
196 } else {
197 qemu_irq_lower(s->rtc_data_irq);
198 }
199 }
200 } else {
201 /* else end or abort */
202 qemu_irq_raise(s->rtc_cmd_reset_irq);
203 }
204 }
205
206 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size)
207 {
208 NeXTPC *s = NEXT_PC(opaque);
209 uint64_t val;
210
211 switch (addr) {
212 case 0x2000: /* 0x2007000 */
213 /* DPRINTF("Read INT status: %x\n", s->int_status); */
214 val = s->int_status;
215 break;
216
217 case 0x2800: /* 0x2007800 */
218 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask);
219 val = s->int_mask;
220 break;
221
222 case 0x7000 ... 0x7003: /* 0x200c000 */
223 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3,
224 size << 3);
225 break;
226
227 case 0x8000 ... 0x8003: /* 0x200d000 */
228 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3,
229 size << 3);
230 break;
231
232 default:
233 val = 0;
234 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size);
235 break;
236 }
237
238 return val;
239 }
240
241 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val,
242 unsigned size)
243 {
244 NeXTPC *s = NEXT_PC(opaque);
245
246 switch (addr) {
247 case 0x2000: /* 0x2007000 */
248 DPRINTF("INT Status old: %x new: %x\n", s->int_status,
249 (unsigned int)val);
250 s->int_status = val;
251 break;
252
253 case 0x2800: /* 0x2007800 */
254 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val);
255 s->int_mask = val;
256 break;
257
258 case 0x7000 ... 0x7003: /* 0x200c000 */
259 DPRINTF("SCR1 Write: %x\n", (unsigned int)val);
260 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3,
261 size << 3, val);
262 break;
263
264 case 0x8000 ... 0x8003: /* 0x200d000 */
265 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3,
266 size << 3, val);
267 next_scr2_led_update(s);
268 next_scr2_rtc_update(s);
269 s->old_scr2 = s->scr2;
270 break;
271
272 default:
273 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr,
274 (unsigned int)val, size);
275 }
276 }
277
278 static const MemoryRegionOps next_mmio_ops = {
279 .read = next_mmio_read,
280 .write = next_mmio_write,
281 .valid.min_access_size = 1,
282 .valid.max_access_size = 4,
283 .endianness = DEVICE_BIG_ENDIAN,
284 };
285
286 #define SCSICSR_ENABLE 0x01
287 #define SCSICSR_RESET 0x02 /* reset scsi dma */
288 #define SCSICSR_FIFOFL 0x04
289 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
290 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
291 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
292
293 #define NEXTDMA_SCSI(x) (0x10 + x)
294 #define NEXTDMA_FD(x) (0x10 + x)
295 #define NEXTDMA_ENTX(x) (0x110 + x)
296 #define NEXTDMA_ENRX(x) (0x150 + x)
297 #define NEXTDMA_CSR 0x0
298 #define NEXTDMA_NEXT 0x4000
299 #define NEXTDMA_LIMIT 0x4004
300 #define NEXTDMA_START 0x4008
301 #define NEXTDMA_STOP 0x400c
302 #define NEXTDMA_NEXT_INIT 0x4200
303 #define NEXTDMA_SIZE 0x4204
304
305 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val,
306 unsigned int size)
307 {
308 NeXTState *next_state = NEXT_MACHINE(opaque);
309
310 switch (addr) {
311 case NEXTDMA_ENRX(NEXTDMA_CSR):
312 if (val & DMA_DEV2M) {
313 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M;
314 }
315
316 if (val & DMA_SETENABLE) {
317 /* DPRINTF("SCSI DMA ENABLE\n"); */
318 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE;
319 }
320 if (val & DMA_SETSUPDATE) {
321 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE;
322 }
323 if (val & DMA_CLRCOMPLETE) {
324 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE;
325 }
326
327 if (val & DMA_RESET) {
328 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
329 DMA_ENABLE | DMA_DEV2M);
330 }
331 /* DPRINTF("RXCSR \tWrite: %x\n",value); */
332 break;
333
334 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
335 next_state->dma[NEXTDMA_ENRX].next_initbuf = val;
336 break;
337
338 case NEXTDMA_ENRX(NEXTDMA_NEXT):
339 next_state->dma[NEXTDMA_ENRX].next = val;
340 break;
341
342 case NEXTDMA_ENRX(NEXTDMA_LIMIT):
343 next_state->dma[NEXTDMA_ENRX].limit = val;
344 break;
345
346 case NEXTDMA_SCSI(NEXTDMA_CSR):
347 if (val & DMA_DEV2M) {
348 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M;
349 }
350 if (val & DMA_SETENABLE) {
351 /* DPRINTF("SCSI DMA ENABLE\n"); */
352 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE;
353 }
354 if (val & DMA_SETSUPDATE) {
355 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE;
356 }
357 if (val & DMA_CLRCOMPLETE) {
358 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE;
359 }
360
361 if (val & DMA_RESET) {
362 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
363 DMA_ENABLE | DMA_DEV2M);
364 /* DPRINTF("SCSI DMA RESET\n"); */
365 }
366 /* DPRINTF("RXCSR \tWrite: %x\n",value); */
367 break;
368
369 case NEXTDMA_SCSI(NEXTDMA_NEXT):
370 next_state->dma[NEXTDMA_SCSI].next = val;
371 break;
372
373 case NEXTDMA_SCSI(NEXTDMA_LIMIT):
374 next_state->dma[NEXTDMA_SCSI].limit = val;
375 break;
376
377 case NEXTDMA_SCSI(NEXTDMA_START):
378 next_state->dma[NEXTDMA_SCSI].start = val;
379 break;
380
381 case NEXTDMA_SCSI(NEXTDMA_STOP):
382 next_state->dma[NEXTDMA_SCSI].stop = val;
383 break;
384
385 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
386 next_state->dma[NEXTDMA_SCSI].next_initbuf = val;
387 break;
388
389 default:
390 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val);
391 }
392 }
393
394 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size)
395 {
396 NeXTState *next_state = NEXT_MACHINE(opaque);
397 uint64_t val;
398
399 switch (addr) {
400 case NEXTDMA_SCSI(NEXTDMA_CSR):
401 DPRINTF("SCSI DMA CSR READ\n");
402 val = next_state->dma[NEXTDMA_SCSI].csr;
403 break;
404
405 case NEXTDMA_ENRX(NEXTDMA_CSR):
406 val = next_state->dma[NEXTDMA_ENRX].csr;
407 break;
408
409 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
410 val = next_state->dma[NEXTDMA_ENRX].next_initbuf;
411 break;
412
413 case NEXTDMA_ENRX(NEXTDMA_NEXT):
414 val = next_state->dma[NEXTDMA_ENRX].next;
415 break;
416
417 case NEXTDMA_ENRX(NEXTDMA_LIMIT):
418 val = next_state->dma[NEXTDMA_ENRX].limit;
419 break;
420
421 case NEXTDMA_SCSI(NEXTDMA_NEXT):
422 val = next_state->dma[NEXTDMA_SCSI].next;
423 break;
424
425 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
426 val = next_state->dma[NEXTDMA_SCSI].next_initbuf;
427 break;
428
429 case NEXTDMA_SCSI(NEXTDMA_LIMIT):
430 val = next_state->dma[NEXTDMA_SCSI].limit;
431 break;
432
433 case NEXTDMA_SCSI(NEXTDMA_START):
434 val = next_state->dma[NEXTDMA_SCSI].start;
435 break;
436
437 case NEXTDMA_SCSI(NEXTDMA_STOP):
438 val = next_state->dma[NEXTDMA_SCSI].stop;
439 break;
440
441 default:
442 DPRINTF("DMA read @ %x\n", (unsigned int)addr);
443 val = 0;
444 }
445
446 /*
447 * once the csr's are done, subtract 0x3FEC from the addr, and that will
448 * normalize the upper registers
449 */
450
451 return val;
452 }
453
454 static const MemoryRegionOps next_dma_ops = {
455 .read = next_dma_read,
456 .write = next_dma_write,
457 .impl.min_access_size = 4,
458 .valid.min_access_size = 4,
459 .valid.max_access_size = 4,
460 .endianness = DEVICE_BIG_ENDIAN,
461 };
462
463 static void next_irq(void *opaque, int number, int level)
464 {
465 NeXTPC *s = NEXT_PC(opaque);
466 M68kCPU *cpu = s->cpu;
467 int shift = 0;
468
469 /* first switch sets interrupt status */
470 /* DPRINTF("IRQ %i\n",number); */
471 switch (number) {
472 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
473 case NEXT_FD_I:
474 shift = 7;
475 break;
476 case NEXT_KBD_I:
477 shift = 3;
478 break;
479 case NEXT_PWR_I:
480 shift = 2;
481 break;
482 case NEXT_ENRX_I:
483 shift = 9;
484 break;
485 case NEXT_ENTX_I:
486 shift = 10;
487 break;
488 case NEXT_SCSI_I:
489 shift = 12;
490 break;
491 case NEXT_CLK_I:
492 shift = 5;
493 break;
494
495 /* level 5 - scc (serial) */
496 case NEXT_SCC_I:
497 shift = 17;
498 break;
499
500 /* level 6 - audio etherrx/tx dma */
501 case NEXT_ENTX_DMA_I:
502 shift = 28;
503 break;
504 case NEXT_ENRX_DMA_I:
505 shift = 27;
506 break;
507 case NEXT_SCSI_DMA_I:
508 shift = 26;
509 break;
510 case NEXT_SND_I:
511 shift = 23;
512 break;
513 case NEXT_SCC_DMA_I:
514 shift = 21;
515 break;
516
517 }
518 /*
519 * this HAS to be wrong, the interrupt handlers in mach and together
520 * int_status and int_mask and return if there is a hit
521 */
522 if (s->int_mask & (1 << shift)) {
523 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc);
524 /* return; */
525 }
526
527 /* second switch triggers the correct interrupt */
528 if (level) {
529 s->int_status |= 1 << shift;
530
531 switch (number) {
532 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
533 case NEXT_FD_I:
534 case NEXT_KBD_I:
535 case NEXT_PWR_I:
536 case NEXT_ENRX_I:
537 case NEXT_ENTX_I:
538 case NEXT_SCSI_I:
539 case NEXT_CLK_I:
540 m68k_set_irq_level(cpu, 3, 27);
541 break;
542
543 /* level 5 - scc (serial) */
544 case NEXT_SCC_I:
545 m68k_set_irq_level(cpu, 5, 29);
546 break;
547
548 /* level 6 - audio etherrx/tx dma */
549 case NEXT_ENTX_DMA_I:
550 case NEXT_ENRX_DMA_I:
551 case NEXT_SCSI_DMA_I:
552 case NEXT_SND_I:
553 case NEXT_SCC_DMA_I:
554 m68k_set_irq_level(cpu, 6, 30);
555 break;
556 }
557 } else {
558 s->int_status &= ~(1 << shift);
559 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
560 }
561 }
562
563 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type)
564 {
565 uint32_t base_addr;
566 int irq = 0;
567 uint8_t align = 16;
568 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine());
569
570 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) {
571 align = 32;
572 }
573 /* Most DMA is supposedly 16 byte aligned */
574 if ((size % align) != 0) {
575 size -= size % align;
576 size += align;
577 }
578
579 /*
580 * prom sets the dma start using initbuf while the bootloader uses next
581 * so we check to see if initbuf is 0
582 */
583 if (next_state->dma[type].next_initbuf == 0) {
584 base_addr = next_state->dma[type].next;
585 } else {
586 base_addr = next_state->dma[type].next_initbuf;
587 }
588
589 physical_memory_write(base_addr, buf, size);
590
591 next_state->dma[type].next_initbuf = 0;
592
593 /* saved limit is checked to calculate packet size by both, rom and netbsd */
594 next_state->dma[type].saved_limit = (next_state->dma[type].next + size);
595 next_state->dma[type].saved_next = (next_state->dma[type].next);
596
597 /*
598 * 32 bytes under savedbase seems to be some kind of register
599 * of which the purpose is unknown as of yet
600 */
601 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */
602
603 if (!(next_state->dma[type].csr & DMA_SUPDATE)) {
604 next_state->dma[type].next = next_state->dma[type].start;
605 next_state->dma[type].limit = next_state->dma[type].stop;
606 }
607
608 /* Set dma registers and raise an irq */
609 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */
610
611 switch (type) {
612 case NEXTDMA_SCSI:
613 irq = NEXT_SCSI_DMA_I;
614 break;
615 }
616
617 next_irq(opaque, irq, 1);
618 next_irq(opaque, irq, 0);
619 }
620
621 static void nextscsi_read(void *opaque, uint8_t *buf, int len)
622 {
623 DPRINTF("SCSI READ: %x\n", len);
624 abort();
625 }
626
627 static void nextscsi_write(void *opaque, uint8_t *buf, int size)
628 {
629 DPRINTF("SCSI WRITE: %i\n", size);
630 nextdma_write(opaque, buf, size, NEXTDMA_SCSI);
631 }
632
633 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val,
634 unsigned size)
635 {
636 NeXTSCSI *s = NEXT_SCSI(opaque);
637 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi));
638
639 switch (addr) {
640 case 0:
641 if (val & SCSICSR_FIFOFL) {
642 DPRINTF("SCSICSR FIFO Flush\n");
643 /* will have to add another irq to the esp if this is needed */
644 /* esp_puflush_fifo(esp_g); */
645 }
646
647 if (val & SCSICSR_ENABLE) {
648 DPRINTF("SCSICSR Enable\n");
649 /*
650 * qemu_irq_raise(s->scsi_dma);
651 * s->scsi_csr_1 = 0xc0;
652 * s->scsi_csr_1 |= 0x1;
653 * qemu_irq_pulse(s->scsi_dma);
654 */
655 }
656 /*
657 * else
658 * s->scsi_csr_1 &= ~SCSICSR_ENABLE;
659 */
660
661 if (val & SCSICSR_RESET) {
662 DPRINTF("SCSICSR Reset\n");
663 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
664 qemu_irq_raise(pc->scsi_reset);
665 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1);
666 qemu_irq_lower(pc->scsi_reset);
667 }
668 if (val & SCSICSR_DMADIR) {
669 DPRINTF("SCSICSR DMAdir\n");
670 }
671 if (val & SCSICSR_CPUDMA) {
672 DPRINTF("SCSICSR CPUDMA\n");
673 /* qemu_irq_raise(s->scsi_dma); */
674 pc->int_status |= 0x4000000;
675 } else {
676 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */
677 pc->int_status &= ~(0x4000000);
678 /* qemu_irq_lower(s->scsi_dma); */
679 }
680 if (val & SCSICSR_INTMASK) {
681 DPRINTF("SCSICSR INTMASK\n");
682 /*
683 * int_mask &= ~0x1000;
684 * s->scsi_csr_1 |= val;
685 * s->scsi_csr_1 &= ~SCSICSR_INTMASK;
686 * if (s->scsi_queued) {
687 * s->scsi_queued = 0;
688 * next_irq(s, NEXT_SCSI_I, level);
689 * }
690 */
691 } else {
692 /* int_mask |= 0x1000; */
693 }
694 if (val & 0x80) {
695 /* int_mask |= 0x1000; */
696 /* s->scsi_csr_1 |= 0x80; */
697 }
698 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val);
699 s->scsi_csr_1 = val;
700 break;
701
702 case 1:
703 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val);
704 s->scsi_csr_2 = val;
705 break;
706
707 default:
708 g_assert_not_reached();
709 }
710 }
711
712 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size)
713 {
714 NeXTSCSI *s = NEXT_SCSI(opaque);
715 uint64_t val;
716
717 switch (addr) {
718 case 0:
719 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1);
720 val = s->scsi_csr_1;
721 break;
722
723 case 1:
724 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2);
725 val = s->scsi_csr_2;
726 break;
727
728 default:
729 g_assert_not_reached();
730 }
731
732 return val;
733 }
734
735 static const MemoryRegionOps next_scsi_csr_ops = {
736 .read = next_scsi_csr_read,
737 .write = next_scsi_csr_write,
738 .valid.min_access_size = 1,
739 .valid.max_access_size = 1,
740 .endianness = DEVICE_BIG_ENDIAN,
741 };
742
743 static void next_scsi_init(Object *obj)
744 {
745 NeXTSCSI *s = NEXT_SCSI(obj);
746 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
747
748 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP);
749
750 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops,
751 s, "csrs", 2);
752
753 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40);
754 sysbus_init_mmio(sbd, &s->scsi_mem);
755 }
756
757 static void next_scsi_realize(DeviceState *dev, Error **errp)
758 {
759 NeXTSCSI *s = NEXT_SCSI(dev);
760 SysBusESPState *sysbus_esp;
761 SysBusDevice *sbd;
762 ESPState *esp;
763 NeXTPC *pcdev;
764
765 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi));
766
767 /* ESP */
768 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp);
769 esp = &sysbus_esp->esp;
770 esp->dma_memory_read = nextscsi_read;
771 esp->dma_memory_write = nextscsi_write;
772 esp->dma_opaque = pcdev;
773 sysbus_esp->it_shift = 0;
774 esp->dma_enabled = 1;
775 sbd = SYS_BUS_DEVICE(sysbus_esp);
776 if (!sysbus_realize(sbd, errp)) {
777 return;
778 }
779 memory_region_add_subregion(&s->scsi_mem, 0x0,
780 sysbus_mmio_get_region(sbd, 0));
781
782 /* SCSI CSRs */
783 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem);
784
785 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus);
786 }
787
788 static const VMStateDescription next_scsi_vmstate = {
789 .name = "next-scsi",
790 .version_id = 0,
791 .minimum_version_id = 0,
792 .fields = (const VMStateField[]) {
793 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI),
794 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI),
795 VMSTATE_END_OF_LIST()
796 },
797 };
798
799 static void next_scsi_class_init(ObjectClass *klass, const void *data)
800 {
801 DeviceClass *dc = DEVICE_CLASS(klass);
802
803 dc->desc = "NeXT SCSI Controller";
804 dc->realize = next_scsi_realize;
805 dc->vmsd = &next_scsi_vmstate;
806 }
807
808 static const TypeInfo next_scsi_info = {
809 .name = TYPE_NEXT_SCSI,
810 .parent = TYPE_SYS_BUS_DEVICE,
811 .instance_init = next_scsi_init,
812 .instance_size = sizeof(NeXTSCSI),
813 .class_init = next_scsi_class_init,
814 };
815
816 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val,
817 unsigned size)
818 {
819 switch (addr) {
820 case 0:
821 DPRINTF("FDCSR Write: %"PRIx64 "\n", val);
822 if (val == 0x0) {
823 /* qemu_irq_raise(s->fd_irq[0]); */
824 }
825 break;
826
827 default:
828 g_assert_not_reached();
829 }
830 }
831
832 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size)
833 {
834 uint64_t val;
835
836 switch (addr) {
837 case 0:
838 DPRINTF("FD read @ %x\n", (unsigned int)addr);
839 val = 0x40 | 0x04 | 0x2 | 0x1;
840 break;
841
842 default:
843 g_assert_not_reached();
844 }
845
846 return val;
847 }
848
849 static const MemoryRegionOps next_floppy_ops = {
850 .read = next_floppy_read,
851 .write = next_floppy_write,
852 .valid.min_access_size = 1,
853 .valid.max_access_size = 4,
854 .endianness = DEVICE_BIG_ENDIAN,
855 };
856
857 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val,
858 unsigned size)
859 {
860 switch (addr) {
861 case 0 ... 3:
862 /* Hardware timer latch - not implemented yet */
863 break;
864
865 default:
866 g_assert_not_reached();
867 }
868 }
869
870 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size)
871 {
872 uint64_t val;
873
874 switch (addr) {
875 case 0 ... 3:
876 /*
877 * These 4 registers are the hardware timer, not sure which register
878 * is the latch instead of data, but no problems so far.
879 *
880 * Hack: We need to have the LSB change consistently to make it work
881 */
882 val = extract32(clock(), (4 - addr - size) << 3,
883 size << 3);
884 break;
885
886 default:
887 g_assert_not_reached();
888 }
889
890 return val;
891 }
892
893 static const MemoryRegionOps next_timer_ops = {
894 .read = next_timer_read,
895 .write = next_timer_write,
896 .valid.min_access_size = 1,
897 .valid.max_access_size = 4,
898 .endianness = DEVICE_BIG_ENDIAN,
899 };
900
901 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val,
902 unsigned size)
903 {
904 /* Do nothing */
905 }
906
907 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size)
908 {
909 uint64_t val;
910
911 switch (addr) {
912 case 0:
913 /* For now return dummy byte to allow the Ethernet test to timeout */
914 val = 0xff;
915 break;
916
917 default:
918 val = 0;
919 }
920
921 return val;
922 }
923
924 static const MemoryRegionOps next_dummy_en_ops = {
925 .read = next_dummy_en_read,
926 .write = next_dummy_en_write,
927 .valid.min_access_size = 1,
928 .valid.max_access_size = 4,
929 .endianness = DEVICE_BIG_ENDIAN,
930 };
931
932 static bool next_rtc_cmd_is_write(uint8_t cmd)
933 {
934 return (cmd >= 0x80 && cmd <= 0x9f) ||
935 (cmd == 0xb1);
936 }
937
938 static void next_rtc_data_in_irq(void *opaque, int n, int level)
939 {
940 NeXTRTC *rtc = NEXT_RTC(opaque);
941
942 if (rtc->phase < 8) {
943 rtc->command = (rtc->command << 1) | level;
944
945 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) {
946 if (rtc->command <= 0x1f) {
947 /* RAM registers */
948 rtc->retval = rtc->ram[rtc->command];
949 }
950 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) {
951 /* RTC */
952 time_t time_h = time(NULL);
953 struct tm *info = localtime(&time_h);
954 rtc->retval = 0;
955
956 switch (rtc->command) {
957 case 0x20:
958 rtc->retval = SCR2_TOBCD(info->tm_sec);
959 break;
960 case 0x21:
961 rtc->retval = SCR2_TOBCD(info->tm_min);
962 break;
963 case 0x22:
964 rtc->retval = SCR2_TOBCD(info->tm_hour);
965 break;
966 case 0x24:
967 rtc->retval = SCR2_TOBCD(info->tm_mday);
968 break;
969 case 0x25:
970 rtc->retval = SCR2_TOBCD((info->tm_mon + 1));
971 break;
972 case 0x26:
973 rtc->retval = SCR2_TOBCD((info->tm_year - 100));
974 break;
975 }
976 }
977 if (rtc->command == 0x30) {
978 /* read the status 0x30 */
979 rtc->retval = rtc->status;
980 }
981 if (rtc->command == 0x31) {
982 /* read the control 0x31 */
983 rtc->retval = rtc->control;
984 }
985 }
986 }
987 if (rtc->phase >= 8 && rtc->phase < 16) {
988 if (next_rtc_cmd_is_write(rtc->command)) {
989 /* Shift in value to write */
990 rtc->value = (rtc->value << 1) | level;
991 } else {
992 /* Shift out value to read */
993 if (rtc->retval & (0x80 >> (rtc->phase - 8))) {
994 qemu_irq_raise(rtc->data_out_irq);
995 } else {
996 qemu_irq_lower(rtc->data_out_irq);
997 }
998 }
999 }
1000
1001 rtc->phase++;
1002 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) {
1003 if (rtc->command >= 0x80 && rtc->command <= 0x9f) {
1004 /* RAM registers */
1005 rtc->ram[rtc->command - 0x80] = rtc->value;
1006 }
1007 if (rtc->command == 0xb1) {
1008 /* write to 0x30 register */
1009 if (rtc->value & 0x04) {
1010 /* clear FTU */
1011 rtc->status = rtc->status & (~0x18);
1012 qemu_irq_lower(rtc->power_irq);
1013 }
1014 }
1015 }
1016 }
1017
1018 static void next_rtc_cmd_reset_irq(void *opaque, int n, int level)
1019 {
1020 NeXTRTC *rtc = NEXT_RTC(opaque);
1021
1022 if (level) {
1023 rtc->phase = 0;
1024 rtc->command = 0;
1025 rtc->value = 0;
1026 }
1027 }
1028
1029 static void next_rtc_reset_hold(Object *obj, ResetType type)
1030 {
1031 NeXTRTC *rtc = NEXT_RTC(obj);
1032
1033 rtc->status = 0x90;
1034
1035 /* Load RTC RAM - TODO: provide possibility to load contents from file */
1036 memcpy(rtc->ram, rtc_ram2, 32);
1037 }
1038
1039 static void next_rtc_init(Object *obj)
1040 {
1041 NeXTRTC *rtc = NEXT_RTC(obj);
1042
1043 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq,
1044 "rtc-data-in", 1);
1045 qdev_init_gpio_out_named(DEVICE(obj), &rtc->data_out_irq,
1046 "rtc-data-out", 1);
1047 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_cmd_reset_irq,
1048 "rtc-cmd-reset", 1);
1049 qdev_init_gpio_out_named(DEVICE(obj), &rtc->power_irq,
1050 "rtc-power-out", 1);
1051 }
1052
1053 static const VMStateDescription next_rtc_vmstate = {
1054 .name = "next-rtc",
1055 .version_id = 3,
1056 .minimum_version_id = 3,
1057 .fields = (const VMStateField[]) {
1058 VMSTATE_INT8(phase, NeXTRTC),
1059 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32),
1060 VMSTATE_UINT8(command, NeXTRTC),
1061 VMSTATE_UINT8(value, NeXTRTC),
1062 VMSTATE_UINT8(status, NeXTRTC),
1063 VMSTATE_UINT8(control, NeXTRTC),
1064 VMSTATE_UINT8(retval, NeXTRTC),
1065 VMSTATE_END_OF_LIST()
1066 },
1067 };
1068
1069 static void next_rtc_class_init(ObjectClass *klass, const void *data)
1070 {
1071 DeviceClass *dc = DEVICE_CLASS(klass);
1072 ResettableClass *rc = RESETTABLE_CLASS(klass);
1073
1074 dc->desc = "NeXT RTC";
1075 dc->vmsd = &next_rtc_vmstate;
1076 rc->phases.hold = next_rtc_reset_hold;
1077 }
1078
1079 static const TypeInfo next_rtc_info = {
1080 .name = TYPE_NEXT_RTC,
1081 .parent = TYPE_SYS_BUS_DEVICE,
1082 .instance_init = next_rtc_init,
1083 .instance_size = sizeof(NeXTRTC),
1084 .class_init = next_rtc_class_init,
1085 };
1086
1087 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level)
1088 {
1089 NeXTPC *s = NEXT_PC(opaque);
1090 uint8_t scr2_2 = extract32(s->scr2, 8, 8);
1091
1092 if (level) {
1093 scr2_2 |= SCR2_RTDATA;
1094 } else {
1095 scr2_2 &= ~SCR2_RTDATA;
1096 }
1097
1098 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2);
1099 }
1100
1101 static void next_pc_reset_hold(Object *obj, ResetType type)
1102 {
1103 NeXTPC *s = NEXT_PC(obj);
1104
1105 /* Set internal registers to initial values */
1106 /* 0x0000XX00 << vital bits */
1107 s->scr1 = 0x00011102;
1108 s->scr2 = 0x00ff0c80;
1109 s->old_scr2 = s->scr2;
1110 }
1111
1112 static void next_pc_realize(DeviceState *dev, Error **errp)
1113 {
1114 NeXTPC *s = NEXT_PC(dev);
1115 SysBusDevice *sbd;
1116 DeviceState *d;
1117
1118 /* SCSI */
1119 sbd = SYS_BUS_DEVICE(&s->next_scsi);
1120 if (!sysbus_realize(sbd, errp)) {
1121 return;
1122 }
1123
1124 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp"));
1125 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0,
1126 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I));
1127
1128 s->scsi_reset = qdev_get_gpio_in(d, 0);
1129 s->scsi_dma = qdev_get_gpio_in(d, 1);
1130
1131 /* ESCC */
1132 d = DEVICE(&s->escc);
1133 qdev_prop_set_uint32(d, "disabled", 0);
1134 qdev_prop_set_uint32(d, "frequency", 9600 * 384);
1135 qdev_prop_set_uint32(d, "it_shift", 0);
1136 qdev_prop_set_bit(d, "bit_swap", true);
1137 qdev_prop_set_chr(d, "chrB", serial_hd(1));
1138 qdev_prop_set_chr(d, "chrA", serial_hd(0));
1139 qdev_prop_set_uint32(d, "chnBtype", escc_serial);
1140 qdev_prop_set_uint32(d, "chnAtype", escc_serial);
1141
1142 sbd = SYS_BUS_DEVICE(d);
1143 if (!sysbus_realize(sbd, errp)) {
1144 return;
1145 }
1146 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I));
1147 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I));
1148
1149 /* RTC */
1150 d = DEVICE(&s->rtc);
1151 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) {
1152 return;
1153 }
1154 /* Data from NeXTPC to RTC */
1155 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0,
1156 qdev_get_gpio_in_named(d, "rtc-data-in", 0));
1157 /* Data from RTC to NeXTPC */
1158 qdev_connect_gpio_out_named(d, "rtc-data-out", 0,
1159 qdev_get_gpio_in_named(dev,
1160 "rtc-data-in", 0));
1161 qdev_connect_gpio_out_named(dev, "rtc-cmd-reset", 0,
1162 qdev_get_gpio_in_named(d, "rtc-cmd-reset", 0));
1163 qdev_connect_gpio_out_named(d, "rtc-power-out", 0,
1164 qdev_get_gpio_in(dev, NEXT_PWR_I));
1165 }
1166
1167 static void next_pc_init(Object *obj)
1168 {
1169 NeXTPC *s = NEXT_PC(obj);
1170 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1171
1172 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS);
1173
1174 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s,
1175 "next.mmio", 0x9000);
1176 sysbus_init_mmio(sbd, &s->mmiomem);
1177
1178 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s,
1179 "next.en", 0x20);
1180 sysbus_init_mmio(sbd, &s->dummyen_mem);
1181
1182 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI);
1183 sysbus_init_mmio(sbd,
1184 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0));
1185
1186 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s,
1187 "next.floppy", 4);
1188 sysbus_init_mmio(sbd, &s->floppy_mem);
1189
1190 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC);
1191 sysbus_init_mmio(sbd,
1192 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0));
1193
1194 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s,
1195 "next.timer", 4);
1196 sysbus_init_mmio(sbd, &s->timer_mem);
1197
1198 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC);
1199
1200 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq,
1201 "rtc-data-in", 1);
1202 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq,
1203 "rtc-data-out", 1);
1204 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_cmd_reset_irq,
1205 "rtc-cmd-reset", 1);
1206 }
1207
1208 /*
1209 * If the m68k CPU implemented its inbound irq lines as GPIO lines
1210 * rather than via the m68k_set_irq_level() function we would not need
1211 * this cpu link property and could instead provide outbound IRQ lines
1212 * that the board could wire up to the CPU.
1213 */
1214 static const Property next_pc_properties[] = {
1215 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *),
1216 };
1217
1218 static const VMStateDescription next_pc_vmstate = {
1219 .name = "next-pc",
1220 .version_id = 4,
1221 .minimum_version_id = 4,
1222 .fields = (const VMStateField[]) {
1223 VMSTATE_UINT32(scr1, NeXTPC),
1224 VMSTATE_UINT32(scr2, NeXTPC),
1225 VMSTATE_UINT32(old_scr2, NeXTPC),
1226 VMSTATE_UINT32(int_mask, NeXTPC),
1227 VMSTATE_UINT32(int_status, NeXTPC),
1228 VMSTATE_UINT32(led, NeXTPC),
1229 VMSTATE_END_OF_LIST()
1230 },
1231 };
1232
1233 static void next_pc_class_init(ObjectClass *klass, const void *data)
1234 {
1235 DeviceClass *dc = DEVICE_CLASS(klass);
1236 ResettableClass *rc = RESETTABLE_CLASS(klass);
1237
1238 dc->desc = "NeXT Peripheral Controller";
1239 dc->realize = next_pc_realize;
1240 device_class_set_props(dc, next_pc_properties);
1241 dc->vmsd = &next_pc_vmstate;
1242 rc->phases.hold = next_pc_reset_hold;
1243 }
1244
1245 static const TypeInfo next_pc_info = {
1246 .name = TYPE_NEXT_PC,
1247 .parent = TYPE_SYS_BUS_DEVICE,
1248 .instance_init = next_pc_init,
1249 .instance_size = sizeof(NeXTPC),
1250 .class_init = next_pc_class_init,
1251 };
1252
1253 static void next_cube_init(MachineState *machine)
1254 {
1255 NeXTState *m = NEXT_MACHINE(machine);
1256 M68kCPU *cpu;
1257 CPUM68KState *env;
1258 MemoryRegion *sysmem = get_system_memory();
1259 const char *bios_name = machine->firmware ?: ROM_FILE;
1260 DeviceState *pcdev;
1261
1262 /* Initialize the cpu core */
1263 cpu = M68K_CPU(cpu_create(machine->cpu_type));
1264 if (!cpu) {
1265 error_report("Unable to find m68k CPU definition");
1266 exit(1);
1267 }
1268 env = &cpu->env;
1269
1270 /* Initialize CPU registers. */
1271 env->vbr = 0;
1272 env->sr = 0x2700;
1273
1274 /* Peripheral Controller */
1275 pcdev = qdev_new(TYPE_NEXT_PC);
1276 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort);
1277 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal);
1278
1279 /* 64MB RAM starting at 0x04000000 */
1280 memory_region_add_subregion(sysmem, 0x04000000, machine->ram);
1281
1282 /* Framebuffer */
1283 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL);
1284
1285 /* MMIO */
1286 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000);
1287
1288 /* BMAP IO - acts as a catch-all for now */
1289 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000);
1290
1291 /* en network (dummy) */
1292 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000);
1293
1294 /* unknown: Brightness control register? */
1295 empty_slot_init("next.unknown.0", 0x02110000, 0x10);
1296 /* unknown: Magneto-Optical drive controller? */
1297 empty_slot_init("next.unknown.1", 0x02112000, 0x10);
1298
1299 /* SCSI */
1300 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000);
1301 /* Floppy */
1302 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108);
1303 /* ESCC */
1304 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000);
1305
1306 /* unknown: Serial clock configuration register? */
1307 empty_slot_init("next.unknown.2", 0x02118004, 0x10);
1308
1309 /* Timer */
1310 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000);
1311
1312 /* BMAP memory */
1313 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem",
1314 64, RAM_SHARED, &error_fatal);
1315 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1);
1316 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */
1317 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1,
1318 0x0, 64);
1319 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2);
1320
1321 /* KBD */
1322 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL);
1323
1324 /* Load ROM here */
1325 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal);
1326 memory_region_add_subregion(sysmem, 0x01000000, &m->rom);
1327 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0,
1328 0x20000);
1329 memory_region_add_subregion(sysmem, 0x0, &m->rom2);
1330 Error *local_err = NULL;
1331 if (load_image_targphys(bios_name, 0x01000000, 0x20000, &local_err) < 8) {
1332 if (!qtest_enabled()) {
1333 if (local_err) {
1334 error_report_err(local_err);
1335 } else {
1336 error_report("Firmware image '%s' is too short.", bios_name);
1337 }
1338 } else {
1339 error_free(local_err);
1340 }
1341 } else {
1342 uint8_t *ptr;
1343 /* Initial PC is always at offset 4 in firmware binaries */
1344 ptr = rom_ptr(0x01000004, 4);
1345 g_assert(ptr != NULL);
1346 env->pc = ldl_be_p(ptr);
1347 if (env->pc >= 0x01020000) {
1348 error_report("'%s' does not seem to be a valid firmware image.",
1349 bios_name);
1350 exit(1);
1351 }
1352 }
1353
1354 /* DMA */
1355 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine,
1356 "next.dma", 0x5000);
1357 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem);
1358 }
1359
1360 static void next_machine_class_init(ObjectClass *oc, const void *data)
1361 {
1362 MachineClass *mc = MACHINE_CLASS(oc);
1363
1364 mc->desc = "NeXT Cube";
1365 mc->init = next_cube_init;
1366 mc->block_default_type = IF_SCSI;
1367 mc->default_ram_size = RAM_SIZE;
1368 mc->default_ram_id = "next.ram";
1369 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
1370 mc->no_cdrom = true;
1371 }
1372
1373 static const TypeInfo next_typeinfo = {
1374 .name = TYPE_NEXT_MACHINE,
1375 .parent = TYPE_MACHINE,
1376 .class_init = next_machine_class_init,
1377 .instance_size = sizeof(NeXTState),
1378 };
1379
1380 static void next_register_type(void)
1381 {
1382 type_register_static(&next_typeinfo);
1383 type_register_static(&next_pc_info);
1384 type_register_static(&next_scsi_info);
1385 type_register_static(&next_rtc_info);
1386 }
1387
1388 type_init(next_register_type)