| 1 | /* |
| 2 | * Coherent Processing System emulation. |
| 3 | * |
| 4 | * Copyright (c) 2016 Imagination Technologies |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qapi/error.h" |
| 22 | #include "qemu/module.h" |
| 23 | #include "hw/mips/cps.h" |
| 24 | #include "hw/mips/mips.h" |
| 25 | #include "hw/core/qdev-clock.h" |
| 26 | #include "hw/core/qdev-properties.h" |
| 27 | #include "system/tcg.h" |
| 28 | #include "system/reset.h" |
| 29 | |
| 30 | qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) |
| 31 | { |
| 32 | assert(pin_number < s->num_irq); |
| 33 | return s->gic.irq_state[pin_number].irq; |
| 34 | } |
| 35 | |
| 36 | static void mips_cps_init(Object *obj) |
| 37 | { |
| 38 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 39 | MIPSCPSState *s = MIPS_CPS(obj); |
| 40 | |
| 41 | s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); |
| 42 | /* |
| 43 | * Cover entire address space as there do not seem to be any |
| 44 | * constraints for the base address of CPC and GIC. |
| 45 | */ |
| 46 | memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); |
| 47 | sysbus_init_mmio(sbd, &s->container); |
| 48 | } |
| 49 | |
| 50 | static void main_cpu_reset(void *opaque) |
| 51 | { |
| 52 | MIPSCPU *cpu = opaque; |
| 53 | CPUState *cs = CPU(cpu); |
| 54 | |
| 55 | cpu_reset(cs); |
| 56 | } |
| 57 | |
| 58 | static bool cpu_mips_itu_supported(CPUMIPSState *env) |
| 59 | { |
| 60 | bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); |
| 61 | |
| 62 | return is_mt && tcg_enabled(); |
| 63 | } |
| 64 | |
| 65 | static void mips_cps_realize(DeviceState *dev, Error **errp) |
| 66 | { |
| 67 | MIPSCPSState *s = MIPS_CPS(dev); |
| 68 | target_ulong gcr_base; |
| 69 | bool itu_present = false; |
| 70 | |
| 71 | if (!clock_get(s->clock)) { |
| 72 | error_setg(errp, "CPS input clock is not connected to an output clock"); |
| 73 | return; |
| 74 | } |
| 75 | |
| 76 | for (int i = 0; i < s->num_vp; i++) { |
| 77 | MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); |
| 78 | CPUMIPSState *env = &cpu->env; |
| 79 | |
| 80 | object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bigendian, |
| 81 | &error_abort); |
| 82 | |
| 83 | /* All VPs are halted on reset. Leave powering up to CPC. */ |
| 84 | object_property_set_bool(OBJECT(cpu), "start-powered-off", true, |
| 85 | &error_abort); |
| 86 | |
| 87 | /* All cores use the same clock tree */ |
| 88 | qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); |
| 89 | |
| 90 | if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { |
| 91 | return; |
| 92 | } |
| 93 | |
| 94 | /* Init internal devices */ |
| 95 | cpu_mips_irq_init_cpu(cpu); |
| 96 | cpu_mips_clock_init(cpu); |
| 97 | |
| 98 | if (cpu_mips_itu_supported(env)) { |
| 99 | itu_present = true; |
| 100 | /* Attach ITC Tag to the VP */ |
| 101 | env->itc_tag = mips_itu_get_tag_region(&s->itu); |
| 102 | } |
| 103 | qemu_register_reset(main_cpu_reset, cpu); |
| 104 | } |
| 105 | |
| 106 | /* Inter-Thread Communication Unit */ |
| 107 | if (itu_present) { |
| 108 | object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); |
| 109 | object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, |
| 110 | &error_abort); |
| 111 | object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, |
| 112 | &error_abort); |
| 113 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { |
| 114 | return; |
| 115 | } |
| 116 | |
| 117 | memory_region_add_subregion(&s->container, 0, |
| 118 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); |
| 119 | } |
| 120 | |
| 121 | /* Cluster Power Controller */ |
| 122 | object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); |
| 123 | object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, |
| 124 | &error_abort); |
| 125 | object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, |
| 126 | &error_abort); |
| 127 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) { |
| 128 | return; |
| 129 | } |
| 130 | |
| 131 | memory_region_add_subregion(&s->container, 0, |
| 132 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); |
| 133 | |
| 134 | /* Global Interrupt Controller */ |
| 135 | object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); |
| 136 | object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, |
| 137 | &error_abort); |
| 138 | object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, |
| 139 | &error_abort); |
| 140 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { |
| 141 | return; |
| 142 | } |
| 143 | |
| 144 | memory_region_add_subregion(&s->container, 0, |
| 145 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); |
| 146 | |
| 147 | /* Global Configuration Registers */ |
| 148 | gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; |
| 149 | |
| 150 | object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); |
| 151 | object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, |
| 152 | &error_abort); |
| 153 | object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, |
| 154 | &error_abort); |
| 155 | object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, |
| 156 | &error_abort); |
| 157 | object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), |
| 158 | &error_abort); |
| 159 | object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), |
| 160 | &error_abort); |
| 161 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { |
| 162 | return; |
| 163 | } |
| 164 | |
| 165 | memory_region_add_subregion(&s->container, gcr_base, |
| 166 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); |
| 167 | } |
| 168 | |
| 169 | static const Property mips_cps_properties[] = { |
| 170 | DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), |
| 171 | DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), |
| 172 | DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), |
| 173 | DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false), |
| 174 | }; |
| 175 | |
| 176 | static void mips_cps_class_init(ObjectClass *klass, const void *data) |
| 177 | { |
| 178 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 179 | |
| 180 | dc->realize = mips_cps_realize; |
| 181 | device_class_set_props(dc, mips_cps_properties); |
| 182 | } |
| 183 | |
| 184 | static const TypeInfo mips_cps_info = { |
| 185 | .name = TYPE_MIPS_CPS, |
| 186 | .parent = TYPE_SYS_BUS_DEVICE, |
| 187 | .instance_size = sizeof(MIPSCPSState), |
| 188 | .instance_init = mips_cps_init, |
| 189 | .class_init = mips_cps_class_init, |
| 190 | }; |
| 191 | |
| 192 | static void mips_cps_register_types(void) |
| 193 | { |
| 194 | type_register_static(&mips_cps_info); |
| 195 | } |
| 196 | |
| 197 | type_init(mips_cps_register_types) |