| 1 | /* |
| 2 | * Generic Loongson-3 Platform support |
| 3 | * |
| 4 | * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com) |
| 5 | * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com> |
| 6 | * |
| 7 | * This program is free software: you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation, either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <https://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with |
| 23 | * extensions, 800~2000MHz) |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "qemu/units.h" |
| 28 | #include "qemu/cutils.h" |
| 29 | #include "qemu/datadir.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "elf.h" |
| 32 | #include "hw/char/serial-mm.h" |
| 33 | #include "hw/intc/loongson_liointc.h" |
| 34 | #include "hw/mips/mips.h" |
| 35 | #include "hw/mips/fw_cfg.h" |
| 36 | #include "hw/mips/loongson3_bootp.h" |
| 37 | #include "hw/misc/unimp.h" |
| 38 | #include "hw/intc/i8259.h" |
| 39 | #include "hw/intc/loongson_ipi.h" |
| 40 | #include "hw/core/loader.h" |
| 41 | #include "hw/isa/superio.h" |
| 42 | #include "hw/pci/msi.h" |
| 43 | #include "hw/pci/pci.h" |
| 44 | #include "hw/pci/pci_host.h" |
| 45 | #include "hw/pci-host/gpex.h" |
| 46 | #include "hw/usb/usb.h" |
| 47 | #include "net/net.h" |
| 48 | #include "system/qtest.h" |
| 49 | #include "system/reset.h" |
| 50 | #include "system/runstate.h" |
| 51 | #include "system/system.h" |
| 52 | #include "qemu/error-report.h" |
| 53 | #include "target/mips/cpu.h" |
| 54 | |
| 55 | #define PM_CNTL_MODE 0x10 |
| 56 | |
| 57 | #define LOONGSON_MAX_VCPUS 16 |
| 58 | |
| 59 | /* |
| 60 | * Loongson-3's virtual machine BIOS can be obtained here: |
| 61 | * 1, https://github.com/loongson-community/firmware-nonfree |
| 62 | * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin |
| 63 | */ |
| 64 | #define LOONGSON3_BIOSNAME "bios_loongson3.bin" |
| 65 | |
| 66 | #define UART_IRQ 0 |
| 67 | #define RTC_IRQ 1 |
| 68 | #define PCIE_IRQ_BASE 2 |
| 69 | |
| 70 | const MemMapEntry virt_memmap[] = { |
| 71 | [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, |
| 72 | [VIRT_PM] = { 0x10080000, 0x100 }, |
| 73 | [VIRT_FW_CFG] = { 0x10080100, 0x100 }, |
| 74 | [VIRT_RTC] = { 0x10081000, 0x1000 }, |
| 75 | [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 }, |
| 76 | [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, |
| 77 | [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, |
| 78 | [VIRT_UART] = { 0x1fe001e0, 0x8 }, |
| 79 | [VIRT_IPI] = { 0x3ff01000, 0x400 }, |
| 80 | [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, |
| 81 | [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, |
| 82 | [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ |
| 83 | }; |
| 84 | |
| 85 | static const MemMapEntry loader_memmap[] = { |
| 86 | [LOADER_KERNEL] = { 0x00000000, 0x4000000 }, |
| 87 | [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */ |
| 88 | [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 }, |
| 89 | }; |
| 90 | |
| 91 | static const MemMapEntry loader_rommap[] = { |
| 92 | [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 }, |
| 93 | [LOADER_PARAM] = { 0x1fc01000, 0x10000 }, |
| 94 | }; |
| 95 | |
| 96 | struct LoongsonMachineState { |
| 97 | MachineState parent_obj; |
| 98 | MemoryRegion *pio_alias; |
| 99 | MemoryRegion *mmio_alias; |
| 100 | MemoryRegion *ecam_alias; |
| 101 | MemoryRegion *core_iocsr[LOONGSON_MAX_VCPUS]; |
| 102 | }; |
| 103 | typedef struct LoongsonMachineState LoongsonMachineState; |
| 104 | |
| 105 | #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt") |
| 106 | DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE) |
| 107 | |
| 108 | static struct _loaderparams { |
| 109 | uint64_t cpu_freq; |
| 110 | uint64_t ram_size; |
| 111 | const char *kernel_cmdline; |
| 112 | const char *kernel_filename; |
| 113 | const char *initrd_filename; |
| 114 | uint64_t kernel_entry; |
| 115 | uint64_t a0, a1, a2; |
| 116 | } loaderparams; |
| 117 | |
| 118 | static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size) |
| 119 | { |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static void loongson3_pm_write(void *opaque, hwaddr addr, |
| 124 | uint64_t val, unsigned size) |
| 125 | { |
| 126 | if (addr != PM_CNTL_MODE) { |
| 127 | return; |
| 128 | } |
| 129 | |
| 130 | switch (val) { |
| 131 | case 0x00: |
| 132 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 133 | return; |
| 134 | case 0x01: |
| 135 | qemu_system_suspend_request(); |
| 136 | return; |
| 137 | case 0xff: |
| 138 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
| 139 | return; |
| 140 | default: |
| 141 | return; |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static const MemoryRegionOps loongson3_pm_ops = { |
| 146 | .read = loongson3_pm_read, |
| 147 | .write = loongson3_pm_write, |
| 148 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 149 | .valid = { |
| 150 | .min_access_size = 1, |
| 151 | .max_access_size = 1 |
| 152 | } |
| 153 | }; |
| 154 | |
| 155 | #define DEF_LOONGSON3_FREQ (800 * 1000 * 1000) |
| 156 | |
| 157 | static uint64_t get_cpu_freq_hz(const MIPSCPU *cpu) |
| 158 | { |
| 159 | return DEF_LOONGSON3_FREQ; |
| 160 | } |
| 161 | |
| 162 | static void init_boot_param(unsigned cpu_count, uint32_t processor_id) |
| 163 | { |
| 164 | static void *p; |
| 165 | struct boot_params *bp; |
| 166 | |
| 167 | p = g_malloc0(loader_rommap[LOADER_PARAM].size); |
| 168 | bp = p; |
| 169 | |
| 170 | bp->efi.smbios.vers = cpu_to_le16(1); |
| 171 | init_reset_system(&(bp->reset_system)); |
| 172 | p += ROUND_UP(sizeof(struct boot_params), 64); |
| 173 | init_loongson_params(&(bp->efi.smbios.lp), p, cpu_count, processor_id, |
| 174 | loaderparams.cpu_freq, loaderparams.ram_size); |
| 175 | |
| 176 | rom_add_blob_fixed("params_rom", bp, |
| 177 | loader_rommap[LOADER_PARAM].size, |
| 178 | loader_rommap[LOADER_PARAM].base); |
| 179 | |
| 180 | g_free(bp); |
| 181 | |
| 182 | loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, |
| 183 | loader_rommap[LOADER_PARAM].base); |
| 184 | } |
| 185 | |
| 186 | static void init_boot_rom(void) |
| 187 | { |
| 188 | const unsigned int boot_code[] = { |
| 189 | 0x40086000, /* mfc0 t0, CP0_STATUS */ |
| 190 | 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */ |
| 191 | 0x01094025, /* or t0, t0, t1 */ |
| 192 | 0x3C090040, /* lui t1, 0x40 #set bev */ |
| 193 | 0x01094025, /* or t0, t0, t1 */ |
| 194 | 0x40886000, /* mtc0 t0, CP0_STATUS */ |
| 195 | 0x00000000, |
| 196 | 0x40806800, /* mtc0 zero, CP0_CAUSE */ |
| 197 | 0x00000000, |
| 198 | 0x400A7801, /* mfc0 t2, $15, 1 */ |
| 199 | 0x314A00FF, /* andi t2, 0x0ff */ |
| 200 | 0x3C089000, /* dli t0, 0x900000003ff01000 */ |
| 201 | 0x00084438, |
| 202 | 0x35083FF0, |
| 203 | 0x00084438, |
| 204 | 0x35081000, |
| 205 | 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */ |
| 206 | 0x000B5A00, /* sll t3, 8 */ |
| 207 | 0x010B4025, /* or t0, t0, t3 */ |
| 208 | 0x314C000C, /* andi t4, t2, 0xc #node id */ |
| 209 | 0x000C62BC, /* dsll t4, 42 */ |
| 210 | 0x010C4025, /* or t0, t0, t4 */ |
| 211 | /* WaitForInit: */ |
| 212 | 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */ |
| 213 | 0x1040FFFE, /* beqz v0, WaitForInit */ |
| 214 | 0x00000000, /* nop */ |
| 215 | 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */ |
| 216 | 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */ |
| 217 | 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */ |
| 218 | 0x00400008, /* jr v0 #byebye */ |
| 219 | 0x00000000, /* nop */ |
| 220 | 0x1000FFFF, /* 1: b 1b */ |
| 221 | 0x00000000, /* nop */ |
| 222 | |
| 223 | /* Reset */ |
| 224 | 0x3C0C9000, /* dli t0, 0x9000000010080010 */ |
| 225 | 0x358C0000, |
| 226 | 0x000C6438, |
| 227 | 0x358C1008, |
| 228 | 0x000C6438, |
| 229 | 0x358C0010, |
| 230 | 0x240D0000, /* li t1, 0x00 */ |
| 231 | 0xA18D0000, /* sb t1, (t0) */ |
| 232 | 0x1000FFFF, /* 1: b 1b */ |
| 233 | 0x00000000, /* nop */ |
| 234 | |
| 235 | /* Shutdown */ |
| 236 | 0x3C0C9000, /* dli t0, 0x9000000010080010 */ |
| 237 | 0x358C0000, |
| 238 | 0x000C6438, |
| 239 | 0x358C1008, |
| 240 | 0x000C6438, |
| 241 | 0x358C0010, |
| 242 | 0x240D00FF, /* li t1, 0xff */ |
| 243 | 0xA18D0000, /* sb t1, (t0) */ |
| 244 | 0x1000FFFF, /* 1: b 1b */ |
| 245 | 0x00000000, /* nop */ |
| 246 | /* Suspend */ |
| 247 | 0x3C0C9000, /* dli t0, 0x9000000010080010 */ |
| 248 | 0x358C0000, |
| 249 | 0x000C6438, |
| 250 | 0x358C1008, |
| 251 | 0x000C6438, |
| 252 | 0x358C0010, |
| 253 | 0x240D0001, /* li t1, 0x01 */ |
| 254 | 0xA18D0000, /* sb t1, (t0) */ |
| 255 | 0x03e00008, /* jr ra */ |
| 256 | 0x00000000 /* nop */ |
| 257 | }; |
| 258 | |
| 259 | rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code), |
| 260 | loader_rommap[LOADER_BOOTROM].base); |
| 261 | } |
| 262 | |
| 263 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
| 264 | Error **errp) |
| 265 | { |
| 266 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
| 267 | } |
| 268 | |
| 269 | static void fw_conf_init(void) |
| 270 | { |
| 271 | static const uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; |
| 272 | FWCfgState *fw_cfg; |
| 273 | hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; |
| 274 | |
| 275 | fw_cfg = fw_cfg_init_mem_nodma(cfg_addr, cfg_addr + 8, 8); |
| 276 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); |
| 277 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); |
| 278 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, loaderparams.ram_size); |
| 279 | fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1); |
| 280 | fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, loaderparams.cpu_freq); |
| 281 | |
| 282 | fw_cfg_add_file(fw_cfg, "etc/system-states", |
| 283 | g_memdup2(suspend, sizeof(suspend)), sizeof(suspend)); |
| 284 | |
| 285 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
| 286 | } |
| 287 | |
| 288 | static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size) |
| 289 | { |
| 290 | int ret = 0; |
| 291 | void *cmdline_buf; |
| 292 | hwaddr cmdline_vaddr; |
| 293 | unsigned int *parg_env; |
| 294 | |
| 295 | /* Allocate cmdline_buf for command line. */ |
| 296 | cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size); |
| 297 | cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL, |
| 298 | loader_memmap[LOADER_CMDLINE].base); |
| 299 | |
| 300 | /* |
| 301 | * Layout of cmdline_buf looks like this: |
| 302 | * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0, |
| 303 | * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0 |
| 304 | */ |
| 305 | parg_env = (void *)cmdline_buf; |
| 306 | |
| 307 | ret = (3 + 1) * 4; |
| 308 | *parg_env++ = cmdline_vaddr + ret; |
| 309 | ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g")); |
| 310 | |
| 311 | /* argv1 */ |
| 312 | *parg_env++ = cmdline_vaddr + ret; |
| 313 | if (initrd_size > 0) |
| 314 | ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, |
| 315 | "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", |
| 316 | cpu_mips_phys_to_kseg0(NULL, initrd_offset), |
| 317 | initrd_size, loaderparams.kernel_cmdline)); |
| 318 | else |
| 319 | ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s", |
| 320 | loaderparams.kernel_cmdline)); |
| 321 | |
| 322 | /* argv2 */ |
| 323 | *parg_env++ = cmdline_vaddr + 4 * ret; |
| 324 | |
| 325 | rom_add_blob_fixed("cmdline", cmdline_buf, |
| 326 | loader_memmap[LOADER_CMDLINE].size, |
| 327 | loader_memmap[LOADER_CMDLINE].base); |
| 328 | |
| 329 | g_free(cmdline_buf); |
| 330 | |
| 331 | loaderparams.a0 = 2; |
| 332 | loaderparams.a1 = cmdline_vaddr; |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | static uint64_t load_kernel(CPUMIPSState *env) |
| 338 | { |
| 339 | long kernel_size; |
| 340 | ram_addr_t initrd_offset; |
| 341 | uint64_t kernel_entry, kernel_low, kernel_high, initrd_size; |
| 342 | |
| 343 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, |
| 344 | cpu_mips_kseg0_to_phys, NULL, |
| 345 | &kernel_entry, |
| 346 | &kernel_low, &kernel_high, |
| 347 | NULL, ELFDATA2LSB, EM_MIPS, 1, 0); |
| 348 | if (kernel_size < 0) { |
| 349 | error_report("could not load kernel '%s': %s", |
| 350 | loaderparams.kernel_filename, |
| 351 | load_elf_strerror(kernel_size)); |
| 352 | exit(1); |
| 353 | } |
| 354 | |
| 355 | /* load initrd */ |
| 356 | initrd_size = 0; |
| 357 | initrd_offset = 0; |
| 358 | if (loaderparams.initrd_filename) { |
| 359 | initrd_size = get_image_size(loaderparams.initrd_filename, NULL); |
| 360 | if (initrd_size > 0) { |
| 361 | initrd_offset = MAX(loader_memmap[LOADER_INITRD].base, |
| 362 | ROUND_UP(kernel_high, INITRD_PAGE_SIZE)); |
| 363 | |
| 364 | if (initrd_offset + initrd_size > loaderparams.ram_size) { |
| 365 | error_report("memory too small for initial ram disk '%s'", |
| 366 | loaderparams.initrd_filename); |
| 367 | exit(1); |
| 368 | } |
| 369 | |
| 370 | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
| 371 | initrd_offset, |
| 372 | loaderparams.ram_size - initrd_offset, |
| 373 | NULL); |
| 374 | } |
| 375 | |
| 376 | if (initrd_size == (target_ulong) -1) { |
| 377 | error_report("could not load initial ram disk '%s'", |
| 378 | loaderparams.initrd_filename); |
| 379 | exit(1); |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | /* Setup prom cmdline. */ |
| 384 | set_prom_cmdline(initrd_offset, initrd_size); |
| 385 | |
| 386 | return kernel_entry; |
| 387 | } |
| 388 | |
| 389 | static void generic_cpu_reset(void *opaque) |
| 390 | { |
| 391 | MIPSCPU *cpu = opaque; |
| 392 | CPUMIPSState *env = &cpu->env; |
| 393 | |
| 394 | cpu_reset(CPU(cpu)); |
| 395 | |
| 396 | if (loaderparams.kernel_filename) { |
| 397 | env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | static void main_cpu_reset(void *opaque) |
| 402 | { |
| 403 | generic_cpu_reset(opaque); |
| 404 | |
| 405 | if (loaderparams.kernel_filename) { |
| 406 | MIPSCPU *cpu = opaque; |
| 407 | CPUMIPSState *env = &cpu->env; |
| 408 | |
| 409 | env->active_tc.gpr[4] = loaderparams.a0; |
| 410 | env->active_tc.gpr[5] = loaderparams.a1; |
| 411 | env->active_tc.gpr[6] = loaderparams.a2; |
| 412 | env->active_tc.PC = loaderparams.kernel_entry; |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | static inline void loongson3_virt_devices_init(MachineState *machine, |
| 417 | DeviceState *pic) |
| 418 | { |
| 419 | int i; |
| 420 | qemu_irq irq; |
| 421 | PCIBus *pci_bus; |
| 422 | DeviceState *dev; |
| 423 | MemoryRegion *mmio_reg, *ecam_reg; |
| 424 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 425 | LoongsonMachineState *s = LOONGSON_MACHINE(machine); |
| 426 | |
| 427 | dev = qdev_new(TYPE_GPEX_HOST); |
| 428 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 429 | pci_bus = PCI_HOST_BRIDGE(dev)->bus; |
| 430 | |
| 431 | s->ecam_alias = g_new0(MemoryRegion, 1); |
| 432 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
| 433 | memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam", |
| 434 | ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); |
| 435 | memory_region_add_subregion(get_system_memory(), |
| 436 | virt_memmap[VIRT_PCIE_ECAM].base, |
| 437 | s->ecam_alias); |
| 438 | |
| 439 | s->mmio_alias = g_new0(MemoryRegion, 1); |
| 440 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); |
| 441 | memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio", |
| 442 | mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, |
| 443 | virt_memmap[VIRT_PCIE_MMIO].size); |
| 444 | memory_region_add_subregion(get_system_memory(), |
| 445 | virt_memmap[VIRT_PCIE_MMIO].base, |
| 446 | s->mmio_alias); |
| 447 | |
| 448 | s->pio_alias = g_new0(MemoryRegion, 1); |
| 449 | memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio", |
| 450 | get_system_io(), 0, |
| 451 | virt_memmap[VIRT_PCIE_PIO].size); |
| 452 | memory_region_add_subregion(get_system_memory(), |
| 453 | virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); |
| 454 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); |
| 455 | |
| 456 | for (i = 0; i < PCI_NUM_PINS; i++) { |
| 457 | irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); |
| 458 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); |
| 459 | gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); |
| 460 | } |
| 461 | msi_nonbroken = true; |
| 462 | |
| 463 | pci_vga_init(pci_bus); |
| 464 | |
| 465 | if (defaults_enabled() && object_class_by_name("pci-ohci")) { |
| 466 | USBBus *usb_bus; |
| 467 | |
| 468 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
| 469 | usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, |
| 470 | &error_abort)); |
| 471 | usb_create_simple(usb_bus, "usb-kbd"); |
| 472 | usb_create_simple(usb_bus, "usb-tablet"); |
| 473 | } |
| 474 | |
| 475 | pci_init_nic_devices(pci_bus, mc->default_nic); |
| 476 | } |
| 477 | |
| 478 | static void mips_loongson3_virt_init(MachineState *machine) |
| 479 | { |
| 480 | int i; |
| 481 | long bios_size; |
| 482 | MIPSCPU *cpu = NULL; |
| 483 | Clock *cpuclk; |
| 484 | DeviceState *liointc; |
| 485 | DeviceState *ipi = NULL; |
| 486 | char *filename; |
| 487 | const char *kernel_cmdline = machine->kernel_cmdline; |
| 488 | const char *kernel_filename = machine->kernel_filename; |
| 489 | const char *initrd_filename = machine->initrd_filename; |
| 490 | ram_addr_t ram_size = machine->ram_size; |
| 491 | LoongsonMachineState *s = LOONGSON_MACHINE(machine); |
| 492 | MemoryRegion *address_space_mem = get_system_memory(); |
| 493 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
| 494 | MemoryRegion *bios = g_new(MemoryRegion, 1); |
| 495 | MemoryRegion *iomem = g_new(MemoryRegion, 1); |
| 496 | MemoryRegion *iocsr = g_new(MemoryRegion, 1); |
| 497 | |
| 498 | /* TODO: Support all CPU types */ |
| 499 | if (!machine->cpu_type) { |
| 500 | machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000"); |
| 501 | } |
| 502 | if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) { |
| 503 | error_report("Loongson-3/TCG needs a Loongson-3 series cpu"); |
| 504 | exit(1); |
| 505 | } |
| 506 | |
| 507 | if (ram_size < 512 * MiB) { |
| 508 | error_report("Loongson-3 machine needs at least 512MB memory"); |
| 509 | exit(1); |
| 510 | } |
| 511 | |
| 512 | /* |
| 513 | * The whole MMIO range among configure registers doesn't generate |
| 514 | * exception when accessing invalid memory. Create some unimplememted |
| 515 | * devices to emulate this feature. |
| 516 | */ |
| 517 | create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); |
| 518 | create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); |
| 519 | |
| 520 | memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX); |
| 521 | |
| 522 | ipi = qdev_new(TYPE_LOONGSON_IPI); |
| 523 | qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus); |
| 524 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); |
| 525 | memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX, |
| 526 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); |
| 527 | memory_region_add_subregion(iocsr, MAIL_SEND_ADDR, |
| 528 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); |
| 529 | |
| 530 | liointc = qdev_new("loongson.liointc"); |
| 531 | sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); |
| 532 | |
| 533 | sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); |
| 534 | |
| 535 | serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0, |
| 536 | qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), |
| 537 | DEVICE_LITTLE_ENDIAN); |
| 538 | |
| 539 | sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base, |
| 540 | qdev_get_gpio_in(liointc, RTC_IRQ)); |
| 541 | |
| 542 | cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); |
| 543 | clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); |
| 544 | |
| 545 | for (i = machine->smp.cpus - 1; i >= 0; --i) { |
| 546 | int node = i / LOONGSON3_CORE_PER_NODE; |
| 547 | int core = i % LOONGSON3_CORE_PER_NODE; |
| 548 | int ip; |
| 549 | hwaddr ipi_base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base; |
| 550 | |
| 551 | /* init CPUs */ |
| 552 | cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); |
| 553 | |
| 554 | /* Init internal devices */ |
| 555 | cpu_mips_irq_init_cpu(cpu); |
| 556 | cpu_mips_clock_init(cpu); |
| 557 | qemu_register_reset(i ? generic_cpu_reset : main_cpu_reset, cpu); |
| 558 | |
| 559 | qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]); |
| 560 | sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, ipi_base + core * 0x100); |
| 561 | |
| 562 | if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { |
| 563 | MemoryRegion *core_iocsr = g_new(MemoryRegion, 1); |
| 564 | g_autofree char *name = g_strdup_printf("core%d_iocsr", i); |
| 565 | memory_region_init_alias(core_iocsr, OBJECT(cpu), name, |
| 566 | iocsr, 0, UINT32_MAX); |
| 567 | memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr, |
| 568 | 0, core_iocsr); |
| 569 | s->core_iocsr[i] = core_iocsr; |
| 570 | } |
| 571 | |
| 572 | if (node > 0) { |
| 573 | continue; /* Only node-0 can be connected to LIOINTC */ |
| 574 | } |
| 575 | |
| 576 | for (ip = 0; ip < 4 ; ip++) { |
| 577 | int pin = core * LOONGSON3_CORE_PER_NODE + ip; |
| 578 | sysbus_connect_irq(SYS_BUS_DEVICE(liointc), |
| 579 | pin, cpu->env.irq[ip + 2]); |
| 580 | } |
| 581 | } |
| 582 | assert(cpu); /* This variable points to the first created cpu. */ |
| 583 | |
| 584 | /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */ |
| 585 | memory_region_init_rom(bios, NULL, "loongson3.bios", |
| 586 | virt_memmap[VIRT_BIOS_ROM].size, &error_fatal); |
| 587 | memory_region_init_alias(ram, NULL, "loongson3.lowmem", |
| 588 | machine->ram, 0, virt_memmap[VIRT_LOWMEM].size); |
| 589 | memory_region_init_io(iomem, NULL, &loongson3_pm_ops, |
| 590 | NULL, "loongson3_pm", virt_memmap[VIRT_PM].size); |
| 591 | qemu_register_wakeup_support(); |
| 592 | |
| 593 | memory_region_add_subregion(address_space_mem, |
| 594 | virt_memmap[VIRT_LOWMEM].base, ram); |
| 595 | memory_region_add_subregion(address_space_mem, |
| 596 | virt_memmap[VIRT_BIOS_ROM].base, bios); |
| 597 | memory_region_add_subregion(address_space_mem, |
| 598 | virt_memmap[VIRT_HIGHMEM].base, machine->ram); |
| 599 | memory_region_add_subregion(address_space_mem, |
| 600 | virt_memmap[VIRT_PM].base, iomem); |
| 601 | |
| 602 | /* |
| 603 | * We do not support flash operation, just loading bios.bin as raw BIOS. |
| 604 | * Please use -L to set the BIOS path and -bios to set bios name. |
| 605 | */ |
| 606 | |
| 607 | loaderparams.cpu_freq = get_cpu_freq_hz(cpu); |
| 608 | loaderparams.ram_size = ram_size; |
| 609 | if (kernel_filename) { |
| 610 | loaderparams.kernel_filename = kernel_filename; |
| 611 | loaderparams.kernel_cmdline = kernel_cmdline; |
| 612 | loaderparams.initrd_filename = initrd_filename; |
| 613 | loaderparams.kernel_entry = load_kernel(&cpu->env); |
| 614 | |
| 615 | init_boot_rom(); |
| 616 | init_boot_param(machine->smp.cpus, cpu->env.CP0_PRid); |
| 617 | } else { |
| 618 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, |
| 619 | machine->firmware ?: LOONGSON3_BIOSNAME); |
| 620 | if (filename) { |
| 621 | bios_size = load_image_targphys(filename, |
| 622 | virt_memmap[VIRT_BIOS_ROM].base, |
| 623 | virt_memmap[VIRT_BIOS_ROM].size, |
| 624 | NULL); |
| 625 | g_free(filename); |
| 626 | } else { |
| 627 | bios_size = -1; |
| 628 | } |
| 629 | |
| 630 | if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) && |
| 631 | !kernel_filename && !qtest_enabled()) { |
| 632 | error_report("Could not load MIPS bios '%s'", machine->firmware); |
| 633 | exit(1); |
| 634 | } |
| 635 | |
| 636 | fw_conf_init(); |
| 637 | } |
| 638 | |
| 639 | loongson3_virt_devices_init(machine, liointc); |
| 640 | } |
| 641 | |
| 642 | static void loongson3v_machine_class_init(ObjectClass *oc, const void *data) |
| 643 | { |
| 644 | MachineClass *mc = MACHINE_CLASS(oc); |
| 645 | |
| 646 | mc->desc = "Loongson-3 Virtualization Platform"; |
| 647 | mc->init = mips_loongson3_virt_init; |
| 648 | mc->block_default_type = IF_IDE; |
| 649 | mc->max_cpus = LOONGSON_MAX_VCPUS; |
| 650 | mc->default_ram_id = "loongson3.highram"; |
| 651 | mc->default_ram_size = 1600 * MiB; |
| 652 | mc->default_nic = "virtio-net-pci"; |
| 653 | } |
| 654 | |
| 655 | static const TypeInfo loongson3_machine_types[] = { |
| 656 | { |
| 657 | .name = TYPE_LOONGSON_MACHINE, |
| 658 | .parent = TYPE_MACHINE, |
| 659 | .instance_size = sizeof(LoongsonMachineState), |
| 660 | .class_init = loongson3v_machine_class_init, |
| 661 | } |
| 662 | }; |
| 663 | |
| 664 | DEFINE_TYPES(loongson3_machine_types) |