| 1 | /* |
| 2 | * QEMU MIPS interrupt support |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 5 | * of this software and associated documentation files (the "Software"), to deal |
| 6 | * in the Software without restriction, including without limitation the rights |
| 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 8 | * copies of the Software, and to permit persons to whom the Software is |
| 9 | * furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 20 | * THE SOFTWARE. |
| 21 | */ |
| 22 | |
| 23 | #include "qemu/osdep.h" |
| 24 | #include "qemu/main-loop.h" |
| 25 | #include "hw/core/irq.h" |
| 26 | #include "target/mips/cpu.h" |
| 27 | |
| 28 | static void cpu_mips_irq_request(void *opaque, int irq, int level) |
| 29 | { |
| 30 | MIPSCPU *cpu = opaque; |
| 31 | CPUMIPSState *env = &cpu->env; |
| 32 | CPUState *cs = CPU(cpu); |
| 33 | |
| 34 | if (irq < 0 || irq > 7) { |
| 35 | return; |
| 36 | } |
| 37 | |
| 38 | BQL_LOCK_GUARD(); |
| 39 | |
| 40 | if (level) { |
| 41 | env->CP0_Cause |= 1 << (irq + CP0Ca_IP); |
| 42 | } else { |
| 43 | env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); |
| 44 | } |
| 45 | |
| 46 | if (env->CP0_Cause & CP0Ca_IP_mask) { |
| 47 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
| 48 | } else { |
| 49 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 50 | } |
| 51 | } |
| 52 | |
| 53 | void cpu_mips_irq_init_cpu(MIPSCPU *cpu) |
| 54 | { |
| 55 | CPUMIPSState *env = &cpu->env; |
| 56 | qemu_irq *qi; |
| 57 | int i; |
| 58 | |
| 59 | qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8); |
| 60 | for (i = 0; i < 8; i++) { |
| 61 | env->irq[i] = qi[i]; |
| 62 | } |
| 63 | g_free(qi); |
| 64 | } |
| 65 | |
| 66 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) |
| 67 | { |
| 68 | if (irq < 0 || irq > 2) { |
| 69 | return; |
| 70 | } |
| 71 | |
| 72 | qemu_set_irq(env->irq[irq], level); |
| 73 | } |