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1 /*
2 * ASPEED Hash and Crypto Engine
3 *
4 * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates
5 * Copyright (C) 2021 IBM Corp.
6 *
7 * Joel Stanley <joel@jms.id.au>
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/cutils.h"
14 #include "qemu/log.h"
15 #include "qemu/error-report.h"
16 #include "qemu/iov.h"
17 #include "hw/misc/aspeed_hace.h"
18 #include "qapi/error.h"
19 #include "migration/vmstate.h"
20 #include "crypto/hash.h"
21 #include "crypto/cipher.h"
22 #include "hw/core/qdev-properties.h"
23 #include "hw/core/irq.h"
24 #include "trace.h"
25
26 /* Crypto engine registers */
27 #define R_CRYPT_SRC (0x00 / 4)
28 #define R_CRYPT_DEST (0x04 / 4)
29 #define R_CRYPT_CONTEXT (0x08 / 4)
30 #define R_CRYPT_DATA_LEN (0x0c / 4)
31 /* HACE0C[27:0] holds the crypto data length */
32 #define CRYPT_DATA_LEN_MASK 0x0FFFFFFF
33 #define R_CRYPT_CMD (0x10 / 4)
34 /* AES-GCM associated data length (HACE14) and tag write buffer (HACE18) */
35 #define R_CRYPT_GCM_ADD_LEN (0x14 / 4)
36 #define R_CRYPT_GCM_TAG (0x18 / 4)
37 /* Crypto engine command register (HACE10) bits */
38 #define CRYPT_CMD_ENCRYPT BIT(7)
39 #define CRYPT_CMD_ISR_EN BIT(12)
40 #define CRYPT_CMD_DES_SELECT BIT(16)
41 #define CRYPT_CMD_TRIPLE_DES BIT(17)
42 #define CRYPT_CMD_SRC_SG_CTRL BIT(18)
43 /* Operation mode HACE10[6:4] */
44 #define CRYPT_CMD_OP_MODE_MASK (0x7 << 4)
45 #define CRYPT_CMD_ECB (0x0 << 4)
46 #define CRYPT_CMD_CBC (0x1 << 4)
47 #define CRYPT_CMD_CTR (0x4 << 4)
48 #define CRYPT_CMD_GCM (0x5 << 4)
49 /* AES key length HACE10[3:2] */
50 #define CRYPT_CMD_AES_KEY_LEN_MASK (0x3 << 2)
51 #define CRYPT_CMD_AES256 (0x2 << 2)
52 #define CRYPT_CMD_AES192 (0x1 << 2)
53 #define CRYPT_CMD_AES128 (0x0 << 2)
54
55 /*
56 * Crypto context buffer layout (HACE08). The IV is at the start of the buffer
57 * (DES places its 8 byte IV at offset 8) and the cipher key at offset 0x10.
58 */
59 #define CRYPT_CTX_IV_OFFSET 0x00
60 #define CRYPT_CTX_DES_IV_OFFSET 0x08
61 #define CRYPT_CTX_KEY_OFFSET 0x10
62 #define CRYPT_CTX_SIZE 0x30
63
64 /* AES-GCM uses a 96-bit IV and a 128-bit authentication tag */
65 #define CRYPT_GCM_IV_LEN 12
66 #define CRYPT_GCM_TAG_LEN 16
67
68 /* AST2700 64-bit DMA high address registers for the crypto command */
69 #define R_CRYPT_SRC_HI (0x80 / 4)
70 #define R_CRYPT_DEST_HI (0x84 / 4)
71 #define R_CRYPT_CONTEXT_HI (0x88 / 4)
72 #define R_CRYPT_GCM_TAG_HI (0x8c / 4)
73
74 #define R_STATUS (0x1c / 4)
75 #define HASH_IRQ BIT(9)
76 #define CRYPT_IRQ BIT(12)
77 #define TAG_IRQ BIT(15)
78
79 #define R_HASH_SRC (0x20 / 4)
80 #define R_HASH_DIGEST (0x24 / 4)
81 #define R_HASH_KEY_BUFF (0x28 / 4)
82 #define R_HASH_SRC_LEN (0x2c / 4)
83 #define R_HASH_SRC_HI (0x90 / 4)
84 #define R_HASH_DIGEST_HI (0x94 / 4)
85 #define R_HASH_KEY_BUFF_HI (0x98 / 4)
86
87 #define R_HASH_CMD (0x30 / 4)
88 /* Hash algorithm selection */
89 #define HASH_ALGO_MASK (BIT(4) | BIT(5) | BIT(6))
90 #define HASH_ALGO_MD5 0
91 #define HASH_ALGO_SHA1 BIT(5)
92 #define HASH_ALGO_SHA224 BIT(6)
93 #define HASH_ALGO_SHA256 (BIT(4) | BIT(6))
94 #define HASH_ALGO_SHA512_SERIES (BIT(5) | BIT(6))
95 /* SHA512 algorithm selection */
96 #define SHA512_HASH_ALGO_MASK (BIT(10) | BIT(11) | BIT(12))
97 #define HASH_ALGO_SHA512_SHA512 0
98 #define HASH_ALGO_SHA512_SHA384 BIT(10)
99 #define HASH_ALGO_SHA512_SHA256 BIT(11)
100 #define HASH_ALGO_SHA512_SHA224 (BIT(10) | BIT(11))
101 /* HMAC modes */
102 #define HASH_HMAC_MASK (BIT(7) | BIT(8))
103 #define HASH_DIGEST 0
104 #define HASH_DIGEST_HMAC BIT(7)
105 #define HASH_DIGEST_ACCUM BIT(8)
106 #define HASH_HMAC_KEY (BIT(7) | BIT(8))
107 /* Cascaded operation modes */
108 #define HASH_ONLY 0
109 #define HASH_ONLY2 BIT(0)
110 #define HASH_CRYPT_THEN_HASH BIT(1)
111 #define HASH_HASH_THEN_CRYPT (BIT(0) | BIT(1))
112 /* Other cmd bits */
113 #define HASH_IRQ_EN BIT(9)
114 #define HASH_SG_EN BIT(18)
115 /* Scatter-gather data list */
116 #define SG_LIST_LEN_SIZE 4
117 #define SG_LIST_LEN_MASK 0x0FFFFFFF
118 #define SG_LIST_LEN_LAST BIT(31)
119 #define SG_LIST_ADDR_SIZE 4
120 #define SG_LIST_ADDR_MASK 0x7FFFFFFF
121 #define SG_LIST_ENTRY_SIZE (SG_LIST_LEN_SIZE + SG_LIST_ADDR_SIZE)
122
123 static const struct {
124 uint32_t mask;
125 QCryptoHashAlgo algo;
126 } hash_algo_map[] = {
127 { HASH_ALGO_MD5, QCRYPTO_HASH_ALGO_MD5 },
128 { HASH_ALGO_SHA1, QCRYPTO_HASH_ALGO_SHA1 },
129 { HASH_ALGO_SHA224, QCRYPTO_HASH_ALGO_SHA224 },
130 { HASH_ALGO_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
131 { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512,
132 QCRYPTO_HASH_ALGO_SHA512 },
133 { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384,
134 QCRYPTO_HASH_ALGO_SHA384 },
135 { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256,
136 QCRYPTO_HASH_ALGO_SHA256 },
137 };
138
139 static void hace_hexdump(const char *desc, const char *buf, size_t size)
140 {
141 g_autoptr(GString) str = g_string_sized_new(64);
142 size_t len;
143 size_t i;
144
145 for (i = 0; i < size; i += len) {
146 len = MIN(16, size - i);
147 g_string_truncate(str, 0);
148 qemu_hexdump_line(str, buf + i, len, 1, 4);
149 trace_aspeed_hace_hexdump(desc, i, str->str);
150 }
151 }
152
153 static void hace_iov_hexdump(const char *desc, const struct iovec *iov,
154 const unsigned int iov_cnt)
155 {
156 size_t size = 0;
157 char *buf;
158 int i;
159
160 for (i = 0; i < iov_cnt; i++) {
161 size += iov[i].iov_len;
162 }
163
164 buf = g_malloc(size);
165
166 if (!buf) {
167 return;
168 }
169
170 iov_to_buf(iov, iov_cnt, 0, buf, size);
171 hace_hexdump(desc, buf, size);
172 g_free(buf);
173 }
174
175 static int hash_algo_lookup(uint32_t reg)
176 {
177 int i;
178
179 reg &= HASH_ALGO_MASK | SHA512_HASH_ALGO_MASK;
180
181 for (i = 0; i < ARRAY_SIZE(hash_algo_map); i++) {
182 if (reg == hash_algo_map[i].mask) {
183 return hash_algo_map[i].algo;
184 }
185 }
186
187 return -1;
188 }
189
190 /**
191 * Check whether the request contains padding message.
192 *
193 * @param s aspeed hace state object
194 * @param iov iov of current request
195 * @param req_len length of the current request
196 * @param total_msg_len length of all acc_mode requests(excluding padding msg)
197 * @param pad_offset start offset of padding message
198 */
199 static bool has_padding(AspeedHACEState *s, struct iovec *iov,
200 hwaddr req_len, uint32_t *total_msg_len,
201 uint32_t *pad_offset)
202 {
203 /* Need at least 8 bytes to read the total message length field */
204 if (req_len < 8) {
205 qemu_log_mask(LOG_GUEST_ERROR,
206 "%s: invalid request length=0x%" HWADDR_PRIx "\n",
207 __func__, req_len);
208 return false;
209 }
210
211 *total_msg_len = (uint32_t)(ldq_be_p(iov->iov_base + req_len - 8) / 8);
212 /*
213 * SG_LIST_LEN_LAST asserted in the request length doesn't mean it is the
214 * last request. The last request should contain padding message.
215 * We check whether message contains padding by
216 * 1. Get total message length. If the current message contains
217 * padding, the last 8 bytes are total message length.
218 * 2. Check whether the total message length is valid.
219 * If it is valid, the value should less than or equal to
220 * total_req_len.
221 * 3. Current request len - padding_size to get padding offset.
222 * The padding message's first byte should be 0x80
223 */
224 if (*total_msg_len <= s->total_req_len) {
225 uint32_t padding_size = s->total_req_len - *total_msg_len;
226 uint8_t *padding = iov->iov_base;
227
228 if (padding_size > req_len) {
229 return false;
230 }
231
232 *pad_offset = req_len - padding_size;
233 if (padding[*pad_offset] == 0x80) {
234 return true;
235 }
236 }
237
238 return false;
239 }
240
241 static uint64_t hash_get_source_addr(AspeedHACEState *s)
242 {
243 AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
244 uint64_t src_addr = 0;
245
246 src_addr = deposit64(src_addr, 0, 32, s->regs[R_HASH_SRC]);
247 if (ahc->has_dma64) {
248 src_addr = deposit64(src_addr, 32, 32, s->regs[R_HASH_SRC_HI]);
249 }
250
251 return src_addr;
252 }
253
254 static bool hash_accumulate_len(AspeedHACEState *s, hwaddr plen)
255 {
256 if (plen > UINT32_MAX - s->total_req_len) {
257 qemu_log_mask(LOG_GUEST_ERROR,
258 "%s: total_req_len overflow, current=0x%x, adding=0x%"
259 HWADDR_PRIx "\n", __func__, s->total_req_len, plen);
260 return false;
261 }
262
263 s->total_req_len += plen;
264 return true;
265 }
266
267 static void hash_iov_unmap(AspeedHACEState *s, struct iovec *iov,
268 hwaddr *mapped_lens, int iov_count)
269 {
270 for (; iov_count > 0; iov_count--) {
271 address_space_unmap(&s->dram_as, iov[iov_count - 1].iov_base,
272 mapped_lens[iov_count - 1], false,
273 mapped_lens[iov_count - 1]);
274 }
275 }
276
277 static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov,
278 bool acc_mode, bool *acc_final_request,
279 hwaddr *mapped_lens)
280 {
281 uint32_t total_msg_len;
282 uint32_t pad_offset;
283 uint64_t src;
284 void *haddr;
285 hwaddr plen;
286 int iov_idx;
287
288 plen = s->regs[R_HASH_SRC_LEN];
289 src = hash_get_source_addr(s);
290 trace_aspeed_hace_hash_addr("src", src);
291 haddr = address_space_map(&s->dram_as, src, &plen, false,
292 MEMTXATTRS_UNSPECIFIED);
293 if (haddr == NULL) {
294 qemu_log_mask(LOG_GUEST_ERROR,
295 "%s: Unable to map address, addr=0x%" HWADDR_PRIx
296 " ,plen=0x%" HWADDR_PRIx "\n",
297 __func__, src, plen);
298 return -1;
299 }
300
301 iov[0].iov_base = haddr;
302 iov_idx = 1;
303 mapped_lens[0] = plen;
304
305 if (acc_mode) {
306 if (!hash_accumulate_len(s, plen)) {
307 hash_iov_unmap(s, iov, mapped_lens, 1);
308 return -1;
309 }
310
311 if (has_padding(s, &iov[0], plen, &total_msg_len,
312 &pad_offset)) {
313 /* Padding being present indicates the final request */
314 *acc_final_request = true;
315 iov[0].iov_len = pad_offset;
316 } else {
317 iov[0].iov_len = plen;
318 }
319 } else {
320 iov[0].iov_len = plen;
321 }
322
323 return iov_idx;
324 }
325
326 static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov,
327 bool acc_mode, bool *acc_final_request,
328 hwaddr *mapped_lens)
329 {
330 uint32_t total_msg_len;
331 uint32_t pad_offset;
332 uint32_t len = 0;
333 uint32_t sg_addr;
334 uint64_t src;
335 int iov_idx;
336 hwaddr plen;
337 void *haddr;
338 int iov_mapped = 0;
339
340 src = hash_get_source_addr(s);
341 for (iov_idx = 0; !(len & SG_LIST_LEN_LAST); iov_idx++) {
342 if (iov_idx == ASPEED_HACE_MAX_SG) {
343 qemu_log_mask(LOG_GUEST_ERROR,
344 "%s: Failed to set end of sg list marker\n",
345 __func__);
346 goto fail;
347 }
348
349 len = address_space_ldl_le(&s->dram_as, src,
350 MEMTXATTRS_UNSPECIFIED, NULL);
351 sg_addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
352 MEMTXATTRS_UNSPECIFIED, NULL);
353 sg_addr &= SG_LIST_ADDR_MASK;
354 trace_aspeed_hace_hash_sg(iov_idx, src, sg_addr, len);
355 /*
356 * To maintain compatibility with older SoCs such as the AST2600,
357 * the AST2700 HW automatically set bit 34 of the 64-bit sg_addr.
358 * As a result, the firmware only needs to provide a 32-bit sg_addr
359 * containing bits [31:0]. This is sufficient for the AST2700, as
360 * it uses a DRAM offset rather than a DRAM address.
361 */
362 plen = len & SG_LIST_LEN_MASK;
363 haddr = address_space_map(&s->dram_as, sg_addr, &plen, false,
364 MEMTXATTRS_UNSPECIFIED);
365
366 if (haddr == NULL) {
367 qemu_log_mask(LOG_GUEST_ERROR,
368 "%s: Unable to map address, sg_addr=0x%x, "
369 "plen=0x%" HWADDR_PRIx "\n",
370 __func__, sg_addr, plen);
371 goto fail;
372 }
373
374 src += SG_LIST_ENTRY_SIZE;
375
376 iov[iov_idx].iov_base = haddr;
377 iov_mapped = iov_idx + 1;
378 mapped_lens[iov_idx] = plen;
379 if (acc_mode) {
380 if (!hash_accumulate_len(s, plen)) {
381 goto fail;
382 }
383
384 if (has_padding(s, &iov[iov_idx], plen, &total_msg_len,
385 &pad_offset)) {
386 /* Padding being present indicates the final request */
387 *acc_final_request = true;
388 iov[iov_idx].iov_len = pad_offset;
389 } else {
390 iov[iov_idx].iov_len = plen;
391 }
392 } else {
393 iov[iov_idx].iov_len = plen;
394 }
395 }
396
397 return iov_idx;
398
399 fail:
400 hash_iov_unmap(s, iov, mapped_lens, iov_mapped);
401 return -1;
402 }
403
404 static uint64_t hash_get_digest_addr(AspeedHACEState *s)
405 {
406 AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
407 uint64_t digest_addr = 0;
408
409 digest_addr = deposit64(digest_addr, 0, 32, s->regs[R_HASH_DIGEST]);
410 if (ahc->has_dma64) {
411 digest_addr = deposit64(digest_addr, 32, 32, s->regs[R_HASH_DIGEST_HI]);
412 }
413
414 return digest_addr;
415 }
416
417 static void hash_write_digest_and_unmap_iov(AspeedHACEState *s,
418 struct iovec *iov,
419 int iov_idx,
420 hwaddr *mapped_lens,
421 uint8_t *digest_buf,
422 size_t digest_len)
423 {
424 uint64_t digest_addr = 0;
425
426 digest_addr = hash_get_digest_addr(s);
427 trace_aspeed_hace_hash_addr("digest", digest_addr);
428 if (address_space_write(&s->dram_as, digest_addr,
429 MEMTXATTRS_UNSPECIFIED,
430 digest_buf, digest_len)) {
431 qemu_log_mask(LOG_GUEST_ERROR,
432 "%s: Failed to write digest to 0x%" HWADDR_PRIx "\n",
433 __func__, digest_addr);
434 }
435
436 if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
437 hace_hexdump("digest", (char *)digest_buf, digest_len);
438 }
439
440 hash_iov_unmap(s, iov, mapped_lens, iov_idx);
441 }
442
443 static void hash_execute_non_acc_mode(AspeedHACEState *s, int algo,
444 struct iovec *iov, int iov_idx,
445 hwaddr *mapped_lens)
446 {
447 g_autofree uint8_t *digest_buf = NULL;
448 Error *local_err = NULL;
449 size_t digest_len = 0;
450
451 if (qcrypto_hash_bytesv(algo, iov, iov_idx, &digest_buf,
452 &digest_len, &local_err) < 0) {
453 qemu_log_mask(LOG_GUEST_ERROR,
454 "%s: qcrypto hash bytesv failed : %s",
455 __func__, error_get_pretty(local_err));
456 error_free(local_err);
457 hash_iov_unmap(s, iov, mapped_lens, iov_idx);
458 return;
459 }
460
461 hash_write_digest_and_unmap_iov(s, iov, iov_idx, mapped_lens,
462 digest_buf, digest_len);
463 }
464
465 static void hash_execute_acc_mode(AspeedHACEState *s, int algo,
466 struct iovec *iov, int iov_idx,
467 bool final_request, hwaddr *mapped_lens)
468 {
469 g_autofree uint8_t *digest_buf = NULL;
470 Error *local_err = NULL;
471 size_t digest_len = 0;
472
473 trace_aspeed_hace_hash_execute_acc_mode(final_request);
474
475 if (s->hash_ctx == NULL) {
476 s->hash_ctx = qcrypto_hash_new(algo, &local_err);
477 if (s->hash_ctx == NULL) {
478 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto hash new failed : %s",
479 __func__, error_get_pretty(local_err));
480 error_free(local_err);
481 hash_iov_unmap(s, iov, mapped_lens, iov_idx);
482 return;
483 }
484 }
485
486 if (qcrypto_hash_updatev(s->hash_ctx, iov, iov_idx, &local_err) < 0) {
487 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto hash updatev failed : %s",
488 __func__, error_get_pretty(local_err));
489 error_free(local_err);
490 hash_iov_unmap(s, iov, mapped_lens, iov_idx);
491 return;
492 }
493
494 if (final_request) {
495 if (qcrypto_hash_finalize_bytes(s->hash_ctx, &digest_buf,
496 &digest_len, &local_err)) {
497 qemu_log_mask(LOG_GUEST_ERROR,
498 "%s: qcrypto hash finalize bytes failed : %s",
499 __func__, error_get_pretty(local_err));
500 error_free(local_err);
501 local_err = NULL;
502 }
503
504 qcrypto_hash_free(s->hash_ctx);
505
506 s->hash_ctx = NULL;
507 s->total_req_len = 0;
508 }
509
510 hash_write_digest_and_unmap_iov(s, iov, iov_idx, mapped_lens,
511 digest_buf, digest_len);
512 }
513
514 static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
515 bool acc_mode)
516 {
517 QEMU_UNINITIALIZED struct iovec iov[ASPEED_HACE_MAX_SG];
518 hwaddr mapped_lens[ASPEED_HACE_MAX_SG] = { 0 };
519 bool acc_final_request = false;
520 int iov_idx = -1;
521
522 /* Prepares the iov for hashing operations based on the selected mode */
523 if (sg_mode) {
524 iov_idx = hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_request,
525 mapped_lens);
526 } else {
527 iov_idx = hash_prepare_direct_iov(s, iov, acc_mode,
528 &acc_final_request, mapped_lens);
529 }
530
531 if (iov_idx <= 0) {
532 qemu_log_mask(LOG_GUEST_ERROR,
533 "%s: Failed to prepare iov\n", __func__);
534 return;
535 }
536
537 if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
538 hace_iov_hexdump("plaintext", iov, iov_idx);
539 }
540
541 /* Executes the hash operation */
542 if (acc_mode) {
543 hash_execute_acc_mode(s, algo, iov, iov_idx, acc_final_request,
544 mapped_lens);
545 } else {
546 hash_execute_non_acc_mode(s, algo, iov, iov_idx, mapped_lens);
547 }
548 }
549
550 static bool crypt_aes_alg(uint32_t cmd, QCryptoCipherAlgo *alg, size_t *keylen)
551 {
552 switch (cmd & CRYPT_CMD_AES_KEY_LEN_MASK) {
553 case CRYPT_CMD_AES128:
554 *alg = QCRYPTO_CIPHER_ALGO_AES_128;
555 *keylen = 16;
556 break;
557 case CRYPT_CMD_AES192:
558 *alg = QCRYPTO_CIPHER_ALGO_AES_192;
559 *keylen = 24;
560 break;
561 case CRYPT_CMD_AES256:
562 *alg = QCRYPTO_CIPHER_ALGO_AES_256;
563 *keylen = 32;
564 break;
565 default:
566 return false;
567 }
568
569 return true;
570 }
571
572 /*
573 * Decode the crypto command register into a libqcrypto algorithm/mode pair
574 * and the block/IV geometry. Returns false for unsupported selections.
575 */
576 static bool crypt_decode_cmd(uint32_t cmd, QCryptoCipherAlgo *alg,
577 QCryptoCipherMode *mode, size_t *keylen,
578 size_t *blocklen, size_t *iv_offset)
579 {
580 if (cmd & CRYPT_CMD_DES_SELECT) {
581 *blocklen = 8;
582 *iv_offset = CRYPT_CTX_DES_IV_OFFSET;
583 if (cmd & CRYPT_CMD_TRIPLE_DES) {
584 *alg = QCRYPTO_CIPHER_ALGO_3DES;
585 *keylen = 24;
586 } else {
587 *alg = QCRYPTO_CIPHER_ALGO_DES;
588 *keylen = 8;
589 }
590 } else {
591 *blocklen = 16;
592 *iv_offset = CRYPT_CTX_IV_OFFSET;
593 if (!crypt_aes_alg(cmd, alg, keylen)) {
594 return false;
595 }
596 }
597
598 switch (cmd & CRYPT_CMD_OP_MODE_MASK) {
599 case CRYPT_CMD_ECB:
600 *mode = QCRYPTO_CIPHER_MODE_ECB;
601 break;
602 case CRYPT_CMD_CBC:
603 *mode = QCRYPTO_CIPHER_MODE_CBC;
604 break;
605 case CRYPT_CMD_CTR:
606 *mode = QCRYPTO_CIPHER_MODE_CTR;
607 break;
608 case CRYPT_CMD_GCM:
609 *mode = QCRYPTO_CIPHER_MODE_GCM;
610 break;
611 default:
612 return false;
613 }
614
615 return true;
616 }
617
618 /*
619 * Direct access mode: the source/destination register (HACE00/HACE04) points
620 * at a single contiguous buffer in DRAM. Copy @len bytes between it and the
621 * bounce buffer @buf; when @to_dram is true @buf is written out, otherwise it
622 * is read in. Returns true on success.
623 */
624 static bool crypt_prepare_direct(AspeedHACEState *s, uint64_t addr,
625 uint8_t *buf, uint32_t len, bool to_dram)
626 {
627 return !address_space_rw(&s->dram_as, addr, MEMTXATTRS_UNSPECIFIED,
628 buf, len, to_dram);
629 }
630
631 /*
632 * Scatter-gather mode: the source/destination register points at an SG list
633 * whose entries are a length word (SG_LIST_LEN_LAST flags the final entry)
634 * followed by a DRAM address, matching the hash engine layout. Gather @len
635 * bytes into @buf, or scatter @buf back out when @to_dram is true.
636 * Returns true on success.
637 */
638 static bool crypt_prepare_sg(AspeedHACEState *s, uint64_t addr,
639 uint8_t *buf, uint32_t len, bool to_dram)
640 {
641 uint32_t copied = 0;
642 uint32_t sg_addr;
643 uint32_t sg_len;
644 uint32_t entry;
645 int i;
646
647 for (i = 0; i < ASPEED_HACE_MAX_SG && copied < len; i++) {
648 entry = address_space_ldl_le(&s->dram_as, addr,
649 MEMTXATTRS_UNSPECIFIED, NULL);
650 sg_addr = address_space_ldl_le(&s->dram_as, addr + SG_LIST_LEN_SIZE,
651 MEMTXATTRS_UNSPECIFIED, NULL);
652 sg_len = entry & SG_LIST_LEN_MASK;
653
654 sg_addr &= SG_LIST_ADDR_MASK;
655 addr += SG_LIST_ENTRY_SIZE;
656
657 if (sg_len > len - copied) {
658 sg_len = len - copied;
659 }
660 if (address_space_rw(&s->dram_as, sg_addr, MEMTXATTRS_UNSPECIFIED,
661 buf + copied, sg_len, to_dram)) {
662 return false;
663 }
664 copied += sg_len;
665
666 if (entry & SG_LIST_LEN_LAST) {
667 break;
668 }
669 }
670
671 return copied == len;
672 }
673
674 /*
675 * Add @add to the big-endian counter block @ctr (@len bytes) in place, so the
676 * CTR mode counter can be advanced by the number of blocks just consumed.
677 */
678 static void crypt_be_add(uint8_t *ctr, size_t len, uint64_t add)
679 {
680 size_t i = len;
681
682 while (i > 0 && add) {
683 i--;
684 add += ctr[i];
685 ctr[i] = add & 0xff;
686 add >>= 8;
687 }
688 }
689
690 static uint64_t crypt_get_addr(AspeedHACEState *s, int reg, int reg_hi)
691 {
692 AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
693 uint64_t addr;
694
695 addr = deposit64(0, 0, 32, s->regs[reg]);
696 if (ahc->has_dma64) {
697 addr = deposit64(addr, 32, 32, s->regs[reg_hi]);
698 }
699
700 return addr;
701 }
702
703 /*
704 * Perform an AES/DES/3DES ECB/CBC/CTR or AES-GCM operation. The source and
705 * destination are either single contiguous buffers (direct access mode) or
706 * scatter-gather lists (HACE10[18]/[19]), addressed by HACE00/HACE04; the
707 * IV/key come from the context buffer (HACE08). For CBC and CTR the resulting
708 * chaining state is written back to the context buffer so the driver can
709 * continue; for GCM the authentication tag is written to the tag buffer.
710 */
711 static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
712 {
713 bool sg_mode = cmd & CRYPT_CMD_SRC_SG_CTRL;
714 uint32_t len = s->regs[R_CRYPT_DATA_LEN];
715 bool encrypt = cmd & CRYPT_CMD_ENCRYPT;
716 g_autoptr(QCryptoCipher) cipher = NULL;
717 g_autofree uint8_t *src_buf = NULL;
718 g_autofree uint8_t *dst_buf = NULL;
719 uint8_t tag[CRYPT_GCM_TAG_LEN];
720 uint8_t ctx[CRYPT_CTX_SIZE];
721 Error *local_err = NULL;
722 QCryptoCipherMode mode;
723 QCryptoCipherAlgo alg;
724 const uint8_t *next_iv;
725 uint64_t ctx_addr;
726 uint64_t src_addr;
727 uint64_t dst_addr;
728 uint64_t tag_addr;
729 uint32_t aad_len;
730 size_t iv_offset;
731 size_t blocklen;
732 size_t buf_len;
733 size_t keylen;
734 size_t ivlen;
735 bool status;
736
737 if (len == 0) {
738 return;
739 }
740
741 if (!crypt_decode_cmd(cmd, &alg, &mode, &keylen, &blocklen, &iv_offset)) {
742 qemu_log_mask(LOG_UNIMP,
743 "%s: Unsupported crypt command 0x%x\n", __func__, cmd);
744 return;
745 }
746
747 if (!qcrypto_cipher_supports(alg, mode)) {
748 qemu_log_mask(LOG_UNIMP,
749 "%s: cipher mode not supported by the crypto backend\n",
750 __func__);
751 return;
752 }
753
754 /* GCM uses a 96-bit IV; the block modes use a full-block IV. */
755 ivlen = (mode == QCRYPTO_CIPHER_MODE_GCM) ? CRYPT_GCM_IV_LEN : blocklen;
756
757 /*
758 * The hardware GCM path is only exercised without associated data (the
759 * driver falls back to software when there is any), so AAD is not modelled.
760 */
761 aad_len = s->regs[R_CRYPT_GCM_ADD_LEN];
762 if (mode == QCRYPTO_CIPHER_MODE_GCM && aad_len != 0) {
763 qemu_log_mask(LOG_UNIMP,
764 "%s: GCM associated data is not implemented\n", __func__);
765 return;
766 }
767
768 /* Fetch the IV and key from the context buffer in DRAM. */
769 ctx_addr = crypt_get_addr(s, R_CRYPT_CONTEXT, R_CRYPT_CONTEXT_HI);
770 if (address_space_read(&s->dram_as, ctx_addr, MEMTXATTRS_UNSPECIFIED,
771 ctx, sizeof(ctx))) {
772 qemu_log_mask(LOG_GUEST_ERROR,
773 "%s: Failed to read context, addr=0x%" HWADDR_PRIx "\n",
774 __func__, ctx_addr);
775 return;
776 }
777
778 if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
779 hace_hexdump("context", (char *)ctx, sizeof(ctx));
780 }
781
782 cipher = qcrypto_cipher_new(alg, mode, ctx + CRYPT_CTX_KEY_OFFSET, keylen,
783 &local_err);
784 if (cipher == NULL) {
785 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto cipher new failed: %s\n",
786 __func__, error_get_pretty(local_err));
787 error_free(local_err);
788 return;
789 }
790
791 if (mode != QCRYPTO_CIPHER_MODE_ECB &&
792 qcrypto_cipher_setiv(cipher, ctx + iv_offset, ivlen,
793 &local_err) < 0) {
794 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto cipher setiv failed: %s\n",
795 __func__, error_get_pretty(local_err));
796 error_free(local_err);
797 return;
798 }
799
800 /*
801 * Round the working buffers up to a whole block. Block modes are already
802 * block-aligned; the stream-like CTR mode may leave a partial final block
803 * that the engine still processes a full block at a time. GCM handles a
804 * partial final block itself, so it operates on the exact length.
805 */
806 buf_len = (mode == QCRYPTO_CIPHER_MODE_GCM) ?
807 len : QEMU_ALIGN_UP(len, blocklen);
808 src_buf = g_malloc0(buf_len);
809 dst_buf = g_malloc0(buf_len);
810
811 /* Gather the source into the bounce buffer, per the selected mode. */
812 src_addr = crypt_get_addr(s, R_CRYPT_SRC, R_CRYPT_SRC_HI);
813 if (sg_mode) {
814 status = crypt_prepare_sg(s, src_addr, src_buf, len, false);
815 } else {
816 status = crypt_prepare_direct(s, src_addr, src_buf, len, false);
817 }
818 if (!status) {
819 qemu_log_mask(LOG_GUEST_ERROR,
820 "%s: Failed to read src, addr=0x%" HWADDR_PRIx "\n",
821 __func__, src_addr);
822 return;
823 }
824
825 if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
826 hace_hexdump("src", (char *)src_buf, len);
827 }
828
829 if (encrypt) {
830 if (qcrypto_cipher_encrypt(cipher, src_buf, dst_buf, buf_len,
831 &local_err) < 0) {
832 qemu_log_mask(LOG_GUEST_ERROR, "%s: encrypt failed: %s\n",
833 __func__, error_get_pretty(local_err));
834 error_free(local_err);
835 return;
836 }
837 } else {
838 if (qcrypto_cipher_decrypt(cipher, src_buf, dst_buf, buf_len,
839 &local_err) < 0) {
840 qemu_log_mask(LOG_GUEST_ERROR, "%s: decrypt failed: %s\n",
841 __func__, error_get_pretty(local_err));
842 error_free(local_err);
843 return;
844 }
845 }
846
847 /* Scatter the result back out, per the selected mode. */
848 dst_addr = crypt_get_addr(s, R_CRYPT_DEST, R_CRYPT_DEST_HI);
849 if (sg_mode) {
850 status = crypt_prepare_sg(s, dst_addr, dst_buf, len, true);
851 } else {
852 status = crypt_prepare_direct(s, dst_addr, dst_buf, len, true);
853 }
854 if (!status) {
855 qemu_log_mask(LOG_GUEST_ERROR,
856 "%s: Failed to write dst, addr=0x%" HWADDR_PRIx "\n",
857 __func__, dst_addr);
858 return;
859 }
860
861 if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
862 hace_hexdump("dst", (char *)dst_buf, len);
863 }
864
865 if (mode == QCRYPTO_CIPHER_MODE_CBC) {
866 /*
867 * CBC chains on the last ciphertext block: the final block of the
868 * output when encrypting, or of the input when decrypting. Write it
869 * back as the IV for the next request.
870 */
871 next_iv = (encrypt ? dst_buf : src_buf) + buf_len - blocklen;
872 if (address_space_write(&s->dram_as, ctx_addr + iv_offset,
873 MEMTXATTRS_UNSPECIFIED, next_iv, blocklen)) {
874 qemu_log_mask(LOG_GUEST_ERROR,
875 "%s: Failed to write IV, addr=0x%" HWADDR_PRIx "\n",
876 __func__, ctx_addr + iv_offset);
877 }
878 } else if (mode == QCRYPTO_CIPHER_MODE_CTR) {
879 /*
880 * CTR chains on the counter, which advances by one per block. Add the
881 * number of blocks processed (buf_len / blocklen) and write it back.
882 */
883 crypt_be_add(ctx + iv_offset, blocklen, buf_len / blocklen);
884 if (address_space_write(&s->dram_as, ctx_addr + iv_offset,
885 MEMTXATTRS_UNSPECIFIED, ctx + iv_offset,
886 blocklen)) {
887 qemu_log_mask(LOG_GUEST_ERROR,
888 "%s: Failed to write IV, addr=0x%" HWADDR_PRIx "\n",
889 __func__, ctx_addr + iv_offset);
890 }
891 } else if (mode == QCRYPTO_CIPHER_MODE_GCM) {
892 /*
893 * GCM authenticates the message and writes the resulting tag to the
894 * dedicated tag buffer (HACE18/HACE8C).
895 */
896 if (qcrypto_cipher_gettag(cipher, tag, sizeof(tag), &local_err) < 0) {
897 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto cipher gettag failed: "
898 "%s\n", __func__, error_get_pretty(local_err));
899 error_free(local_err);
900 return;
901 }
902 tag_addr = crypt_get_addr(s, R_CRYPT_GCM_TAG, R_CRYPT_GCM_TAG_HI);
903 if (address_space_write(&s->dram_as, tag_addr, MEMTXATTRS_UNSPECIFIED,
904 tag, sizeof(tag))) {
905 qemu_log_mask(LOG_GUEST_ERROR,
906 "%s: Failed to write tag, addr=0x%" HWADDR_PRIx "\n",
907 __func__, tag_addr);
908 }
909 }
910 }
911
912 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int size)
913 {
914 AspeedHACEState *s = ASPEED_HACE(opaque);
915
916 addr >>= 2;
917
918 trace_aspeed_hace_read(addr << 2, s->regs[addr]);
919
920 return s->regs[addr];
921 }
922
923 static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
924 unsigned int size)
925 {
926 AspeedHACEState *s = ASPEED_HACE(opaque);
927 AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
928
929 addr >>= 2;
930
931 trace_aspeed_hace_write(addr << 2, data);
932
933 switch (addr) {
934 case R_STATUS:
935 if (data & HASH_IRQ) {
936 data &= ~HASH_IRQ;
937
938 if (s->regs[addr] & HASH_IRQ) {
939 qemu_irq_lower(s->irq);
940 }
941 }
942 if (data & CRYPT_IRQ) {
943 data &= ~CRYPT_IRQ;
944
945 if (s->regs[addr] & CRYPT_IRQ) {
946 qemu_irq_lower(s->irq);
947 }
948 }
949 break;
950 case R_CRYPT_SRC:
951 case R_CRYPT_DEST:
952 case R_CRYPT_CONTEXT:
953 case R_CRYPT_GCM_TAG:
954 data &= ahc->src_mask;
955 break;
956 case R_CRYPT_DATA_LEN:
957 case R_CRYPT_GCM_ADD_LEN:
958 data &= CRYPT_DATA_LEN_MASK;
959 break;
960 case R_HASH_SRC:
961 data &= ahc->src_mask;
962 break;
963 case R_HASH_DIGEST:
964 data &= ahc->dest_mask;
965 break;
966 case R_HASH_KEY_BUFF:
967 data &= ahc->key_mask;
968 break;
969 case R_HASH_SRC_LEN:
970 data &= 0x0FFFFFFF;
971 break;
972 case R_HASH_CMD: {
973 int algo;
974 data &= ahc->hash_mask;
975
976 if ((data & HASH_DIGEST_HMAC)) {
977 qemu_log_mask(LOG_UNIMP,
978 "%s: HMAC mode not implemented\n",
979 __func__);
980 }
981 if (data & BIT(1)) {
982 qemu_log_mask(LOG_UNIMP,
983 "%s: Cascaded mode not implemented\n",
984 __func__);
985 }
986 algo = hash_algo_lookup(data);
987 if (algo < 0) {
988 qemu_log_mask(LOG_GUEST_ERROR,
989 "%s: Invalid hash algorithm selection 0x%"PRIx64"\n",
990 __func__, data & ahc->hash_mask);
991 } else {
992 do_hash_operation(s, algo, data & HASH_SG_EN,
993 ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM));
994 }
995
996 /*
997 * Set status bits to indicate completion. Testing shows hardware sets
998 * these irrespective of HASH_IRQ_EN.
999 */
1000 s->regs[R_STATUS] |= HASH_IRQ;
1001
1002 if (data & HASH_IRQ_EN) {
1003 qemu_irq_raise(s->irq);
1004 }
1005 break;
1006 }
1007 case R_CRYPT_CMD:
1008 do_crypt_operation(s, data);
1009
1010 /* Hardware raises the crypt interrupt once the command finishes. */
1011 s->regs[R_STATUS] |= CRYPT_IRQ;
1012 if (data & CRYPT_CMD_ISR_EN) {
1013 qemu_irq_raise(s->irq);
1014 }
1015 break;
1016 case R_HASH_SRC_HI:
1017 data &= ahc->src_hi_mask;
1018 break;
1019 case R_HASH_DIGEST_HI:
1020 data &= ahc->dest_hi_mask;
1021 break;
1022 case R_HASH_KEY_BUFF_HI:
1023 data &= ahc->key_hi_mask;
1024 break;
1025 case R_CRYPT_SRC_HI:
1026 data &= ahc->src_hi_mask;
1027 break;
1028 case R_CRYPT_DEST_HI:
1029 case R_CRYPT_GCM_TAG_HI:
1030 data &= ahc->dest_hi_mask;
1031 break;
1032 case R_CRYPT_CONTEXT_HI:
1033 data &= ahc->key_hi_mask;
1034 break;
1035 default:
1036 break;
1037 }
1038
1039 s->regs[addr] = data;
1040 }
1041
1042 static const MemoryRegionOps aspeed_hace_ops = {
1043 .read = aspeed_hace_read,
1044 .write = aspeed_hace_write,
1045 .endianness = DEVICE_LITTLE_ENDIAN,
1046 .valid = {
1047 .min_access_size = 1,
1048 .max_access_size = 4,
1049 },
1050 };
1051
1052 static void aspeed_hace_reset_hold(Object *obj, ResetType type)
1053 {
1054 AspeedHACEState *s = ASPEED_HACE(obj);
1055 AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
1056
1057 if (s->hash_ctx != NULL) {
1058 qcrypto_hash_free(s->hash_ctx);
1059 s->hash_ctx = NULL;
1060 }
1061
1062 memset(s->regs, 0, ahc->nr_regs << 2);
1063 s->total_req_len = 0;
1064 }
1065
1066 static void aspeed_hace_realize(DeviceState *dev, Error **errp)
1067 {
1068 AspeedHACEState *s = ASPEED_HACE(dev);
1069 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1070 AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
1071
1072 sysbus_init_irq(sbd, &s->irq);
1073
1074 s->regs = g_new(uint32_t, ahc->nr_regs);
1075 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s,
1076 TYPE_ASPEED_HACE, ahc->nr_regs << 2);
1077
1078 if (!s->dram_mr) {
1079 error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set");
1080 return;
1081 }
1082
1083 address_space_init(&s->dram_as, s->dram_mr, "dram");
1084
1085 sysbus_init_mmio(sbd, &s->iomem);
1086 }
1087
1088 static const Property aspeed_hace_properties[] = {
1089 DEFINE_PROP_LINK("dram", AspeedHACEState, dram_mr,
1090 TYPE_MEMORY_REGION, MemoryRegion *),
1091 };
1092
1093
1094 static const VMStateDescription vmstate_aspeed_hace = {
1095 .name = TYPE_ASPEED_HACE,
1096 .version_id = 2,
1097 .minimum_version_id = 2,
1098 .fields = (const VMStateField[]) {
1099 VMSTATE_UINT32(total_req_len, AspeedHACEState),
1100 VMSTATE_END_OF_LIST(),
1101 }
1102 };
1103
1104 static void aspeed_hace_unrealize(DeviceState *dev)
1105 {
1106 AspeedHACEState *s = ASPEED_HACE(dev);
1107
1108 g_free(s->regs);
1109 s->regs = NULL;
1110 }
1111
1112 static void aspeed_hace_class_init(ObjectClass *klass, const void *data)
1113 {
1114 DeviceClass *dc = DEVICE_CLASS(klass);
1115 ResettableClass *rc = RESETTABLE_CLASS(klass);
1116
1117 dc->realize = aspeed_hace_realize;
1118 dc->unrealize = aspeed_hace_unrealize;
1119 rc->phases.hold = aspeed_hace_reset_hold;
1120 device_class_set_props(dc, aspeed_hace_properties);
1121 dc->vmsd = &vmstate_aspeed_hace;
1122 }
1123
1124 static void aspeed_ast2400_hace_class_init(ObjectClass *klass, const void *data)
1125 {
1126 DeviceClass *dc = DEVICE_CLASS(klass);
1127 AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
1128
1129 dc->desc = "AST2400 Hash and Crypto Engine";
1130
1131 ahc->nr_regs = 0x64 >> 2;
1132 ahc->src_mask = 0x0FFFFFFF;
1133 ahc->dest_mask = 0x0FFFFFF8;
1134 ahc->key_mask = 0x0FFFFFC0;
1135 ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */
1136 }
1137
1138 static void aspeed_ast2500_hace_class_init(ObjectClass *klass, const void *data)
1139 {
1140 DeviceClass *dc = DEVICE_CLASS(klass);
1141 AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
1142
1143 dc->desc = "AST2500 Hash and Crypto Engine";
1144
1145 ahc->nr_regs = 0x64 >> 2;
1146 ahc->src_mask = 0x3fffffff;
1147 ahc->dest_mask = 0x3ffffff8;
1148 ahc->key_mask = 0x3FFFFFC0;
1149 ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */
1150 }
1151
1152 static void aspeed_ast2600_hace_class_init(ObjectClass *klass, const void *data)
1153 {
1154 DeviceClass *dc = DEVICE_CLASS(klass);
1155 AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
1156
1157 dc->desc = "AST2600 Hash and Crypto Engine";
1158
1159 ahc->nr_regs = 0x64 >> 2;
1160 ahc->src_mask = 0x7FFFFFFF;
1161 ahc->dest_mask = 0x7FFFFFF8;
1162 ahc->key_mask = 0x7FFFFFF8;
1163 ahc->hash_mask = 0x00147FFF;
1164 }
1165
1166 static void aspeed_ast1030_hace_class_init(ObjectClass *klass, const void *data)
1167 {
1168 DeviceClass *dc = DEVICE_CLASS(klass);
1169 AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
1170
1171 dc->desc = "AST1030 Hash and Crypto Engine";
1172
1173 ahc->nr_regs = 0x64 >> 2;
1174 ahc->src_mask = 0x7FFFFFFF;
1175 ahc->dest_mask = 0x7FFFFFF8;
1176 ahc->key_mask = 0x7FFFFFF8;
1177 ahc->hash_mask = 0x00147FFF;
1178 }
1179
1180 static void aspeed_ast2700_hace_class_init(ObjectClass *klass, const void *data)
1181 {
1182 DeviceClass *dc = DEVICE_CLASS(klass);
1183 AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
1184
1185 dc->desc = "AST2700 Hash and Crypto Engine";
1186
1187 ahc->nr_regs = 0x9C >> 2;
1188 ahc->src_mask = 0x7FFFFFFF;
1189 ahc->dest_mask = 0x7FFFFFF8;
1190 ahc->key_mask = 0x7FFFFFF8;
1191 ahc->hash_mask = 0x00147FFF;
1192
1193 /*
1194 * The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM
1195 * addressable range from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range
1196 * fits within 34 bits, only bits [33:0] are needed to store the DRAM
1197 * offset. To optimize address storage, the high physical address bits
1198 * [1:0] of the source, digest and key buffer addresses are stored as
1199 * dram_offset bits [33:32].
1200 *
1201 * This approach eliminates the need to reduce the high part of the DRAM
1202 * physical address for DMA operations. Previously, this was calculated as
1203 * (high physical address bits [7:0] - 4), since the DRAM start address is
1204 * 0x4_00000000, making the high part address [7:0] - 4.
1205 */
1206 ahc->src_hi_mask = 0x00000003;
1207 ahc->dest_hi_mask = 0x00000003;
1208 ahc->key_hi_mask = 0x00000003;
1209
1210 ahc->has_dma64 = true;
1211 }
1212
1213 static const TypeInfo aspeed_hace_types[] = {
1214 {
1215 .name = TYPE_ASPEED_HACE,
1216 .parent = TYPE_SYS_BUS_DEVICE,
1217 .instance_size = sizeof(AspeedHACEState),
1218 .class_init = aspeed_hace_class_init,
1219 .class_size = sizeof(AspeedHACEClass),
1220 },
1221 {
1222 .name = TYPE_ASPEED_AST1030_HACE,
1223 .parent = TYPE_ASPEED_HACE,
1224 .class_init = aspeed_ast1030_hace_class_init,
1225 },
1226 {
1227 .name = TYPE_ASPEED_AST2400_HACE,
1228 .parent = TYPE_ASPEED_HACE,
1229 .class_init = aspeed_ast2400_hace_class_init,
1230 },
1231 {
1232 .name = TYPE_ASPEED_AST2500_HACE,
1233 .parent = TYPE_ASPEED_HACE,
1234 .class_init = aspeed_ast2500_hace_class_init,
1235 },
1236 {
1237 .name = TYPE_ASPEED_AST2600_HACE,
1238 .parent = TYPE_ASPEED_HACE,
1239 .class_init = aspeed_ast2600_hace_class_init,
1240 },
1241 {
1242 .name = TYPE_ASPEED_AST2700_HACE,
1243 .parent = TYPE_ASPEED_HACE,
1244 .class_init = aspeed_ast2700_hace_class_init,
1245 }
1246 };
1247
1248 DEFINE_TYPES(aspeed_hace_types)