| 1 | /* |
| 2 | * ASPEED Secure Boot Controller |
| 3 | * |
| 4 | * Copyright (C) 2021-2022 IBM Corp. |
| 5 | * |
| 6 | * Joel Stanley <joel@jms.id.au> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | */ |
| 10 | |
| 11 | #include "qemu/osdep.h" |
| 12 | #include "qemu/log.h" |
| 13 | #include "qemu/error-report.h" |
| 14 | #include "hw/core/qdev-properties.h" |
| 15 | #include "hw/misc/aspeed_sbc.h" |
| 16 | #include "qapi/error.h" |
| 17 | #include "migration/vmstate.h" |
| 18 | #include "trace.h" |
| 19 | |
| 20 | #define R_PROT (0x000 / 4) |
| 21 | #define R_CMD (0x004 / 4) |
| 22 | #define R_ADDR (0x010 / 4) |
| 23 | #define R_STATUS (0x014 / 4) |
| 24 | #define R_CAMP1 (0x020 / 4) |
| 25 | #define R_CAMP2 (0x024 / 4) |
| 26 | #define R_QSR (0x040 / 4) |
| 27 | |
| 28 | /* R_STATUS */ |
| 29 | #define ABR_EN BIT(14) /* Mirrors SCU510[11] */ |
| 30 | #define ABR_IMAGE_SOURCE BIT(13) |
| 31 | #define SPI_ABR_IMAGE_SOURCE BIT(12) |
| 32 | #define SB_CRYPTO_KEY_EXP_DONE BIT(11) |
| 33 | #define SB_CRYPTO_BUSY BIT(10) |
| 34 | #define OTP_WP_EN BIT(9) |
| 35 | #define OTP_ADDR_WP_EN BIT(8) |
| 36 | #define LOW_SEC_KEY_EN BIT(7) |
| 37 | #define SECURE_BOOT_EN BIT(6) |
| 38 | #define UART_BOOT_EN BIT(5) |
| 39 | /* bit 4 reserved*/ |
| 40 | #define OTP_CHARGE_PUMP_READY BIT(3) |
| 41 | #define OTP_IDLE BIT(2) |
| 42 | #define OTP_MEM_IDLE BIT(1) |
| 43 | #define OTP_COMPARE_STATUS BIT(0) |
| 44 | |
| 45 | /* QSR */ |
| 46 | #define QSR_RSA_MASK (0x3 << 12) |
| 47 | #define QSR_HASH_MASK (0x3 << 10) |
| 48 | |
| 49 | #define OTP_MEMORY_SIZE 0x4000 |
| 50 | /* OTP command */ |
| 51 | #define SBC_OTP_CMD_READ 0x23b1e361 |
| 52 | #define SBC_OTP_CMD_WRITE 0x23b1e362 |
| 53 | #define SBC_OTP_CMD_PROG 0x23b1e364 |
| 54 | |
| 55 | #define OTP_DATA_DWORD_COUNT (0x800) |
| 56 | #define OTP_TOTAL_DWORD_COUNT (0x1000) |
| 57 | |
| 58 | /* Voltage mode */ |
| 59 | #define MODE_REGISTER (0x1000) |
| 60 | #define MODE_REGISTER_A (0x3000) |
| 61 | #define MODE_REGISTER_B (0x5000) |
| 62 | |
| 63 | static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size) |
| 64 | { |
| 65 | AspeedSBCState *s = ASPEED_SBC(opaque); |
| 66 | |
| 67 | addr >>= 2; |
| 68 | |
| 69 | if (addr >= ASPEED_SBC_NR_REGS) { |
| 70 | qemu_log_mask(LOG_GUEST_ERROR, |
| 71 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", |
| 72 | __func__, addr << 2); |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | return s->regs[addr]; |
| 77 | } |
| 78 | |
| 79 | static bool aspeed_sbc_otp_read(AspeedSBCState *s, |
| 80 | uint32_t otp_addr) |
| 81 | { |
| 82 | MemTxResult ret; |
| 83 | AspeedOTPState *otp = &s->otp; |
| 84 | uint32_t value, otp_offset; |
| 85 | bool is_data = false; |
| 86 | |
| 87 | if (otp_addr < OTP_DATA_DWORD_COUNT) { |
| 88 | is_data = true; |
| 89 | } else if (otp_addr >= OTP_TOTAL_DWORD_COUNT) { |
| 90 | qemu_log_mask(LOG_GUEST_ERROR, |
| 91 | "Invalid OTP addr 0x%x\n", |
| 92 | otp_addr); |
| 93 | return false; |
| 94 | } |
| 95 | |
| 96 | otp_offset = otp_addr << 2; |
| 97 | ret = address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIED, |
| 98 | &value, sizeof(value)); |
| 99 | if (ret != MEMTX_OK) { |
| 100 | qemu_log_mask(LOG_GUEST_ERROR, |
| 101 | "Failed to read OTP memory, addr = %x\n", |
| 102 | otp_addr); |
| 103 | return false; |
| 104 | } |
| 105 | s->regs[R_CAMP1] = value; |
| 106 | trace_aspeed_sbc_otp_read(otp_addr, value); |
| 107 | |
| 108 | if (is_data) { |
| 109 | ret = address_space_read(&otp->as, otp_offset + 4, |
| 110 | MEMTXATTRS_UNSPECIFIED, |
| 111 | &value, sizeof(value)); |
| 112 | if (ret != MEMTX_OK) { |
| 113 | qemu_log_mask(LOG_GUEST_ERROR, |
| 114 | "Failed to read OTP memory, addr = %x\n", |
| 115 | otp_addr); |
| 116 | return false; |
| 117 | } |
| 118 | s->regs[R_CAMP2] = value; |
| 119 | trace_aspeed_sbc_otp_read(otp_addr + 1, value); |
| 120 | } |
| 121 | |
| 122 | return true; |
| 123 | } |
| 124 | |
| 125 | static bool mode_handler(uint32_t otp_addr) |
| 126 | { |
| 127 | switch (otp_addr) { |
| 128 | case MODE_REGISTER: |
| 129 | case MODE_REGISTER_A: |
| 130 | case MODE_REGISTER_B: |
| 131 | /* HW behavior, do nothing here */ |
| 132 | return true; |
| 133 | default: |
| 134 | qemu_log_mask(LOG_GUEST_ERROR, |
| 135 | "Unsupported address 0x%x\n", |
| 136 | otp_addr); |
| 137 | return false; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | static bool aspeed_sbc_otp_write(AspeedSBCState *s, |
| 142 | uint32_t otp_addr) |
| 143 | { |
| 144 | if (otp_addr == 0) { |
| 145 | trace_aspeed_sbc_ignore_cmd(otp_addr); |
| 146 | return true; |
| 147 | } else { |
| 148 | if (mode_handler(otp_addr) == false) { |
| 149 | return false; |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | return true; |
| 154 | } |
| 155 | |
| 156 | static bool aspeed_sbc_otp_prog(AspeedSBCState *s, |
| 157 | uint32_t otp_addr) |
| 158 | { |
| 159 | MemTxResult ret; |
| 160 | AspeedOTPState *otp = &s->otp; |
| 161 | uint32_t value = s->regs[R_CAMP1]; |
| 162 | uint32_t otp_offset = otp_addr << 2; |
| 163 | |
| 164 | if (otp_addr >= OTP_TOTAL_DWORD_COUNT) { |
| 165 | qemu_log_mask(LOG_GUEST_ERROR, |
| 166 | "Invalid OTP addr 0x%x\n", |
| 167 | otp_addr); |
| 168 | return false; |
| 169 | } |
| 170 | |
| 171 | ret = address_space_write(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIED, |
| 172 | &value, sizeof(value)); |
| 173 | if (ret != MEMTX_OK) { |
| 174 | qemu_log_mask(LOG_GUEST_ERROR, |
| 175 | "Failed to write OTP memory, addr = %x\n", |
| 176 | otp_addr); |
| 177 | return false; |
| 178 | } |
| 179 | |
| 180 | trace_aspeed_sbc_otp_prog(otp_addr, value); |
| 181 | |
| 182 | return true; |
| 183 | } |
| 184 | |
| 185 | static void aspeed_sbc_handle_command(void *opaque, uint32_t cmd) |
| 186 | { |
| 187 | AspeedSBCState *s = ASPEED_SBC(opaque); |
| 188 | AspeedSBCClass *sc = ASPEED_SBC_GET_CLASS(opaque); |
| 189 | bool ret = false; |
| 190 | uint32_t otp_addr; |
| 191 | |
| 192 | if (!sc->has_otp) { |
| 193 | qemu_log_mask(LOG_GUEST_ERROR, |
| 194 | "%s: OTP memory is not supported\n", |
| 195 | __func__); |
| 196 | return; |
| 197 | } |
| 198 | |
| 199 | s->regs[R_STATUS] &= ~(OTP_MEM_IDLE | OTP_IDLE); |
| 200 | otp_addr = s->regs[R_ADDR]; |
| 201 | |
| 202 | switch (cmd) { |
| 203 | case SBC_OTP_CMD_READ: |
| 204 | ret = aspeed_sbc_otp_read(s, otp_addr); |
| 205 | break; |
| 206 | case SBC_OTP_CMD_WRITE: |
| 207 | ret = aspeed_sbc_otp_write(s, otp_addr); |
| 208 | break; |
| 209 | case SBC_OTP_CMD_PROG: |
| 210 | ret = aspeed_sbc_otp_prog(s, otp_addr); |
| 211 | break; |
| 212 | default: |
| 213 | qemu_log_mask(LOG_GUEST_ERROR, |
| 214 | "%s: Unknown command 0x%x\n", |
| 215 | __func__, cmd); |
| 216 | break; |
| 217 | } |
| 218 | |
| 219 | trace_aspeed_sbc_handle_cmd(cmd, otp_addr, ret); |
| 220 | s->regs[R_STATUS] |= (OTP_MEM_IDLE | OTP_IDLE); |
| 221 | } |
| 222 | |
| 223 | static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data, |
| 224 | unsigned int size) |
| 225 | { |
| 226 | AspeedSBCState *s = ASPEED_SBC(opaque); |
| 227 | |
| 228 | addr >>= 2; |
| 229 | |
| 230 | if (addr >= ASPEED_SBC_NR_REGS) { |
| 231 | qemu_log_mask(LOG_GUEST_ERROR, |
| 232 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", |
| 233 | __func__, addr << 2); |
| 234 | return; |
| 235 | } |
| 236 | |
| 237 | switch (addr) { |
| 238 | case R_STATUS: |
| 239 | case R_QSR: |
| 240 | qemu_log_mask(LOG_GUEST_ERROR, |
| 241 | "%s: write to read only register 0x%" HWADDR_PRIx "\n", |
| 242 | __func__, addr << 2); |
| 243 | return; |
| 244 | case R_CMD: |
| 245 | aspeed_sbc_handle_command(opaque, data); |
| 246 | return; |
| 247 | default: |
| 248 | break; |
| 249 | } |
| 250 | |
| 251 | s->regs[addr] = data; |
| 252 | } |
| 253 | |
| 254 | static const MemoryRegionOps aspeed_sbc_ops = { |
| 255 | .read = aspeed_sbc_read, |
| 256 | .write = aspeed_sbc_write, |
| 257 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 258 | .valid = { |
| 259 | .min_access_size = 1, |
| 260 | .max_access_size = 4, |
| 261 | }, |
| 262 | }; |
| 263 | |
| 264 | static void aspeed_sbc_reset_hold(Object *obj, ResetType type) |
| 265 | { |
| 266 | AspeedSBCState *s = ASPEED_SBC(obj); |
| 267 | |
| 268 | memset(s->regs, 0, sizeof(s->regs)); |
| 269 | |
| 270 | /* Set secure boot enabled with RSA4096_SHA256 and enable eMMC ABR */ |
| 271 | s->regs[R_STATUS] = OTP_IDLE | OTP_MEM_IDLE; |
| 272 | |
| 273 | if (s->emmc_abr) { |
| 274 | s->regs[R_STATUS] &= ABR_EN; |
| 275 | } |
| 276 | |
| 277 | if (s->signing_settings) { |
| 278 | s->regs[R_STATUS] &= SECURE_BOOT_EN; |
| 279 | } |
| 280 | |
| 281 | s->regs[R_QSR] = s->signing_settings; |
| 282 | } |
| 283 | |
| 284 | static void aspeed_sbc_instance_init(Object *obj) |
| 285 | { |
| 286 | AspeedSBCClass *sc = ASPEED_SBC_GET_CLASS(obj); |
| 287 | AspeedSBCState *s = ASPEED_SBC(obj); |
| 288 | |
| 289 | if (sc->has_otp) { |
| 290 | object_initialize_child(OBJECT(s), "otp", &s->otp, |
| 291 | TYPE_ASPEED_OTP); |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | static void aspeed_sbc_realize(DeviceState *dev, Error **errp) |
| 296 | { |
| 297 | AspeedSBCState *s = ASPEED_SBC(dev); |
| 298 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 299 | AspeedSBCClass *sc = ASPEED_SBC_GET_CLASS(dev); |
| 300 | |
| 301 | if (sc->has_otp) { |
| 302 | object_property_set_int(OBJECT(&s->otp), "size", |
| 303 | OTP_MEMORY_SIZE, &error_abort); |
| 304 | if (!qdev_realize(DEVICE(&s->otp), NULL, errp)) { |
| 305 | return; |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s, |
| 310 | TYPE_ASPEED_SBC, 0x1000); |
| 311 | |
| 312 | sysbus_init_mmio(sbd, &s->iomem); |
| 313 | } |
| 314 | |
| 315 | static const VMStateDescription vmstate_aspeed_sbc = { |
| 316 | .name = TYPE_ASPEED_SBC, |
| 317 | .version_id = 1, |
| 318 | .minimum_version_id = 1, |
| 319 | .fields = (const VMStateField[]) { |
| 320 | VMSTATE_UINT32_ARRAY(regs, AspeedSBCState, ASPEED_SBC_NR_REGS), |
| 321 | VMSTATE_END_OF_LIST(), |
| 322 | } |
| 323 | }; |
| 324 | |
| 325 | static const Property aspeed_sbc_properties[] = { |
| 326 | DEFINE_PROP_BOOL("emmc-abr", AspeedSBCState, emmc_abr, 0), |
| 327 | DEFINE_PROP_UINT32("signing-settings", AspeedSBCState, signing_settings, 0), |
| 328 | }; |
| 329 | |
| 330 | static void aspeed_sbc_class_init(ObjectClass *klass, const void *data) |
| 331 | { |
| 332 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 333 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 334 | |
| 335 | dc->realize = aspeed_sbc_realize; |
| 336 | rc->phases.hold = aspeed_sbc_reset_hold; |
| 337 | dc->vmsd = &vmstate_aspeed_sbc; |
| 338 | device_class_set_props(dc, aspeed_sbc_properties); |
| 339 | } |
| 340 | |
| 341 | |
| 342 | static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, const void *data) |
| 343 | { |
| 344 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 345 | AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass); |
| 346 | |
| 347 | dc->desc = "AST2600 Secure Boot Controller"; |
| 348 | sc->has_otp = true; |
| 349 | } |
| 350 | |
| 351 | static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *data) |
| 352 | { |
| 353 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 354 | AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass); |
| 355 | |
| 356 | dc->desc = "AST10X0 Secure Boot Controller"; |
| 357 | sc->has_otp = true; |
| 358 | } |
| 359 | |
| 360 | static const TypeInfo aspeed_sbc_types[] = { |
| 361 | { |
| 362 | .name = TYPE_ASPEED_SBC, |
| 363 | .parent = TYPE_SYS_BUS_DEVICE, |
| 364 | .instance_size = sizeof(AspeedSBCState), |
| 365 | .instance_init = aspeed_sbc_instance_init, |
| 366 | .class_init = aspeed_sbc_class_init, |
| 367 | .class_size = sizeof(AspeedSBCClass), |
| 368 | }, |
| 369 | { |
| 370 | .name = TYPE_ASPEED_AST10X0_SBC, |
| 371 | .parent = TYPE_ASPEED_SBC, |
| 372 | .class_init = aspeed_ast10x0_sbc_class_init, |
| 373 | }, |
| 374 | { |
| 375 | .name = TYPE_ASPEED_AST2600_SBC, |
| 376 | .parent = TYPE_ASPEED_SBC, |
| 377 | .class_init = aspeed_ast2600_sbc_class_init, |
| 378 | } |
| 379 | }; |
| 380 | |
| 381 | DEFINE_TYPES(aspeed_sbc_types) |