| 1 | /* |
| 2 | * ASPEED SDRAM Memory Controller |
| 3 | * |
| 4 | * Copyright (C) 2016 IBM Corp. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See |
| 7 | * the COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qemu/log.h" |
| 12 | #include "qemu/module.h" |
| 13 | #include "qemu/error-report.h" |
| 14 | #include "hw/misc/aspeed_sdmc.h" |
| 15 | #include "hw/core/qdev-properties.h" |
| 16 | #include "migration/vmstate.h" |
| 17 | #include "qapi/error.h" |
| 18 | #include "trace.h" |
| 19 | #include "qemu/units.h" |
| 20 | #include "qemu/cutils.h" |
| 21 | #include "qapi/visitor.h" |
| 22 | |
| 23 | /* Protection Key Register */ |
| 24 | #define R_PROT (0x00 / 4) |
| 25 | #define PROT_UNLOCKED 0x01 |
| 26 | #define PROT_HARDLOCKED 0x10 /* AST2600 */ |
| 27 | #define PROT_SOFTLOCKED 0x00 |
| 28 | |
| 29 | #define PROT_KEY_UNLOCK 0xFC600309 |
| 30 | #define PROT_2700_KEY_UNLOCK 0x1688A8A8 |
| 31 | #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */ |
| 32 | |
| 33 | /* Configuration Register */ |
| 34 | #define R_CONF (0x04 / 4) |
| 35 | |
| 36 | /* Interrupt control/status */ |
| 37 | #define R_ISR (0x50 / 4) |
| 38 | |
| 39 | /* Control/Status Register #1 (ast2500) */ |
| 40 | #define R_STATUS1 (0x60 / 4) |
| 41 | #define PHY_BUSY_STATE BIT(0) |
| 42 | #define PHY_PLL_LOCK_STATUS BIT(4) |
| 43 | |
| 44 | /* Reserved */ |
| 45 | #define R_MCR6C (0x6c / 4) |
| 46 | |
| 47 | #define R_ECC_TEST_CTRL (0x70 / 4) |
| 48 | #define ECC_TEST_FINISHED BIT(12) |
| 49 | #define ECC_TEST_FAIL BIT(13) |
| 50 | |
| 51 | #define R_TEST_START_LEN (0x74 / 4) |
| 52 | #define R_TEST_FAIL_DQ (0x78 / 4) |
| 53 | #define R_TEST_INIT_VAL (0x7c / 4) |
| 54 | #define R_DRAM_SW (0x88 / 4) |
| 55 | #define R_DRAM_TIME (0x8c / 4) |
| 56 | #define R_ECC_ERR_INJECT (0xb4 / 4) |
| 57 | |
| 58 | /* AST2700 Register */ |
| 59 | #define R_2700_PROT (0x00 / 4) |
| 60 | #define R_INT_STATUS (0x04 / 4) |
| 61 | #define R_INT_CLEAR (0x08 / 4) |
| 62 | #define R_INT_MASK (0x0c / 4) |
| 63 | #define R_MAIN_CONF (0x10 / 4) |
| 64 | #define R_MAIN_CONTROL (0x14 / 4) |
| 65 | #define R_MAIN_STATUS (0x18 / 4) |
| 66 | #define R_ERR_STATUS (0x1c / 4) |
| 67 | #define R_ECC_FAIL_STATUS (0x78 / 4) |
| 68 | #define R_ECC_FAIL_ADDR (0x7c / 4) |
| 69 | #define R_ECC_TESTING_CONTROL (0x80 / 4) |
| 70 | #define R_PROT_REGION_LOCK_STATUS (0x94 / 4) |
| 71 | #define R_TEST_FAIL_ADDR (0xd4 / 4) |
| 72 | #define R_TEST_FAIL_D0 (0xd8 / 4) |
| 73 | #define R_TEST_FAIL_D1 (0xdc / 4) |
| 74 | #define R_TEST_FAIL_D2 (0xe0 / 4) |
| 75 | #define R_TEST_FAIL_D3 (0xe4 / 4) |
| 76 | #define R_DBG_STATUS (0xf4 / 4) |
| 77 | #define R_PHY_INTERFACE_STATUS (0xf8 / 4) |
| 78 | #define R_GRAPHIC_MEM_BASE_ADDR (0x10c / 4) |
| 79 | #define R_PORT0_INTERFACE_MONITOR0 (0x240 / 4) |
| 80 | #define R_PORT0_INTERFACE_MONITOR1 (0x244 / 4) |
| 81 | #define R_PORT0_INTERFACE_MONITOR2 (0x248 / 4) |
| 82 | #define R_PORT1_INTERFACE_MONITOR0 (0x2c0 / 4) |
| 83 | #define R_PORT1_INTERFACE_MONITOR1 (0x2c4 / 4) |
| 84 | #define R_PORT1_INTERFACE_MONITOR2 (0x2c8 / 4) |
| 85 | #define R_PORT2_INTERFACE_MONITOR0 (0x340 / 4) |
| 86 | #define R_PORT2_INTERFACE_MONITOR1 (0x344 / 4) |
| 87 | #define R_PORT2_INTERFACE_MONITOR2 (0x348 / 4) |
| 88 | #define R_PORT3_INTERFACE_MONITOR0 (0x3c0 / 4) |
| 89 | #define R_PORT3_INTERFACE_MONITOR1 (0x3c4 / 4) |
| 90 | #define R_PORT3_INTERFACE_MONITOR2 (0x3c8 / 4) |
| 91 | #define R_PORT4_INTERFACE_MONITOR0 (0x440 / 4) |
| 92 | #define R_PORT4_INTERFACE_MONITOR1 (0x444 / 4) |
| 93 | #define R_PORT4_INTERFACE_MONITOR2 (0x448 / 4) |
| 94 | #define R_PORT5_INTERFACE_MONITOR0 (0x4c0 / 4) |
| 95 | #define R_PORT5_INTERFACE_MONITOR1 (0x4c4 / 4) |
| 96 | #define R_PORT5_INTERFACE_MONITOR2 (0x4c8 / 4) |
| 97 | |
| 98 | /* |
| 99 | * Configuration register Ox4 (for Aspeed AST2400 SOC) |
| 100 | * |
| 101 | * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is |
| 102 | * what we care about right now as it is checked by U-Boot to |
| 103 | * determine the RAM size. |
| 104 | */ |
| 105 | |
| 106 | #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */ |
| 107 | #define ASPEED_SDMC_AST2300_COMPAT (1 << 10) |
| 108 | #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9) |
| 109 | #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8) |
| 110 | #define ASPEED_SDMC_ECC_ENABLE (1 << 7) |
| 111 | #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */ |
| 112 | #define ASPEED_SDMC_DRAM_BANK (1 << 5) |
| 113 | #define ASPEED_SDMC_DRAM_BURST (1 << 4) |
| 114 | #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */ |
| 115 | #define ASPEED_SDMC_VGA_8MB 0x0 |
| 116 | #define ASPEED_SDMC_VGA_16MB 0x1 |
| 117 | #define ASPEED_SDMC_VGA_32MB 0x2 |
| 118 | #define ASPEED_SDMC_VGA_64MB 0x3 |
| 119 | #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3) |
| 120 | |
| 121 | #define ASPEED_SDMC_READONLY_MASK \ |
| 122 | (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ |
| 123 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) |
| 124 | /* |
| 125 | * Configuration register Ox4 (for Aspeed AST2500 SOC and higher) |
| 126 | * |
| 127 | * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION |
| 128 | * should be set to 1 for the AST2500 SOC. |
| 129 | */ |
| 130 | #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */ |
| 131 | #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20) |
| 132 | #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */ |
| 133 | #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */ |
| 134 | #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13) |
| 135 | #define ASPEED_SDMC_CACHE_INITIAL (1 << 12) |
| 136 | #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11) |
| 137 | #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */ |
| 138 | #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */ |
| 139 | |
| 140 | #define ASPEED_SDMC_AST2500_READONLY_MASK \ |
| 141 | (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ |
| 142 | ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ |
| 143 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) |
| 144 | |
| 145 | /* |
| 146 | * Main Configuration register Ox10 (for Aspeed AST2700 SOC and higher) |
| 147 | * |
| 148 | */ |
| 149 | #define ASPEED_SDMC_AST2700_RESERVED 0xFFFF2082 /* 31:16, 13, 7, 1 */ |
| 150 | #define ASPEED_SDMC_AST2700_DATA_SCRAMBLE (1 << 8) |
| 151 | #define ASPEED_SDMC_AST2700_ECC_ENABLE (1 << 6) |
| 152 | #define ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE (1 << 5) |
| 153 | #define ASPEED_SDMC_AST2700_DRAM_SIZE(x) ((x & 0x7) << 2) |
| 154 | |
| 155 | #define ASPEED_SDMC_AST2700_READONLY_MASK \ |
| 156 | (ASPEED_SDMC_AST2700_RESERVED) |
| 157 | |
| 158 | static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size) |
| 159 | { |
| 160 | AspeedSDMCState *s = ASPEED_SDMC(opaque); |
| 161 | |
| 162 | addr >>= 2; |
| 163 | |
| 164 | if (addr >= ARRAY_SIZE(s->regs)) { |
| 165 | qemu_log_mask(LOG_GUEST_ERROR, |
| 166 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", |
| 167 | __func__, addr * 4); |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | trace_aspeed_sdmc_read(addr, s->regs[addr]); |
| 172 | return s->regs[addr]; |
| 173 | } |
| 174 | |
| 175 | static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, |
| 176 | unsigned int size) |
| 177 | { |
| 178 | AspeedSDMCState *s = ASPEED_SDMC(opaque); |
| 179 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
| 180 | |
| 181 | addr >>= 2; |
| 182 | |
| 183 | if (addr >= ARRAY_SIZE(s->regs)) { |
| 184 | qemu_log_mask(LOG_GUEST_ERROR, |
| 185 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", |
| 186 | __func__, addr); |
| 187 | return; |
| 188 | } |
| 189 | |
| 190 | trace_aspeed_sdmc_write(addr, data); |
| 191 | asc->write(s, addr, data); |
| 192 | } |
| 193 | |
| 194 | static const MemoryRegionOps aspeed_sdmc_ops = { |
| 195 | .read = aspeed_sdmc_read, |
| 196 | .write = aspeed_sdmc_write, |
| 197 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 198 | .valid.min_access_size = 4, |
| 199 | .valid.max_access_size = 4, |
| 200 | }; |
| 201 | |
| 202 | static void aspeed_sdmc_reset_hold(Object *obj, ResetType type) |
| 203 | { |
| 204 | AspeedSDMCState *s = ASPEED_SDMC(obj); |
| 205 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
| 206 | |
| 207 | memset(s->regs, 0, sizeof(s->regs)); |
| 208 | |
| 209 | /* Set ram size bit and defaults values */ |
| 210 | s->regs[R_CONF] = asc->compute_conf(s, 0); |
| 211 | |
| 212 | /* |
| 213 | * PHY status: |
| 214 | * - set phy status ok (set bit 1) |
| 215 | * - initial PVT calibration ok (clear bit 3) |
| 216 | * - runtime calibration ok (clear bit 5) |
| 217 | */ |
| 218 | s->regs[0x100] = BIT(1); |
| 219 | |
| 220 | /* PHY eye window: set all as passing */ |
| 221 | s->regs[0x100 | (0x68 / 4)] = 0xff; |
| 222 | s->regs[0x100 | (0x7c / 4)] = 0xff; |
| 223 | s->regs[0x100 | (0x50 / 4)] = 0xfffffff; |
| 224 | } |
| 225 | |
| 226 | static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, |
| 227 | void *opaque, Error **errp) |
| 228 | { |
| 229 | AspeedSDMCState *s = ASPEED_SDMC(obj); |
| 230 | int64_t value = s->ram_size; |
| 231 | |
| 232 | visit_type_int(v, name, &value, errp); |
| 233 | } |
| 234 | |
| 235 | static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, |
| 236 | void *opaque, Error **errp) |
| 237 | { |
| 238 | int i; |
| 239 | char *sz; |
| 240 | int64_t value; |
| 241 | AspeedSDMCState *s = ASPEED_SDMC(obj); |
| 242 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
| 243 | |
| 244 | if (!visit_type_int(v, name, &value, errp)) { |
| 245 | return; |
| 246 | } |
| 247 | |
| 248 | for (i = 0; asc->valid_ram_sizes[i]; i++) { |
| 249 | if (value == asc->valid_ram_sizes[i]) { |
| 250 | s->ram_size = value; |
| 251 | return; |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | sz = size_to_str(value); |
| 256 | error_setg(errp, "Invalid RAM size %s", sz); |
| 257 | g_free(sz); |
| 258 | } |
| 259 | |
| 260 | static void aspeed_sdmc_initfn(Object *obj) |
| 261 | { |
| 262 | object_property_add(obj, "ram-size", "int", |
| 263 | aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, |
| 264 | NULL, NULL); |
| 265 | } |
| 266 | |
| 267 | static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) |
| 268 | { |
| 269 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 270 | AspeedSDMCState *s = ASPEED_SDMC(dev); |
| 271 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
| 272 | |
| 273 | assert(asc->max_ram_size < 4 * GiB || asc->is_bus64bit); |
| 274 | |
| 275 | if (!s->ram_size) { |
| 276 | error_setg(errp, "RAM size is not set"); |
| 277 | return; |
| 278 | } |
| 279 | |
| 280 | s->max_ram_size = asc->max_ram_size; |
| 281 | |
| 282 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, |
| 283 | TYPE_ASPEED_SDMC, 0x1000); |
| 284 | sysbus_init_mmio(sbd, &s->iomem); |
| 285 | } |
| 286 | |
| 287 | static const VMStateDescription vmstate_aspeed_sdmc = { |
| 288 | .name = "aspeed.sdmc", |
| 289 | .version_id = 2, |
| 290 | .minimum_version_id = 2, |
| 291 | .fields = (const VMStateField[]) { |
| 292 | VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS), |
| 293 | VMSTATE_END_OF_LIST() |
| 294 | } |
| 295 | }; |
| 296 | |
| 297 | static const Property aspeed_sdmc_properties[] = { |
| 298 | DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), |
| 299 | DEFINE_PROP_BOOL("unlocked", AspeedSDMCState, unlocked, false), |
| 300 | }; |
| 301 | |
| 302 | static void aspeed_sdmc_class_init(ObjectClass *klass, const void *data) |
| 303 | { |
| 304 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 305 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 306 | dc->realize = aspeed_sdmc_realize; |
| 307 | rc->phases.hold = aspeed_sdmc_reset_hold; |
| 308 | dc->desc = "ASPEED SDRAM Memory Controller"; |
| 309 | dc->vmsd = &vmstate_aspeed_sdmc; |
| 310 | device_class_set_props(dc, aspeed_sdmc_properties); |
| 311 | } |
| 312 | |
| 313 | static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s) |
| 314 | { |
| 315 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
| 316 | int i; |
| 317 | |
| 318 | /* |
| 319 | * The bitfield value encoding the RAM size is the index of the |
| 320 | * possible RAM size array |
| 321 | */ |
| 322 | for (i = 0; asc->valid_ram_sizes[i]; i++) { |
| 323 | if (s->ram_size == asc->valid_ram_sizes[i]) { |
| 324 | return i; |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * Invalid RAM sizes should have been excluded when setting the |
| 330 | * SoC RAM size. |
| 331 | */ |
| 332 | g_assert_not_reached(); |
| 333 | } |
| 334 | |
| 335 | static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) |
| 336 | { |
| 337 | uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | |
| 338 | ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); |
| 339 | |
| 340 | /* Make sure readonly bits are kept */ |
| 341 | data &= ~ASPEED_SDMC_READONLY_MASK; |
| 342 | |
| 343 | return data | fixed_conf; |
| 344 | } |
| 345 | |
| 346 | static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, |
| 347 | uint32_t data) |
| 348 | { |
| 349 | if (reg == R_PROT) { |
| 350 | s->regs[reg] = |
| 351 | (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; |
| 352 | return; |
| 353 | } |
| 354 | |
| 355 | if (!s->regs[R_PROT]) { |
| 356 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); |
| 357 | return; |
| 358 | } |
| 359 | |
| 360 | switch (reg) { |
| 361 | case R_CONF: |
| 362 | data = aspeed_2400_sdmc_compute_conf(s, data); |
| 363 | break; |
| 364 | default: |
| 365 | break; |
| 366 | } |
| 367 | |
| 368 | s->regs[reg] = data; |
| 369 | } |
| 370 | |
| 371 | static const uint64_t |
| 372 | aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; |
| 373 | |
| 374 | static void aspeed_2400_sdmc_class_init(ObjectClass *klass, const void *data) |
| 375 | { |
| 376 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 377 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); |
| 378 | |
| 379 | dc->desc = "ASPEED 2400 SDRAM Memory Controller"; |
| 380 | asc->max_ram_size = 512 * MiB; |
| 381 | asc->compute_conf = aspeed_2400_sdmc_compute_conf; |
| 382 | asc->write = aspeed_2400_sdmc_write; |
| 383 | asc->valid_ram_sizes = aspeed_2400_ram_sizes; |
| 384 | } |
| 385 | |
| 386 | static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) |
| 387 | { |
| 388 | uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | |
| 389 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | |
| 390 | ASPEED_SDMC_CACHE_INITIAL_DONE | |
| 391 | ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); |
| 392 | |
| 393 | /* Make sure readonly bits are kept */ |
| 394 | data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; |
| 395 | |
| 396 | return data | fixed_conf; |
| 397 | } |
| 398 | |
| 399 | static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, |
| 400 | uint32_t data) |
| 401 | { |
| 402 | if (reg == R_PROT) { |
| 403 | s->regs[reg] = |
| 404 | (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; |
| 405 | return; |
| 406 | } |
| 407 | |
| 408 | if (!s->regs[R_PROT]) { |
| 409 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); |
| 410 | return; |
| 411 | } |
| 412 | |
| 413 | switch (reg) { |
| 414 | case R_CONF: |
| 415 | data = aspeed_2500_sdmc_compute_conf(s, data); |
| 416 | break; |
| 417 | case R_STATUS1: |
| 418 | /* Will never return 'busy' */ |
| 419 | data &= ~PHY_BUSY_STATE; |
| 420 | break; |
| 421 | case R_ECC_TEST_CTRL: |
| 422 | /* Always done, always happy */ |
| 423 | data |= ECC_TEST_FINISHED; |
| 424 | data &= ~ECC_TEST_FAIL; |
| 425 | break; |
| 426 | default: |
| 427 | break; |
| 428 | } |
| 429 | |
| 430 | s->regs[reg] = data; |
| 431 | } |
| 432 | |
| 433 | static const uint64_t |
| 434 | aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; |
| 435 | |
| 436 | static void aspeed_2500_sdmc_class_init(ObjectClass *klass, const void *data) |
| 437 | { |
| 438 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 439 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); |
| 440 | |
| 441 | dc->desc = "ASPEED 2500 SDRAM Memory Controller"; |
| 442 | asc->max_ram_size = 1 * GiB; |
| 443 | asc->compute_conf = aspeed_2500_sdmc_compute_conf; |
| 444 | asc->write = aspeed_2500_sdmc_write; |
| 445 | asc->valid_ram_sizes = aspeed_2500_ram_sizes; |
| 446 | } |
| 447 | |
| 448 | static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) |
| 449 | { |
| 450 | uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | |
| 451 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | |
| 452 | ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); |
| 453 | |
| 454 | /* Make sure readonly bits are kept (use ast2500 mask) */ |
| 455 | data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; |
| 456 | |
| 457 | return data | fixed_conf; |
| 458 | } |
| 459 | |
| 460 | static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, |
| 461 | uint32_t data) |
| 462 | { |
| 463 | /* Unprotected registers */ |
| 464 | switch (reg) { |
| 465 | case R_ISR: |
| 466 | case R_MCR6C: |
| 467 | case R_TEST_START_LEN: |
| 468 | case R_TEST_FAIL_DQ: |
| 469 | case R_TEST_INIT_VAL: |
| 470 | case R_DRAM_SW: |
| 471 | case R_DRAM_TIME: |
| 472 | case R_ECC_ERR_INJECT: |
| 473 | s->regs[reg] = data; |
| 474 | return; |
| 475 | } |
| 476 | |
| 477 | if (s->regs[R_PROT] == PROT_HARDLOCKED) { |
| 478 | qemu_log_mask(LOG_GUEST_ERROR, |
| 479 | "%s: SDMC is locked until system reset!\n", |
| 480 | __func__); |
| 481 | return; |
| 482 | } |
| 483 | |
| 484 | if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) { |
| 485 | qemu_log_mask(LOG_GUEST_ERROR, |
| 486 | "%s: SDMC is locked! (write to MCR%02x blocked)\n", |
| 487 | __func__, reg * 4); |
| 488 | return; |
| 489 | } |
| 490 | |
| 491 | switch (reg) { |
| 492 | case R_PROT: |
| 493 | if (data == PROT_KEY_UNLOCK) { |
| 494 | data = PROT_UNLOCKED; |
| 495 | } else if (data == PROT_KEY_HARDLOCK) { |
| 496 | data = PROT_HARDLOCKED; |
| 497 | } else { |
| 498 | data = PROT_SOFTLOCKED; |
| 499 | } |
| 500 | break; |
| 501 | case R_CONF: |
| 502 | data = aspeed_2600_sdmc_compute_conf(s, data); |
| 503 | break; |
| 504 | case R_STATUS1: |
| 505 | /* Will never return 'busy'. 'lock status' is always set */ |
| 506 | data &= ~PHY_BUSY_STATE; |
| 507 | data |= PHY_PLL_LOCK_STATUS; |
| 508 | break; |
| 509 | case R_ECC_TEST_CTRL: |
| 510 | /* Always done, always happy */ |
| 511 | data |= ECC_TEST_FINISHED; |
| 512 | data &= ~ECC_TEST_FAIL; |
| 513 | break; |
| 514 | default: |
| 515 | break; |
| 516 | } |
| 517 | |
| 518 | s->regs[reg] = data; |
| 519 | } |
| 520 | |
| 521 | static const uint64_t |
| 522 | aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; |
| 523 | |
| 524 | static void aspeed_2600_sdmc_class_init(ObjectClass *klass, const void *data) |
| 525 | { |
| 526 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 527 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); |
| 528 | |
| 529 | dc->desc = "ASPEED 2600 SDRAM Memory Controller"; |
| 530 | asc->max_ram_size = 2 * GiB; |
| 531 | asc->compute_conf = aspeed_2600_sdmc_compute_conf; |
| 532 | asc->write = aspeed_2600_sdmc_write; |
| 533 | asc->valid_ram_sizes = aspeed_2600_ram_sizes; |
| 534 | } |
| 535 | |
| 536 | static void aspeed_2700_sdmc_reset_hold(Object *obj, ResetType type) |
| 537 | { |
| 538 | AspeedSDMCState *s = ASPEED_SDMC(obj); |
| 539 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
| 540 | |
| 541 | memset(s->regs, 0, sizeof(s->regs)); |
| 542 | |
| 543 | /* Set ram size bit and defaults values */ |
| 544 | s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0); |
| 545 | |
| 546 | /* Skipping dram init */ |
| 547 | s->regs[R_MAIN_CONTROL] = BIT(16); |
| 548 | |
| 549 | if (s->unlocked) { |
| 550 | s->regs[R_2700_PROT] = PROT_UNLOCKED; |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | static uint32_t aspeed_2700_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) |
| 555 | { |
| 556 | uint32_t fixed_conf = ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE | |
| 557 | ASPEED_SDMC_AST2700_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); |
| 558 | |
| 559 | /* Make sure readonly bits are kept */ |
| 560 | data &= ~ASPEED_SDMC_AST2700_READONLY_MASK; |
| 561 | |
| 562 | return data | fixed_conf; |
| 563 | } |
| 564 | |
| 565 | static void aspeed_2700_sdmc_write(AspeedSDMCState *s, uint32_t reg, |
| 566 | uint32_t data) |
| 567 | { |
| 568 | /* Unprotected registers */ |
| 569 | switch (reg) { |
| 570 | case R_INT_STATUS: |
| 571 | case R_INT_CLEAR: |
| 572 | case R_INT_MASK: |
| 573 | case R_ERR_STATUS: |
| 574 | case R_ECC_FAIL_STATUS: |
| 575 | case R_ECC_FAIL_ADDR: |
| 576 | case R_PROT_REGION_LOCK_STATUS: |
| 577 | case R_TEST_FAIL_ADDR: |
| 578 | case R_TEST_FAIL_D0: |
| 579 | case R_TEST_FAIL_D1: |
| 580 | case R_TEST_FAIL_D2: |
| 581 | case R_TEST_FAIL_D3: |
| 582 | case R_DBG_STATUS: |
| 583 | case R_PHY_INTERFACE_STATUS: |
| 584 | case R_GRAPHIC_MEM_BASE_ADDR: |
| 585 | case R_PORT0_INTERFACE_MONITOR0: |
| 586 | case R_PORT0_INTERFACE_MONITOR1: |
| 587 | case R_PORT0_INTERFACE_MONITOR2: |
| 588 | case R_PORT1_INTERFACE_MONITOR0: |
| 589 | case R_PORT1_INTERFACE_MONITOR1: |
| 590 | case R_PORT1_INTERFACE_MONITOR2: |
| 591 | case R_PORT2_INTERFACE_MONITOR0: |
| 592 | case R_PORT2_INTERFACE_MONITOR1: |
| 593 | case R_PORT2_INTERFACE_MONITOR2: |
| 594 | case R_PORT3_INTERFACE_MONITOR0: |
| 595 | case R_PORT3_INTERFACE_MONITOR1: |
| 596 | case R_PORT3_INTERFACE_MONITOR2: |
| 597 | case R_PORT4_INTERFACE_MONITOR0: |
| 598 | case R_PORT4_INTERFACE_MONITOR1: |
| 599 | case R_PORT4_INTERFACE_MONITOR2: |
| 600 | case R_PORT5_INTERFACE_MONITOR0: |
| 601 | case R_PORT5_INTERFACE_MONITOR1: |
| 602 | case R_PORT5_INTERFACE_MONITOR2: |
| 603 | s->regs[reg] = data; |
| 604 | return; |
| 605 | } |
| 606 | |
| 607 | if (s->regs[R_2700_PROT] == PROT_HARDLOCKED) { |
| 608 | qemu_log_mask(LOG_GUEST_ERROR, |
| 609 | "%s: SDMC is locked until system reset!\n", |
| 610 | __func__); |
| 611 | return; |
| 612 | } |
| 613 | |
| 614 | if (reg != R_2700_PROT && s->regs[R_2700_PROT] == PROT_SOFTLOCKED) { |
| 615 | qemu_log_mask(LOG_GUEST_ERROR, |
| 616 | "%s: SDMC is locked! (write to MCR%02x blocked)\n", |
| 617 | __func__, reg * 4); |
| 618 | return; |
| 619 | } |
| 620 | |
| 621 | switch (reg) { |
| 622 | case R_2700_PROT: |
| 623 | if (data == PROT_2700_KEY_UNLOCK) { |
| 624 | data = PROT_UNLOCKED; |
| 625 | } else if (data == PROT_KEY_HARDLOCK) { |
| 626 | data = PROT_HARDLOCKED; |
| 627 | } else { |
| 628 | data = PROT_SOFTLOCKED; |
| 629 | } |
| 630 | break; |
| 631 | case R_MAIN_CONF: |
| 632 | data = aspeed_2700_sdmc_compute_conf(s, data); |
| 633 | break; |
| 634 | case R_MAIN_STATUS: |
| 635 | /* Will never return 'busy'. */ |
| 636 | data &= ~PHY_BUSY_STATE; |
| 637 | break; |
| 638 | default: |
| 639 | break; |
| 640 | } |
| 641 | |
| 642 | s->regs[reg] = data; |
| 643 | } |
| 644 | |
| 645 | static const uint64_t |
| 646 | aspeed_2700_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, |
| 647 | 2048 * MiB, 4096 * MiB, 8192 * MiB, 0}; |
| 648 | |
| 649 | static void aspeed_2700_sdmc_class_init(ObjectClass *klass, const void *data) |
| 650 | { |
| 651 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 652 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 653 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); |
| 654 | |
| 655 | dc->desc = "ASPEED 2700 SDRAM Memory Controller"; |
| 656 | rc->phases.hold = aspeed_2700_sdmc_reset_hold; |
| 657 | |
| 658 | asc->is_bus64bit = true; |
| 659 | asc->max_ram_size = 8 * GiB; |
| 660 | asc->compute_conf = aspeed_2700_sdmc_compute_conf; |
| 661 | asc->write = aspeed_2700_sdmc_write; |
| 662 | asc->valid_ram_sizes = aspeed_2700_ram_sizes; |
| 663 | } |
| 664 | |
| 665 | static const TypeInfo aspeed_sdmc_types[] = { |
| 666 | { |
| 667 | .name = TYPE_ASPEED_SDMC, |
| 668 | .parent = TYPE_SYS_BUS_DEVICE, |
| 669 | .instance_size = sizeof(AspeedSDMCState), |
| 670 | .instance_init = aspeed_sdmc_initfn, |
| 671 | .class_init = aspeed_sdmc_class_init, |
| 672 | .class_size = sizeof(AspeedSDMCClass), |
| 673 | .abstract = true, |
| 674 | }, |
| 675 | { |
| 676 | .name = TYPE_ASPEED_2400_SDMC, |
| 677 | .parent = TYPE_ASPEED_SDMC, |
| 678 | .class_init = aspeed_2400_sdmc_class_init, |
| 679 | }, |
| 680 | { |
| 681 | .name = TYPE_ASPEED_2500_SDMC, |
| 682 | .parent = TYPE_ASPEED_SDMC, |
| 683 | .class_init = aspeed_2500_sdmc_class_init, |
| 684 | }, |
| 685 | { |
| 686 | .name = TYPE_ASPEED_2600_SDMC, |
| 687 | .parent = TYPE_ASPEED_SDMC, |
| 688 | .class_init = aspeed_2600_sdmc_class_init, |
| 689 | }, |
| 690 | { |
| 691 | .name = TYPE_ASPEED_2700_SDMC, |
| 692 | .parent = TYPE_ASPEED_SDMC, |
| 693 | .class_init = aspeed_2700_sdmc_class_init, |
| 694 | } |
| 695 | }; |
| 696 | |
| 697 | DEFINE_TYPES(aspeed_sdmc_types) |