@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 79 lines 1.96 KB
Raw
1 /*
2 * Axiado Clock Control
3 *
4 * Author: Kuan-Jui Chiu <kchiu@axiado.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "hw/misc/axiado_clk.h"
11 #include "qemu/log.h"
12
13 #define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C
14 #define CLKRST_CPU_PLL_STS_OFFSET 0x14
15
16 static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size)
17 {
18 switch (offset) {
19 case CLKRST_CPU_PLL_POSTDIV_OFFSET:
20 return 0x20891b;
21 case CLKRST_CPU_PLL_STS_OFFSET:
22 return 0x01;
23 default:
24 qemu_log_mask(LOG_UNIMP,
25 "Register 0x%" HWADDR_PRIx " not implemented\n", offset);
26 break;
27 }
28 return 0x00;
29 }
30
31 static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
32 {
33 qemu_log_mask(LOG_UNIMP,
34 "Register 0x%" HWADDR_PRIx " not implemented\n", offset);
35 }
36
37 static const MemoryRegionOps pll_ops = {
38 .read = pll_read,
39 .write = pll_write,
40 .endianness = DEVICE_LITTLE_ENDIAN,
41 .impl = {
42 .min_access_size = 4,
43 .max_access_size = 4,
44 },
45 .valid = {
46 .min_access_size = 4,
47 .max_access_size = 4,
48 }
49 };
50
51 static void ax3000_clk_init(Object *obj)
52 {
53 Ax3000ClkState *s = AX3000_CLK(obj);
54
55 memory_region_init_io(&s->pll_ctrl, obj, &pll_ops, s,
56 TYPE_AX3000_CLK, AX3000_CLK_PLL_CTRL_SIZE);
57 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->pll_ctrl);
58 }
59
60 static void ax3000_clk_class_init(ObjectClass *klass, const void *data)
61 {
62 DeviceClass *dc = DEVICE_CLASS(klass);
63
64 dc->desc = "Axiado AX3000 Clock Control";
65 }
66
67 static const TypeInfo ax3000_clk_info = {
68 .parent = TYPE_SYS_BUS_DEVICE,
69 .name = TYPE_AX3000_CLK,
70 .instance_size = sizeof(Ax3000ClkState),
71 .instance_init = ax3000_clk_init,
72 .class_init = ax3000_clk_class_init,
73 };
74
75 static void axiado_clk_register_type(void)
76 {
77 type_register_static(&ax3000_clk_info);
78 }
79 type_init(axiado_clk_register_type);