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1 /*
2 * QEMU Sparc Sun4m ECC memory controller emulation
3 *
4 * Copyright (c) 2007 Robert Reif
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/core/irq.h"
27 #include "hw/core/qdev-properties.h"
28 #include "hw/core/sysbus.h"
29 #include "migration/vmstate.h"
30 #include "qemu/module.h"
31 #include "trace.h"
32 #include "qom/object.h"
33
34 /* There are 3 versions of this chip used in SMP sun4m systems:
35 * MCC (version 0, implementation 0) SS-600MP
36 * EMC (version 0, implementation 1) SS-10
37 * SMC (version 0, implementation 2) SS-10SX and SS-20
38 *
39 * Chipset docs:
40 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
41 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
42 */
43
44 #define ECC_MCC 0x00000000
45 #define ECC_EMC 0x10000000
46 #define ECC_SMC 0x20000000
47
48 /* Register indexes */
49 #define ECC_MER 0 /* Memory Enable Register */
50 #define ECC_MDR 1 /* Memory Delay Register */
51 #define ECC_MFSR 2 /* Memory Fault Status Register */
52 #define ECC_VCR 3 /* Video Configuration Register */
53 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
54 #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */
55 #define ECC_DR 6 /* Diagnostic Register */
56 #define ECC_ECR0 7 /* Event Count Register 0 */
57 #define ECC_ECR1 8 /* Event Count Register 1 */
58
59 /* ECC fault control register */
60 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
61 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on
62 correctable errors */
63 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
64 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
65 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
66 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
67 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
68 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
69 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
70 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
71 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */
72 #define ECC_MER_MRR 0x000003fc /* MRR mask */
73 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */
74 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
75 #define ECC_MER_VER 0x0f000000 /* Version */
76 #define ECC_MER_IMPL 0xf0000000 /* Implementation */
77 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */
78 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */
79 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */
80
81 /* ECC memory delay register */
82 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
83 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */
84 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
85 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
86 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
87 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
88 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */
89 #define ECC_MDR_MASK 0x7fffffff
90
91 /* ECC fault status register */
92 #define ECC_MFSR_CE 0x00000001 /* Correctable error */
93 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
94 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */
95 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
96 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
97 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
98 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */
99 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
100
101 /* ECC fault address register 0 */
102 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
103 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
104 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
105 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
106 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
107 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
108 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
109 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
110 #define ECC_MFARO_MID 0xf0000000 /* Module ID */
111
112 /* ECC diagnostic register */
113 #define ECC_DR_CBX 0x00000001
114 #define ECC_DR_CB0 0x00000002
115 #define ECC_DR_CB1 0x00000004
116 #define ECC_DR_CB2 0x00000008
117 #define ECC_DR_CB4 0x00000010
118 #define ECC_DR_CB8 0x00000020
119 #define ECC_DR_CB16 0x00000040
120 #define ECC_DR_CB32 0x00000080
121 #define ECC_DR_DMODE 0x00000c00
122
123 #define ECC_NREGS 9
124 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
125
126 #define ECC_DIAG_SIZE 4
127 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
128
129 #define TYPE_ECC_MEMCTL "eccmemctl"
130 OBJECT_DECLARE_SIMPLE_TYPE(ECCState, ECC_MEMCTL)
131
132 struct ECCState {
133 SysBusDevice parent_obj;
134
135 MemoryRegion iomem, iomem_diag;
136 qemu_irq irq;
137 uint32_t regs[ECC_NREGS];
138 uint8_t diag[ECC_DIAG_SIZE];
139 uint32_t version;
140 };
141
142 static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
143 unsigned size)
144 {
145 ECCState *s = opaque;
146
147 switch (addr >> 2) {
148 case ECC_MER:
149 if (s->version == ECC_MCC)
150 s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
151 else if (s->version == ECC_EMC)
152 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
153 else if (s->version == ECC_SMC)
154 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
155 trace_ecc_mem_writel_mer(val);
156 break;
157 case ECC_MDR:
158 s->regs[ECC_MDR] = val & ECC_MDR_MASK;
159 trace_ecc_mem_writel_mdr(val);
160 break;
161 case ECC_MFSR:
162 s->regs[ECC_MFSR] = val;
163 qemu_irq_lower(s->irq);
164 trace_ecc_mem_writel_mfsr(val);
165 break;
166 case ECC_VCR:
167 s->regs[ECC_VCR] = val;
168 trace_ecc_mem_writel_vcr(val);
169 break;
170 case ECC_DR:
171 s->regs[ECC_DR] = val;
172 trace_ecc_mem_writel_dr(val);
173 break;
174 case ECC_ECR0:
175 s->regs[ECC_ECR0] = val;
176 trace_ecc_mem_writel_ecr0(val);
177 break;
178 case ECC_ECR1:
179 s->regs[ECC_ECR0] = val;
180 trace_ecc_mem_writel_ecr1(val);
181 break;
182 }
183 }
184
185 static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
186 unsigned size)
187 {
188 ECCState *s = opaque;
189 uint32_t ret = 0;
190
191 switch (addr >> 2) {
192 case ECC_MER:
193 ret = s->regs[ECC_MER];
194 trace_ecc_mem_readl_mer(ret);
195 break;
196 case ECC_MDR:
197 ret = s->regs[ECC_MDR];
198 trace_ecc_mem_readl_mdr(ret);
199 break;
200 case ECC_MFSR:
201 ret = s->regs[ECC_MFSR];
202 trace_ecc_mem_readl_mfsr(ret);
203 break;
204 case ECC_VCR:
205 ret = s->regs[ECC_VCR];
206 trace_ecc_mem_readl_vcr(ret);
207 break;
208 case ECC_MFAR0:
209 ret = s->regs[ECC_MFAR0];
210 trace_ecc_mem_readl_mfar0(ret);
211 break;
212 case ECC_MFAR1:
213 ret = s->regs[ECC_MFAR1];
214 trace_ecc_mem_readl_mfar1(ret);
215 break;
216 case ECC_DR:
217 ret = s->regs[ECC_DR];
218 trace_ecc_mem_readl_dr(ret);
219 break;
220 case ECC_ECR0:
221 ret = s->regs[ECC_ECR0];
222 trace_ecc_mem_readl_ecr0(ret);
223 break;
224 case ECC_ECR1:
225 ret = s->regs[ECC_ECR0];
226 trace_ecc_mem_readl_ecr1(ret);
227 break;
228 }
229 return ret;
230 }
231
232 static const MemoryRegionOps ecc_mem_ops = {
233 .read = ecc_mem_read,
234 .write = ecc_mem_write,
235 .endianness = DEVICE_BIG_ENDIAN,
236 .valid = {
237 .min_access_size = 4,
238 .max_access_size = 4,
239 },
240 };
241
242 static void ecc_diag_mem_write(void *opaque, hwaddr addr,
243 uint64_t val, unsigned size)
244 {
245 ECCState *s = opaque;
246
247 trace_ecc_diag_mem_writeb(addr, val);
248 s->diag[addr & ECC_DIAG_MASK] = val;
249 }
250
251 static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
252 unsigned size)
253 {
254 ECCState *s = opaque;
255 uint32_t ret = s->diag[(int)addr];
256
257 trace_ecc_diag_mem_readb(addr, ret);
258 return ret;
259 }
260
261 static const MemoryRegionOps ecc_diag_mem_ops = {
262 .read = ecc_diag_mem_read,
263 .write = ecc_diag_mem_write,
264 .endianness = DEVICE_NATIVE_ENDIAN,
265 .valid = {
266 .min_access_size = 1,
267 .max_access_size = 1,
268 },
269 };
270
271 static const VMStateDescription vmstate_ecc = {
272 .name ="ECC",
273 .version_id = 3,
274 .minimum_version_id = 3,
275 .fields = (const VMStateField[]) {
276 VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
277 VMSTATE_BUFFER(diag, ECCState),
278 VMSTATE_UINT32(version, ECCState),
279 VMSTATE_END_OF_LIST()
280 }
281 };
282
283 static void ecc_reset(DeviceState *d)
284 {
285 ECCState *s = ECC_MEMCTL(d);
286
287 if (s->version == ECC_MCC) {
288 s->regs[ECC_MER] &= ECC_MER_REU;
289 } else {
290 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
291 ECC_MER_DCI);
292 }
293 s->regs[ECC_MDR] = 0x20;
294 s->regs[ECC_MFSR] = 0;
295 s->regs[ECC_VCR] = 0;
296 s->regs[ECC_MFAR0] = 0x07c00000;
297 s->regs[ECC_MFAR1] = 0;
298 s->regs[ECC_DR] = 0;
299 s->regs[ECC_ECR0] = 0;
300 s->regs[ECC_ECR1] = 0;
301 }
302
303 static void ecc_init(Object *obj)
304 {
305 ECCState *s = ECC_MEMCTL(obj);
306 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
307
308 sysbus_init_irq(dev, &s->irq);
309
310 memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE);
311 sysbus_init_mmio(dev, &s->iomem);
312 }
313
314 static void ecc_realize(DeviceState *dev, Error **errp)
315 {
316 ECCState *s = ECC_MEMCTL(dev);
317 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
318
319 s->regs[0] = s->version;
320
321 if (s->version == ECC_MCC) { // SS-600MP only
322 memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,
323 "ecc.diag", ECC_DIAG_SIZE);
324 sysbus_init_mmio(sbd, &s->iomem_diag);
325 }
326 }
327
328 static const Property ecc_properties[] = {
329 DEFINE_PROP_UINT32("version", ECCState, version, -1),
330 };
331
332 static void ecc_class_init(ObjectClass *klass, const void *data)
333 {
334 DeviceClass *dc = DEVICE_CLASS(klass);
335
336 dc->realize = ecc_realize;
337 device_class_set_legacy_reset(dc, ecc_reset);
338 dc->vmsd = &vmstate_ecc;
339 device_class_set_props(dc, ecc_properties);
340 }
341
342 static const TypeInfo ecc_info = {
343 .name = TYPE_ECC_MEMCTL,
344 .parent = TYPE_SYS_BUS_DEVICE,
345 .instance_size = sizeof(ECCState),
346 .instance_init = ecc_init,
347 .class_init = ecc_class_init,
348 };
349
350
351 static void ecc_register_types(void)
352 {
353 type_register_static(&ecc_info);
354 }
355
356 type_init(ecc_register_types)