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1 /*
2 * IMX31 Clock Control Module
3 *
4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 *
10 * To get the timer frequencies right, we need to emulate at least part of
11 * the i.MX31 CCM.
12 */
13
14 #include "qemu/osdep.h"
15 #include "hw/misc/imx31_ccm.h"
16 #include "migration/vmstate.h"
17 #include "qemu/log.h"
18 #include "qemu/module.h"
19 #include "trace.h"
20
21 #define CKIH_FREQ 26000000 /* 26MHz crystal input */
22
23 static const char *imx31_ccm_reg_name(uint32_t reg)
24 {
25 static char unknown[20];
26
27 switch (reg) {
28 case IMX31_CCM_CCMR_REG:
29 return "CCMR";
30 case IMX31_CCM_PDR0_REG:
31 return "PDR0";
32 case IMX31_CCM_PDR1_REG:
33 return "PDR1";
34 case IMX31_CCM_RCSR_REG:
35 return "RCSR";
36 case IMX31_CCM_MPCTL_REG:
37 return "MPCTL";
38 case IMX31_CCM_UPCTL_REG:
39 return "UPCTL";
40 case IMX31_CCM_SPCTL_REG:
41 return "SPCTL";
42 case IMX31_CCM_COSR_REG:
43 return "COSR";
44 case IMX31_CCM_CGR0_REG:
45 return "CGR0";
46 case IMX31_CCM_CGR1_REG:
47 return "CGR1";
48 case IMX31_CCM_CGR2_REG:
49 return "CGR2";
50 case IMX31_CCM_WIMR_REG:
51 return "WIMR";
52 case IMX31_CCM_LDC_REG:
53 return "LDC";
54 case IMX31_CCM_DCVR0_REG:
55 return "DCVR0";
56 case IMX31_CCM_DCVR1_REG:
57 return "DCVR1";
58 case IMX31_CCM_DCVR2_REG:
59 return "DCVR2";
60 case IMX31_CCM_DCVR3_REG:
61 return "DCVR3";
62 case IMX31_CCM_LTR0_REG:
63 return "LTR0";
64 case IMX31_CCM_LTR1_REG:
65 return "LTR1";
66 case IMX31_CCM_LTR2_REG:
67 return "LTR2";
68 case IMX31_CCM_LTR3_REG:
69 return "LTR3";
70 case IMX31_CCM_LTBR0_REG:
71 return "LTBR0";
72 case IMX31_CCM_LTBR1_REG:
73 return "LTBR1";
74 case IMX31_CCM_PMCR0_REG:
75 return "PMCR0";
76 case IMX31_CCM_PMCR1_REG:
77 return "PMCR1";
78 case IMX31_CCM_PDR2_REG:
79 return "PDR2";
80 default:
81 snprintf(unknown, sizeof(unknown), "[%u ?]", reg);
82 return unknown;
83 }
84 }
85
86 static const VMStateDescription vmstate_imx31_ccm = {
87 .name = TYPE_IMX31_CCM,
88 .version_id = 2,
89 .minimum_version_id = 2,
90 .fields = (const VMStateField[]) {
91 VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
92 VMSTATE_END_OF_LIST()
93 },
94 };
95
96 static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
97 {
98 uint32_t freq = 0;
99 IMX31CCMState *s = IMX31_CCM(dev);
100
101 if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
102 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
103 freq = CKIL_FREQ;
104 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
105 freq *= 1024;
106 }
107 }
108 } else {
109 freq = CKIH_FREQ;
110 }
111
112 trace_imx31_ccm_get_pll_ref_clk(freq);
113
114 return freq;
115 }
116
117 static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
118 {
119 uint32_t freq;
120 IMX31CCMState *s = IMX31_CCM(dev);
121
122 freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
123 imx31_ccm_get_pll_ref_clk(dev));
124
125 trace_imx31_ccm_get_mpll_clk(freq);
126
127 return freq;
128 }
129
130 static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
131 {
132 uint32_t freq;
133 IMX31CCMState *s = IMX31_CCM(dev);
134
135 if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
136 !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
137 freq = imx31_ccm_get_pll_ref_clk(dev);
138 } else {
139 freq = imx31_ccm_get_mpll_clk(dev);
140 }
141
142 trace_imx31_ccm_get_mcu_main_clk(freq);
143
144 return freq;
145 }
146
147 static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
148 {
149 uint32_t freq;
150 IMX31CCMState *s = IMX31_CCM(dev);
151
152 freq = imx31_ccm_get_mcu_main_clk(dev)
153 / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
154
155 trace_imx31_ccm_get_hclk_clk(freq);
156
157 return freq;
158 }
159
160 static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
161 {
162 uint32_t freq;
163 IMX31CCMState *s = IMX31_CCM(dev);
164
165 freq = imx31_ccm_get_hclk_clk(dev)
166 / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
167
168 trace_imx31_ccm_get_ipg_clk(freq);
169
170 return freq;
171 }
172
173 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
174 {
175 uint32_t freq = 0;
176
177 switch (clock) {
178 case CLK_NONE:
179 break;
180 case CLK_IPG:
181 case CLK_IPG_HIGH:
182 freq = imx31_ccm_get_ipg_clk(dev);
183 break;
184 case CLK_32k:
185 freq = CKIL_FREQ;
186 break;
187 default:
188 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
189 TYPE_IMX31_CCM, __func__, clock);
190 break;
191 }
192
193 trace_imx31_ccm_get_clock_frequency(clock, freq);
194
195 return freq;
196 }
197
198 static void imx31_ccm_reset(DeviceState *dev)
199 {
200 IMX31CCMState *s = IMX31_CCM(dev);
201
202 memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
203
204 s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
205 s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
206 s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
207 s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
208 s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
209 s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
210 s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
211 s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
212 s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
213 s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
214 s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
215 s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
216 s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
217 s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
218 s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
219 s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
220 }
221
222 static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
223 {
224 uint32_t value = 0;
225 IMX31CCMState *s = (IMX31CCMState *)opaque;
226
227 if ((offset >> 2) < IMX31_CCM_MAX_REG) {
228 value = s->reg[offset >> 2];
229 } else {
230 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
231 HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
232 }
233
234 trace_imx31_ccm_read(imx31_ccm_reg_name(offset >> 2), value);
235
236 return (uint64_t)value;
237 }
238
239 static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
240 unsigned size)
241 {
242 IMX31CCMState *s = (IMX31CCMState *)opaque;
243
244 trace_imx31_ccm_write(imx31_ccm_reg_name(offset >> 2), value);
245
246 switch (offset >> 2) {
247 case IMX31_CCM_CCMR_REG:
248 s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
249 break;
250 case IMX31_CCM_PDR0_REG:
251 s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
252 break;
253 case IMX31_CCM_PDR1_REG:
254 s->reg[IMX31_CCM_PDR1_REG] = value;
255 break;
256 case IMX31_CCM_MPCTL_REG:
257 s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
258 break;
259 case IMX31_CCM_SPCTL_REG:
260 s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
261 break;
262 case IMX31_CCM_CGR0_REG:
263 s->reg[IMX31_CCM_CGR0_REG] = value;
264 break;
265 case IMX31_CCM_CGR1_REG:
266 s->reg[IMX31_CCM_CGR1_REG] = value;
267 break;
268 case IMX31_CCM_CGR2_REG:
269 s->reg[IMX31_CCM_CGR2_REG] = value;
270 break;
271 default:
272 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
273 HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
274 break;
275 }
276 }
277
278 static const struct MemoryRegionOps imx31_ccm_ops = {
279 .read = imx31_ccm_read,
280 .write = imx31_ccm_write,
281 .endianness = DEVICE_NATIVE_ENDIAN,
282 .valid = {
283 /*
284 * Our device would not work correctly if the guest was doing
285 * unaligned access. This might not be a limitation on the real
286 * device but in practice there is no reason for a guest to access
287 * this device unaligned.
288 */
289 .min_access_size = 4,
290 .max_access_size = 4,
291 .unaligned = false,
292 },
293
294 };
295
296 static void imx31_ccm_init(Object *obj)
297 {
298 DeviceState *dev = DEVICE(obj);
299 SysBusDevice *sd = SYS_BUS_DEVICE(obj);
300 IMX31CCMState *s = IMX31_CCM(obj);
301
302 memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
303 TYPE_IMX31_CCM, 0x1000);
304 sysbus_init_mmio(sd, &s->iomem);
305 }
306
307 static void imx31_ccm_class_init(ObjectClass *klass, const void *data)
308 {
309 DeviceClass *dc = DEVICE_CLASS(klass);
310 IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
311
312 device_class_set_legacy_reset(dc, imx31_ccm_reset);
313 dc->vmsd = &vmstate_imx31_ccm;
314 dc->desc = "i.MX31 Clock Control Module";
315
316 ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
317 }
318
319 static const TypeInfo imx31_ccm_info = {
320 .name = TYPE_IMX31_CCM,
321 .parent = TYPE_IMX_CCM,
322 .instance_size = sizeof(IMX31CCMState),
323 .instance_init = imx31_ccm_init,
324 .class_init = imx31_ccm_class_init,
325 };
326
327 static void imx31_ccm_register_types(void)
328 {
329 type_register_static(&imx31_ccm_info);
330 }
331
332 type_init(imx31_ccm_register_types)