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1 /*
2 * ARM IoTKit system control element
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /*
13 * This is a model of the "system control element" which is part of the
14 * Arm IoTKit and documented in
15 * https://developer.arm.com/documentation/ecm0601256/latest
16 * Specifically, it implements the "system control register" blocks.
17 */
18
19 #include "qemu/osdep.h"
20 #include "qemu/bitops.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "system/runstate.h"
24 #include "trace.h"
25 #include "qapi/error.h"
26 #include "hw/core/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "hw/core/registerfields.h"
29 #include "hw/misc/iotkit-sysctl.h"
30 #include "hw/core/qdev-properties.h"
31 #include "hw/arm/armsse-version.h"
32 #include "target/arm/arm-powerctl.h"
33
34 REG32(SECDBGSTAT, 0x0)
35 REG32(SECDBGSET, 0x4)
36 REG32(SECDBGCLR, 0x8)
37 REG32(SCSECCTRL, 0xc)
38 REG32(FCLK_DIV, 0x10)
39 REG32(SYSCLK_DIV, 0x14)
40 REG32(CLOCK_FORCE, 0x18)
41 REG32(RESET_SYNDROME, 0x100)
42 REG32(RESET_MASK, 0x104)
43 REG32(SWRESET, 0x108)
44 FIELD(SWRESET, SWRESETREQ, 9, 1)
45 REG32(GRETREG, 0x10c)
46 REG32(INITSVTOR0, 0x110)
47 FIELD(INITSVTOR0, LOCK, 0, 1)
48 FIELD(INITSVTOR0, VTOR, 7, 25)
49 REG32(INITSVTOR1, 0x114)
50 REG32(CPUWAIT, 0x118)
51 REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
52 REG32(WICCTRL, 0x120)
53 REG32(EWCTRL, 0x124)
54 REG32(PPUINTSTAT, 0x128)
55 REG32(PWRCTRL, 0x1fc)
56 FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1)
57 FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1)
58 REG32(PDCM_PD_SYS_SENSE, 0x200)
59 REG32(PDCM_PD_CPU0_SENSE, 0x204)
60 REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
61 REG32(PDCM_PD_SRAM1_SENSE, 0x210)
62 REG32(PDCM_PD_SRAM2_SENSE, 0x214) /* PDCM_PD_VMR0_SENSE on SSE300 */
63 REG32(PDCM_PD_SRAM3_SENSE, 0x218) /* PDCM_PD_VMR1_SENSE on SSE300 */
64 REG32(PID4, 0xfd0)
65 REG32(PID5, 0xfd4)
66 REG32(PID6, 0xfd8)
67 REG32(PID7, 0xfdc)
68 REG32(PID0, 0xfe0)
69 REG32(PID1, 0xfe4)
70 REG32(PID2, 0xfe8)
71 REG32(PID3, 0xfec)
72 REG32(CID0, 0xff0)
73 REG32(CID1, 0xff4)
74 REG32(CID2, 0xff8)
75 REG32(CID3, 0xffc)
76
77 /* PID/CID values */
78 static const int iotkit_sysctl_id[] = {
79 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
80 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
81 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
82 };
83
84 /* Also used by the SSE300 */
85 static const int sse200_sysctl_id[] = {
86 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
87 0x54, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
88 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
89 };
90
91 static const int sse310_sysctl_id[] = {
92 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
93 0x54, 0xb8, 0x4b, 0x00, /* PID0..PID3 */
94 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
95 };
96
97 /*
98 * Set the initial secure vector table offset address for the core.
99 * This will take effect when the CPU next resets.
100 */
101 static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
102 {
103 Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
104
105 if (cpuobj) {
106 if (object_property_find(cpuobj, "init-svtor")) {
107 object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort);
108 }
109 }
110 }
111
112 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
113 unsigned size)
114 {
115 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
116 uint64_t r;
117
118 switch (offset) {
119 case A_SECDBGSTAT:
120 r = s->secure_debug;
121 break;
122 case A_SCSECCTRL:
123 switch (s->sse_version) {
124 case ARMSSE_IOTKIT:
125 goto bad_offset;
126 case ARMSSE_SSE200:
127 case ARMSSE_SSE300:
128 case ARMSSE_SSE310:
129 r = s->scsecctrl;
130 break;
131 default:
132 g_assert_not_reached();
133 }
134 break;
135 case A_FCLK_DIV:
136 switch (s->sse_version) {
137 case ARMSSE_IOTKIT:
138 goto bad_offset;
139 case ARMSSE_SSE200:
140 case ARMSSE_SSE300:
141 case ARMSSE_SSE310:
142 r = s->fclk_div;
143 break;
144 default:
145 g_assert_not_reached();
146 }
147 break;
148 case A_SYSCLK_DIV:
149 switch (s->sse_version) {
150 case ARMSSE_IOTKIT:
151 goto bad_offset;
152 case ARMSSE_SSE200:
153 case ARMSSE_SSE300:
154 case ARMSSE_SSE310:
155 r = s->sysclk_div;
156 break;
157 default:
158 g_assert_not_reached();
159 }
160 break;
161 case A_CLOCK_FORCE:
162 switch (s->sse_version) {
163 case ARMSSE_IOTKIT:
164 goto bad_offset;
165 case ARMSSE_SSE200:
166 case ARMSSE_SSE300:
167 case ARMSSE_SSE310:
168 r = s->clock_force;
169 break;
170 default:
171 g_assert_not_reached();
172 }
173 break;
174 case A_RESET_SYNDROME:
175 r = s->reset_syndrome;
176 break;
177 case A_RESET_MASK:
178 r = s->reset_mask;
179 break;
180 case A_GRETREG:
181 r = s->gretreg;
182 break;
183 case A_INITSVTOR0:
184 r = s->initsvtor0;
185 break;
186 case A_INITSVTOR1:
187 switch (s->sse_version) {
188 case ARMSSE_IOTKIT:
189 goto bad_offset;
190 case ARMSSE_SSE200:
191 r = s->initsvtor1;
192 break;
193 case ARMSSE_SSE300:
194 case ARMSSE_SSE310:
195 goto bad_offset;
196 default:
197 g_assert_not_reached();
198 }
199 break;
200 case A_CPUWAIT:
201 switch (s->sse_version) {
202 case ARMSSE_IOTKIT:
203 case ARMSSE_SSE200:
204 r = s->cpuwait;
205 break;
206 case ARMSSE_SSE300:
207 case ARMSSE_SSE310:
208 /* In SSE300 this is reserved (for INITSVTOR2) */
209 goto bad_offset;
210 default:
211 g_assert_not_reached();
212 }
213 break;
214 case A_NMI_ENABLE:
215 switch (s->sse_version) {
216 case ARMSSE_IOTKIT:
217 /* In IoTKit this is named BUSWAIT but marked reserved, R/O, zero */
218 r = 0;
219 break;
220 case ARMSSE_SSE200:
221 r = s->nmi_enable;
222 break;
223 case ARMSSE_SSE300:
224 case ARMSSE_SSE310:
225 /* In SSE300 this is reserved (for INITSVTOR3) */
226 goto bad_offset;
227 default:
228 g_assert_not_reached();
229 }
230 break;
231 case A_WICCTRL:
232 switch (s->sse_version) {
233 case ARMSSE_IOTKIT:
234 case ARMSSE_SSE200:
235 r = s->wicctrl;
236 break;
237 case ARMSSE_SSE300:
238 case ARMSSE_SSE310:
239 /* In SSE300 and SSE310 this offset is CPUWAIT */
240 r = s->cpuwait;
241 break;
242 default:
243 g_assert_not_reached();
244 }
245 break;
246 case A_EWCTRL:
247 switch (s->sse_version) {
248 case ARMSSE_IOTKIT:
249 goto bad_offset;
250 case ARMSSE_SSE200:
251 r = s->ewctrl;
252 break;
253 case ARMSSE_SSE300:
254 case ARMSSE_SSE310:
255 /* In SSE300 and SSE310 this offset is NMI_ENABLE */
256 r = s->nmi_enable;
257 break;
258 default:
259 g_assert_not_reached();
260 }
261 break;
262 case A_PPUINTSTAT:
263 switch (s->sse_version) {
264 case ARMSSE_IOTKIT:
265 case ARMSSE_SSE200:
266 case ARMSSE_SSE300:
267 goto bad_offset;
268 case ARMSSE_SSE310:
269 qemu_log_mask(LOG_UNIMP,
270 "IoTKit SysCtl PPUINTSTAT unimplemented\n");
271 r = 0;
272 break;
273 default:
274 g_assert_not_reached();
275 }
276 break;
277 case A_PWRCTRL:
278 switch (s->sse_version) {
279 case ARMSSE_IOTKIT:
280 case ARMSSE_SSE200:
281 goto bad_offset;
282 case ARMSSE_SSE300:
283 case ARMSSE_SSE310:
284 r = s->pwrctrl;
285 break;
286 default:
287 g_assert_not_reached();
288 }
289 break;
290 case A_PDCM_PD_SYS_SENSE:
291 switch (s->sse_version) {
292 case ARMSSE_IOTKIT:
293 goto bad_offset;
294 case ARMSSE_SSE200:
295 case ARMSSE_SSE300:
296 case ARMSSE_SSE310:
297 r = s->pdcm_pd_sys_sense;
298 break;
299 default:
300 g_assert_not_reached();
301 }
302 break;
303 case A_PDCM_PD_CPU0_SENSE:
304 switch (s->sse_version) {
305 case ARMSSE_IOTKIT:
306 case ARMSSE_SSE200:
307 goto bad_offset;
308 case ARMSSE_SSE300:
309 case ARMSSE_SSE310:
310 r = s->pdcm_pd_cpu0_sense;
311 break;
312 default:
313 g_assert_not_reached();
314 }
315 break;
316 case A_PDCM_PD_SRAM0_SENSE:
317 switch (s->sse_version) {
318 case ARMSSE_IOTKIT:
319 goto bad_offset;
320 case ARMSSE_SSE200:
321 r = s->pdcm_pd_sram0_sense;
322 break;
323 case ARMSSE_SSE300:
324 case ARMSSE_SSE310:
325 goto bad_offset;
326 default:
327 g_assert_not_reached();
328 }
329 break;
330 case A_PDCM_PD_SRAM1_SENSE:
331 switch (s->sse_version) {
332 case ARMSSE_IOTKIT:
333 goto bad_offset;
334 case ARMSSE_SSE200:
335 r = s->pdcm_pd_sram1_sense;
336 break;
337 case ARMSSE_SSE300:
338 case ARMSSE_SSE310:
339 goto bad_offset;
340 default:
341 g_assert_not_reached();
342 }
343 break;
344 case A_PDCM_PD_SRAM2_SENSE:
345 switch (s->sse_version) {
346 case ARMSSE_IOTKIT:
347 goto bad_offset;
348 case ARMSSE_SSE200:
349 r = s->pdcm_pd_sram2_sense;
350 break;
351 case ARMSSE_SSE300:
352 case ARMSSE_SSE310:
353 r = s->pdcm_pd_vmr0_sense;
354 break;
355 default:
356 g_assert_not_reached();
357 }
358 break;
359 case A_PDCM_PD_SRAM3_SENSE:
360 switch (s->sse_version) {
361 case ARMSSE_IOTKIT:
362 goto bad_offset;
363 case ARMSSE_SSE200:
364 r = s->pdcm_pd_sram3_sense;
365 break;
366 case ARMSSE_SSE300:
367 case ARMSSE_SSE310:
368 r = s->pdcm_pd_vmr1_sense;
369 break;
370 default:
371 g_assert_not_reached();
372 }
373 break;
374 case A_PID4 ... A_CID3:
375 switch (s->sse_version) {
376 case ARMSSE_IOTKIT:
377 r = iotkit_sysctl_id[(offset - A_PID4) / 4];
378 break;
379 case ARMSSE_SSE200:
380 case ARMSSE_SSE300:
381 r = sse200_sysctl_id[(offset - A_PID4) / 4];
382 break;
383 case ARMSSE_SSE310:
384 r = sse310_sysctl_id[(offset - A_PID4) / 4];
385 break;
386 default:
387 g_assert_not_reached();
388 }
389 break;
390 case A_SECDBGSET:
391 case A_SECDBGCLR:
392 case A_SWRESET:
393 qemu_log_mask(LOG_GUEST_ERROR,
394 "IoTKit SysCtl read: read of WO offset %x\n",
395 (int)offset);
396 r = 0;
397 break;
398 default:
399 bad_offset:
400 qemu_log_mask(LOG_GUEST_ERROR,
401 "IoTKit SysCtl read: bad offset %x\n", (int)offset);
402 r = 0;
403 break;
404 }
405 trace_iotkit_sysctl_read(offset, r, size);
406 return r;
407 }
408
409 static void cpuwait_write(IoTKitSysCtl *s, uint32_t value)
410 {
411 int num_cpus = (s->sse_version == ARMSSE_SSE300 ||
412 s->sse_version == ARMSSE_SSE310) ? 1 : 2;
413 int i;
414
415 for (i = 0; i < num_cpus; i++) {
416 uint32_t mask = 1 << i;
417 if ((s->cpuwait & mask) && !(value & mask)) {
418 /* Powering up CPU 0 */
419 arm_set_cpu_on_and_reset(i);
420 }
421 }
422 s->cpuwait = value;
423 }
424
425 static void iotkit_sysctl_write(void *opaque, hwaddr offset,
426 uint64_t value, unsigned size)
427 {
428 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
429
430 trace_iotkit_sysctl_write(offset, value, size);
431
432 /*
433 * Most of the state here has to do with control of reset and
434 * similar kinds of power up -- for instance the guest can ask
435 * what the reason for the last reset was, or forbid reset for
436 * some causes (like the non-secure watchdog). Most of this is
437 * not relevant to QEMU, which doesn't really model anything other
438 * than a full power-on reset.
439 * We just model the registers as reads-as-written.
440 */
441
442 switch (offset) {
443 case A_RESET_SYNDROME:
444 qemu_log_mask(LOG_UNIMP,
445 "IoTKit SysCtl RESET_SYNDROME unimplemented\n");
446 s->reset_syndrome = value;
447 break;
448 case A_RESET_MASK:
449 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n");
450 s->reset_mask = value;
451 break;
452 case A_GRETREG:
453 /*
454 * General retention register, which is only reset by a power-on
455 * reset. Technically this implementation is complete, since
456 * QEMU only supports power-on resets...
457 */
458 s->gretreg = value;
459 break;
460 case A_INITSVTOR0:
461 switch (s->sse_version) {
462 case ARMSSE_SSE300:
463 case ARMSSE_SSE310:
464 /* SSE300, SSE310 have a LOCK bit which prevents further writes */
465 if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) {
466 qemu_log_mask(LOG_GUEST_ERROR,
467 "IoTKit INITSVTOR0 write when register locked\n");
468 break;
469 }
470 s->initsvtor0 = value;
471 set_init_vtor(0, s->initsvtor0 & R_INITSVTOR0_VTOR_MASK);
472 break;
473 case ARMSSE_IOTKIT:
474 case ARMSSE_SSE200:
475 s->initsvtor0 = value;
476 set_init_vtor(0, s->initsvtor0);
477 break;
478 default:
479 g_assert_not_reached();
480 }
481 break;
482 case A_CPUWAIT:
483 switch (s->sse_version) {
484 case ARMSSE_IOTKIT:
485 case ARMSSE_SSE200:
486 cpuwait_write(s, value);
487 break;
488 case ARMSSE_SSE300:
489 case ARMSSE_SSE310:
490 /* In SSE300 this is reserved (for INITSVTOR2) */
491 goto bad_offset;
492 default:
493 g_assert_not_reached();
494 }
495 break;
496 case A_WICCTRL:
497 switch (s->sse_version) {
498 case ARMSSE_IOTKIT:
499 case ARMSSE_SSE200:
500 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n");
501 s->wicctrl = value;
502 break;
503 case ARMSSE_SSE300:
504 case ARMSSE_SSE310:
505 /* In SSE300 and SSE310 this offset is CPUWAIT */
506 cpuwait_write(s, value);
507 break;
508 default:
509 g_assert_not_reached();
510 }
511 break;
512 case A_SECDBGSET:
513 /* write-1-to-set */
514 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n");
515 s->secure_debug |= value;
516 break;
517 case A_SECDBGCLR:
518 /* write-1-to-clear */
519 s->secure_debug &= ~value;
520 break;
521 case A_SWRESET:
522 /* One w/o bit to request a reset; all other bits reserved */
523 if (value & R_SWRESET_SWRESETREQ_MASK) {
524 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
525 }
526 break;
527 case A_SCSECCTRL:
528 switch (s->sse_version) {
529 case ARMSSE_IOTKIT:
530 goto bad_offset;
531 case ARMSSE_SSE200:
532 case ARMSSE_SSE300:
533 case ARMSSE_SSE310:
534 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
535 s->scsecctrl = value;
536 break;
537 default:
538 g_assert_not_reached();
539 }
540 break;
541 case A_FCLK_DIV:
542 switch (s->sse_version) {
543 case ARMSSE_IOTKIT:
544 goto bad_offset;
545 case ARMSSE_SSE200:
546 case ARMSSE_SSE300:
547 case ARMSSE_SSE310:
548 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
549 s->fclk_div = value;
550 break;
551 default:
552 g_assert_not_reached();
553 }
554 break;
555 case A_SYSCLK_DIV:
556 switch (s->sse_version) {
557 case ARMSSE_IOTKIT:
558 goto bad_offset;
559 case ARMSSE_SSE200:
560 case ARMSSE_SSE300:
561 case ARMSSE_SSE310:
562 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
563 s->sysclk_div = value;
564 break;
565 default:
566 g_assert_not_reached();
567 }
568 break;
569 case A_CLOCK_FORCE:
570 switch (s->sse_version) {
571 case ARMSSE_IOTKIT:
572 goto bad_offset;
573 case ARMSSE_SSE200:
574 case ARMSSE_SSE300:
575 case ARMSSE_SSE310:
576 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
577 s->clock_force = value;
578 break;
579 default:
580 g_assert_not_reached();
581 }
582 break;
583 case A_INITSVTOR1:
584 switch (s->sse_version) {
585 case ARMSSE_IOTKIT:
586 goto bad_offset;
587 case ARMSSE_SSE200:
588 s->initsvtor1 = value;
589 set_init_vtor(1, s->initsvtor1);
590 break;
591 case ARMSSE_SSE300:
592 case ARMSSE_SSE310:
593 goto bad_offset;
594 default:
595 g_assert_not_reached();
596 }
597 break;
598 case A_EWCTRL:
599 switch (s->sse_version) {
600 case ARMSSE_IOTKIT:
601 goto bad_offset;
602 case ARMSSE_SSE200:
603 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
604 s->ewctrl = value;
605 break;
606 case ARMSSE_SSE300:
607 case ARMSSE_SSE310:
608 /* In SSE300 and SSE310 this offset is NMI_ENABLE */
609 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
610 s->nmi_enable = value;
611 break;
612 default:
613 g_assert_not_reached();
614 }
615 break;
616 case A_PPUINTSTAT:
617 switch (s->sse_version) {
618 case ARMSSE_IOTKIT:
619 case ARMSSE_SSE200:
620 case ARMSSE_SSE300:
621 goto bad_offset;
622 case ARMSSE_SSE310:
623 goto ro_offset;
624 default:
625 g_assert_not_reached();
626 }
627 break;
628 case A_PWRCTRL:
629 switch (s->sse_version) {
630 case ARMSSE_IOTKIT:
631 case ARMSSE_SSE200:
632 goto bad_offset;
633 case ARMSSE_SSE300:
634 case ARMSSE_SSE310:
635 if (!(s->pwrctrl & R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK)) {
636 qemu_log_mask(LOG_GUEST_ERROR,
637 "IoTKit PWRCTRL write when register locked\n");
638 break;
639 }
640 s->pwrctrl = value;
641 break;
642 default:
643 g_assert_not_reached();
644 }
645 break;
646 case A_PDCM_PD_SYS_SENSE:
647 switch (s->sse_version) {
648 case ARMSSE_IOTKIT:
649 goto bad_offset;
650 case ARMSSE_SSE200:
651 case ARMSSE_SSE300:
652 case ARMSSE_SSE310:
653 qemu_log_mask(LOG_UNIMP,
654 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
655 s->pdcm_pd_sys_sense = value;
656 break;
657 default:
658 g_assert_not_reached();
659 }
660 break;
661 case A_PDCM_PD_CPU0_SENSE:
662 switch (s->sse_version) {
663 case ARMSSE_IOTKIT:
664 case ARMSSE_SSE200:
665 goto bad_offset;
666 case ARMSSE_SSE300:
667 case ARMSSE_SSE310:
668 qemu_log_mask(LOG_UNIMP,
669 "IoTKit SysCtl PDCM_PD_CPU0_SENSE unimplemented\n");
670 s->pdcm_pd_cpu0_sense = value;
671 break;
672 default:
673 g_assert_not_reached();
674 }
675 break;
676 case A_PDCM_PD_SRAM0_SENSE:
677 switch (s->sse_version) {
678 case ARMSSE_IOTKIT:
679 goto bad_offset;
680 case ARMSSE_SSE200:
681 qemu_log_mask(LOG_UNIMP,
682 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
683 s->pdcm_pd_sram0_sense = value;
684 break;
685 case ARMSSE_SSE300:
686 case ARMSSE_SSE310:
687 goto bad_offset;
688 default:
689 g_assert_not_reached();
690 }
691 break;
692 case A_PDCM_PD_SRAM1_SENSE:
693 switch (s->sse_version) {
694 case ARMSSE_IOTKIT:
695 goto bad_offset;
696 case ARMSSE_SSE200:
697 qemu_log_mask(LOG_UNIMP,
698 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
699 s->pdcm_pd_sram1_sense = value;
700 break;
701 case ARMSSE_SSE300:
702 case ARMSSE_SSE310:
703 goto bad_offset;
704 default:
705 g_assert_not_reached();
706 }
707 break;
708 case A_PDCM_PD_SRAM2_SENSE:
709 switch (s->sse_version) {
710 case ARMSSE_IOTKIT:
711 goto bad_offset;
712 case ARMSSE_SSE200:
713 qemu_log_mask(LOG_UNIMP,
714 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
715 s->pdcm_pd_sram2_sense = value;
716 break;
717 case ARMSSE_SSE300:
718 case ARMSSE_SSE310:
719 qemu_log_mask(LOG_UNIMP,
720 "IoTKit SysCtl PDCM_PD_VMR0_SENSE unimplemented\n");
721 s->pdcm_pd_vmr0_sense = value;
722 break;
723 default:
724 g_assert_not_reached();
725 }
726 break;
727 case A_PDCM_PD_SRAM3_SENSE:
728 switch (s->sse_version) {
729 case ARMSSE_IOTKIT:
730 goto bad_offset;
731 case ARMSSE_SSE200:
732 qemu_log_mask(LOG_UNIMP,
733 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
734 s->pdcm_pd_sram3_sense = value;
735 break;
736 case ARMSSE_SSE300:
737 case ARMSSE_SSE310:
738 qemu_log_mask(LOG_UNIMP,
739 "IoTKit SysCtl PDCM_PD_VMR1_SENSE unimplemented\n");
740 s->pdcm_pd_vmr1_sense = value;
741 break;
742 default:
743 g_assert_not_reached();
744 }
745 break;
746 case A_NMI_ENABLE:
747 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
748 switch (s->sse_version) {
749 case ARMSSE_IOTKIT:
750 goto ro_offset;
751 case ARMSSE_SSE200:
752 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
753 s->nmi_enable = value;
754 break;
755 case ARMSSE_SSE300:
756 case ARMSSE_SSE310:
757 /* In SSE300 this is reserved (for INITSVTOR3) */
758 goto bad_offset;
759 default:
760 g_assert_not_reached();
761 }
762 break;
763 case A_SECDBGSTAT:
764 case A_PID4 ... A_CID3:
765 ro_offset:
766 qemu_log_mask(LOG_GUEST_ERROR,
767 "IoTKit SysCtl write: write of RO offset %x\n",
768 (int)offset);
769 break;
770 default:
771 bad_offset:
772 qemu_log_mask(LOG_GUEST_ERROR,
773 "IoTKit SysCtl write: bad offset %x\n", (int)offset);
774 break;
775 }
776 }
777
778 static const MemoryRegionOps iotkit_sysctl_ops = {
779 .read = iotkit_sysctl_read,
780 .write = iotkit_sysctl_write,
781 .endianness = DEVICE_LITTLE_ENDIAN,
782 /* byte/halfword accesses are just zero-padded on reads and writes */
783 .impl.min_access_size = 4,
784 .impl.max_access_size = 4,
785 .valid.min_access_size = 1,
786 .valid.max_access_size = 4,
787 };
788
789 static void iotkit_sysctl_reset(DeviceState *dev)
790 {
791 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
792
793 trace_iotkit_sysctl_reset();
794 s->secure_debug = 0;
795 s->reset_syndrome = 1;
796 s->reset_mask = 0;
797 s->gretreg = 0;
798 s->initsvtor0 = s->initsvtor0_rst;
799 s->initsvtor1 = s->initsvtor1_rst;
800 s->cpuwait = s->cpuwait_rst;
801 s->wicctrl = 0;
802 s->scsecctrl = 0;
803 s->fclk_div = 0;
804 s->sysclk_div = 0;
805 s->clock_force = 0;
806 s->nmi_enable = 0;
807 s->ewctrl = 0;
808 s->pwrctrl = 0x3;
809 s->pdcm_pd_sys_sense = 0x7f;
810 s->pdcm_pd_sram0_sense = 0;
811 s->pdcm_pd_sram1_sense = 0;
812 s->pdcm_pd_sram2_sense = 0;
813 s->pdcm_pd_sram3_sense = 0;
814 s->pdcm_pd_cpu0_sense = 0;
815 s->pdcm_pd_vmr0_sense = 0;
816 s->pdcm_pd_vmr1_sense = 0;
817 }
818
819 static void iotkit_sysctl_init(Object *obj)
820 {
821 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
822 IoTKitSysCtl *s = IOTKIT_SYSCTL(obj);
823
824 memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops,
825 s, "iotkit-sysctl", 0x1000);
826 sysbus_init_mmio(sbd, &s->iomem);
827 }
828
829 static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
830 {
831 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
832
833 if (!armsse_version_valid(s->sse_version)) {
834 error_setg(errp, "invalid sse-version value %d", s->sse_version);
835 return;
836 }
837 }
838
839 static bool sse300_needed(void *opaque)
840 {
841 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
842
843 return s->sse_version == ARMSSE_SSE300 ||
844 s->sse_version == ARMSSE_SSE310;
845 }
846
847 static const VMStateDescription iotkit_sysctl_sse300_vmstate = {
848 .name = "iotkit-sysctl/sse-300",
849 .version_id = 1,
850 .minimum_version_id = 1,
851 .needed = sse300_needed,
852 .fields = (const VMStateField[]) {
853 VMSTATE_UINT32(pwrctrl, IoTKitSysCtl),
854 VMSTATE_UINT32(pdcm_pd_cpu0_sense, IoTKitSysCtl),
855 VMSTATE_UINT32(pdcm_pd_vmr0_sense, IoTKitSysCtl),
856 VMSTATE_UINT32(pdcm_pd_vmr1_sense, IoTKitSysCtl),
857 VMSTATE_END_OF_LIST()
858 }
859 };
860
861 static bool sse200_needed(void *opaque)
862 {
863 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
864
865 return s->sse_version != ARMSSE_IOTKIT;
866 }
867
868 static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
869 .name = "iotkit-sysctl/sse-200",
870 .version_id = 1,
871 .minimum_version_id = 1,
872 .needed = sse200_needed,
873 .fields = (const VMStateField[]) {
874 VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
875 VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
876 VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
877 VMSTATE_UINT32(clock_force, IoTKitSysCtl),
878 VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
879 VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
880 VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
881 VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
882 VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
883 VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
884 VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
885 VMSTATE_END_OF_LIST()
886 }
887 };
888
889 static const VMStateDescription iotkit_sysctl_vmstate = {
890 .name = "iotkit-sysctl",
891 .version_id = 1,
892 .minimum_version_id = 1,
893 .fields = (const VMStateField[]) {
894 VMSTATE_UINT32(secure_debug, IoTKitSysCtl),
895 VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
896 VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
897 VMSTATE_UINT32(gretreg, IoTKitSysCtl),
898 VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
899 VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
900 VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
901 VMSTATE_END_OF_LIST()
902 },
903 .subsections = (const VMStateDescription * const []) {
904 &iotkit_sysctl_sse200_vmstate,
905 &iotkit_sysctl_sse300_vmstate,
906 NULL
907 }
908 };
909
910 static const Property iotkit_sysctl_props[] = {
911 DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl, sse_version, 0),
912 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
913 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
914 0x10000000),
915 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
916 0x10000000),
917 };
918
919 static void iotkit_sysctl_class_init(ObjectClass *klass, const void *data)
920 {
921 DeviceClass *dc = DEVICE_CLASS(klass);
922
923 dc->vmsd = &iotkit_sysctl_vmstate;
924 device_class_set_legacy_reset(dc, iotkit_sysctl_reset);
925 device_class_set_props(dc, iotkit_sysctl_props);
926 dc->realize = iotkit_sysctl_realize;
927 }
928
929 static const TypeInfo iotkit_sysctl_info = {
930 .name = TYPE_IOTKIT_SYSCTL,
931 .parent = TYPE_SYS_BUS_DEVICE,
932 .instance_size = sizeof(IoTKitSysCtl),
933 .instance_init = iotkit_sysctl_init,
934 .class_init = iotkit_sysctl_class_init,
935 };
936
937 static void iotkit_sysctl_register_types(void)
938 {
939 type_register_static(&iotkit_sysctl_info);
940 }
941
942 type_init(iotkit_sysctl_register_types);