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1 /*
2 * Kendryte K230 DDR controller and PHY models
3 *
4 * Models the K230 DDRC CFG registers and K230 DDR PHY registers exercised
5 * by the K230 SDK U-Boot SPL.
6 *
7 * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "qemu/module.h"
15 #include "migration/vmstate.h"
16 #include "hw/core/registerfields.h"
17 #include "hw/core/resettable.h"
18 #include "hw/misc/k230_ddr.h"
19
20 /* DDRC CFG registers */
21
22 enum K230DDRCOperatingMode {
23 K230_DDRC_MODE_INIT = 0,
24 K230_DDRC_MODE_NORMAL = 1,
25 };
26
27 REG32(K230_DDRC_MSTR, 0x000)
28
29 REG32(K230_DDRC_STAT, 0x004)
30 FIELD(K230_DDRC_STAT, OPERATING_MODE, 0, 3)
31
32 REG32(K230_DDRC_PWRCTL, 0x030)
33
34 REG32(K230_DDRC_RFSHCTL0, 0x050)
35
36 REG32(K230_DDRC_RFSHTMG, 0x064)
37
38 REG32(K230_DDRC_RFSHTMG1, 0x068)
39
40 REG32(K230_DDRC_INIT0, 0x0d0)
41
42 REG32(K230_DDRC_INIT2, 0x0d8)
43
44 REG32(K230_DDRC_INIT3, 0x0dc)
45
46 REG32(K230_DDRC_INIT5, 0x0e4)
47
48 REG32(K230_DDRC_DRAMTMG0, 0x100)
49 #define R_K230_DDRC_DRAMTMG(index) \
50 (R_K230_DDRC_DRAMTMG0 + (index))
51
52 REG32(K230_DDRC_ZQCTL0, 0x180)
53
54 REG32(K230_DDRC_ZQCTL1, 0x184)
55
56 REG32(K230_DDRC_ZQCTL2, 0x188)
57
58 REG32(K230_DDRC_ZQSTAT, 0x18c)
59
60 REG32(K230_DDRC_DFITMG0, 0x190)
61
62 REG32(K230_DDRC_DFITMG1, 0x194)
63
64 REG32(K230_DDRC_DFIUPD0, 0x1a0)
65
66 REG32(K230_DDRC_DFIUPD1, 0x1a4)
67
68 REG32(K230_DDRC_DFIUPD2, 0x1a8)
69
70 REG32(K230_DDRC_DFIMISC, 0x1b0)
71 FIELD(K230_DDRC_DFIMISC, DFI_INIT_COMPLETE_EN, 0, 1)
72 FIELD(K230_DDRC_DFIMISC, DFI_INIT_START, 5, 1)
73
74 REG32(K230_DDRC_DFITMG2, 0x1b4)
75
76 REG32(K230_DDRC_DFISTAT, 0x1bc)
77 FIELD(K230_DDRC_DFISTAT, DFI_INIT_COMPLETE, 0, 1)
78
79 REG32(K230_DDRC_ODTCFG, 0x240)
80
81 REG32(K230_DDRC_SWCTL, 0x320)
82 FIELD(K230_DDRC_SWCTL, SW_DONE, 0, 1)
83
84 REG32(K230_DDRC_SWSTAT, 0x324)
85 FIELD(K230_DDRC_SWSTAT, SW_DONE_ACK, 0, 1)
86
87 static const uint32_t k230_ddrc_reset_values[K230_DDRC_REG_COUNT] = {
88 [R_K230_DDRC_MSTR] = 0x01040000,
89 [R_K230_DDRC_RFSHCTL0] = 0x00210000,
90 [R_K230_DDRC_RFSHTMG] = 0x0062008c,
91 [R_K230_DDRC_RFSHTMG1] = 0x0000008c,
92 [R_K230_DDRC_INIT0] = 0x0002004e,
93 [R_K230_DDRC_INIT3] = 0x00000510,
94 [R_K230_DDRC_INIT5] = 0x00100000,
95 [R_K230_DDRC_DRAMTMG(0)] = 0x0f101b0f,
96 [R_K230_DDRC_DRAMTMG(1)] = 0x00080414,
97 [R_K230_DDRC_DRAMTMG(2)] = 0x0305060d,
98 [R_K230_DDRC_DRAMTMG(3)] = 0x00004000,
99 [R_K230_DDRC_DRAMTMG(4)] = 0x05040405,
100 [R_K230_DDRC_DRAMTMG(5)] = 0x05050403,
101 [R_K230_DDRC_DRAMTMG(6)] = 0x02020005,
102 [R_K230_DDRC_DRAMTMG(7)] = 0x00000202,
103 [R_K230_DDRC_DRAMTMG(8)] = 0x03034405,
104 [R_K230_DDRC_DRAMTMG(9)] = 0x0004040d,
105 [R_K230_DDRC_DRAMTMG(10)] = 0x001c180a,
106 [R_K230_DDRC_DRAMTMG(11)] = 0x440c021c,
107 [R_K230_DDRC_DRAMTMG(12)] = 0x00020610,
108 [R_K230_DDRC_DRAMTMG(13)] = 0x1c200004,
109 [R_K230_DDRC_DRAMTMG(14)] = 0x000000a0,
110 [R_K230_DDRC_DRAMTMG(16)] = 0x05100404,
111 [R_K230_DDRC_ZQCTL0] = 0x02000040,
112 [R_K230_DDRC_ZQCTL1] = 0x02000100,
113 [R_K230_DDRC_DFITMG0] = 0x07020002,
114 [R_K230_DDRC_DFITMG1] = 0x00000404,
115 [R_K230_DDRC_DFIUPD0] = 0x00400003,
116 [R_K230_DDRC_DFIUPD1] = 0x00010001,
117 [R_K230_DDRC_DFIUPD2] = 0x80000000,
118 [R_K230_DDRC_DFIMISC] = 0x00000001,
119 [R_K230_DDRC_DFITMG2] = 0x00000202,
120 [R_K230_DDRC_ODTCFG] = 0x04000400,
121 [R_K230_DDRC_SWCTL] = 0x00000001,
122 [R_K230_DDRC_SWSTAT] = 0x00000001,
123 };
124
125 /* K230 DDR PHY CSRs use byte offset = CSR index * 4. */
126 #define K230_DDR_PHY_CSR_OFFSET(index) ((index) * 4)
127 #define K230_DDR_PHY_MASTER_CSR(reg) \
128 K230_DDR_PHY_CSR_OFFSET(0x20000 + (reg))
129 #define K230_DDR_PHY_APBONLY_CSR(reg) \
130 K230_DDR_PHY_CSR_OFFSET(0xd0000 + (reg))
131
132 #define K230_DDR_PHY_ATX_IMPEDANCE_RESET UINT32_C(0x03ff)
133
134 REG32(K230_DDR_PHY_MICRO_CONT_MUX_SEL,
135 K230_DDR_PHY_APBONLY_CSR(0x000))
136 FIELD(K230_DDR_PHY_MICRO_CONT_MUX_SEL, MICRO_CONT_MUX_SEL, 0, 1)
137
138 REG32(K230_DDR_PHY_TRAINING_STATUS,
139 K230_DDR_PHY_APBONLY_CSR(0x004))
140 FIELD(K230_DDR_PHY_TRAINING_STATUS, MAILBOX_EMPTY, 0, 1)
141
142 REG32(K230_DDR_PHY_TRAINING_ACK,
143 K230_DDR_PHY_APBONLY_CSR(0x031))
144
145 REG32(K230_DDR_PHY_TRAINING_MESSAGE,
146 K230_DDR_PHY_APBONLY_CSR(0x032))
147
148 REG32(K230_DDR_PHY_TRAINING_TRIGGER,
149 K230_DDR_PHY_APBONLY_CSR(0x099))
150
151 #define K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET UINT32_C(0x0fff)
152
153 REG32(K230_DDR_PHY_DFI_INIT_COMPLETE,
154 K230_DDR_PHY_MASTER_CSR(0x0f9))
155 FIELD(K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 0, 1)
156
157 REG32(K230_DDR_PHY_VREF_IN_GLOBAL,
158 K230_DDR_PHY_MASTER_CSR(0x0b2))
159 #define K230_DDR_PHY_VREF_IN_GLOBAL_RESET UINT32_C(0x0200)
160
161 static void k230_ddr_cfg_update_state(K230DDRCfgState *s)
162 {
163 bool dfi_complete = false;
164 unsigned int operating_mode = K230_DDRC_MODE_INIT;
165
166 if (s->phy) {
167 dfi_complete = FIELD_EX32(s->phy->dfi_init_complete,
168 K230_DDR_PHY_DFI_INIT_COMPLETE,
169 DFI_INIT_COMPLETE);
170 }
171
172 ARRAY_FIELD_DP32(s->regs, K230_DDRC_DFISTAT,
173 DFI_INIT_COMPLETE, dfi_complete);
174 ARRAY_FIELD_DP32(s->regs, K230_DDRC_SWSTAT, SW_DONE_ACK,
175 ARRAY_FIELD_EX32(s->regs, K230_DDRC_SWCTL, SW_DONE));
176
177 if (dfi_complete &&
178 ARRAY_FIELD_EX32(s->regs, K230_DDRC_DFIMISC,
179 DFI_INIT_COMPLETE_EN)) {
180 s->initialized = true;
181 }
182
183 if (s->initialized) {
184 operating_mode = K230_DDRC_MODE_NORMAL;
185 }
186
187 ARRAY_FIELD_DP32(s->regs, K230_DDRC_STAT,
188 OPERATING_MODE, operating_mode);
189 }
190
191 static uint64_t k230_ddr_cfg_read(void *opaque, hwaddr addr, unsigned int size)
192 {
193 K230DDRCfgState *s = opaque;
194 uint64_t value = 0;
195
196 if (addr < K230_DDRC_REG_SIZE) {
197 k230_ddr_cfg_update_state(s);
198 value = s->regs[addr / sizeof(uint32_t)];
199 }
200
201 return value;
202 }
203
204 static void k230_ddr_cfg_write(void *opaque, hwaddr addr, uint64_t value,
205 unsigned int size)
206 {
207 K230DDRCfgState *s = opaque;
208 uint32_t val = value;
209
210 if (addr >= K230_DDRC_REG_SIZE) {
211 return;
212 }
213
214 switch (addr) {
215 case A_K230_DDRC_STAT:
216 case A_K230_DDRC_DFISTAT:
217 case A_K230_DDRC_ZQSTAT:
218 case A_K230_DDRC_SWSTAT:
219 return;
220 case A_K230_DDRC_PWRCTL:
221 s->regs[R_K230_DDRC_PWRCTL] = val & MAKE_64BIT_MASK(0, 9);
222 break;
223 case A_K230_DDRC_ZQCTL2:
224 /* ZQ reset completes immediately and the W1S bit self-clears. */
225 s->regs[R_K230_DDRC_ZQCTL2] = 0;
226 s->regs[R_K230_DDRC_ZQSTAT] = 0;
227 break;
228 case A_K230_DDRC_DFIMISC:
229 s->regs[R_K230_DDRC_DFIMISC] =
230 val & (MAKE_64BIT_MASK(0, 6) | MAKE_64BIT_MASK(8, 5));
231 if (s->phy && s->phy->training_complete &&
232 FIELD_EX32(val, K230_DDRC_DFIMISC, DFI_INIT_START)) {
233 s->phy->dfi_init_complete = FIELD_DP32(
234 s->phy->dfi_init_complete,
235 K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 1);
236 }
237 break;
238 case A_K230_DDRC_SWCTL:
239 s->regs[R_K230_DDRC_SWCTL] =
240 val & R_K230_DDRC_SWCTL_SW_DONE_MASK;
241 break;
242 default:
243 s->regs[addr / sizeof(uint32_t)] = val;
244 break;
245 }
246
247 k230_ddr_cfg_update_state(s);
248 }
249
250 static bool k230_ddr_phy_decode_anib(hwaddr addr, unsigned int *anib)
251 {
252 uint32_t csr = addr / sizeof(uint32_t);
253
254 if ((csr & 0xfff) != 0x043) {
255 return false;
256 }
257
258 *anib = csr >> 12;
259 return *anib < K230_DDR_PHY_ANIB_COUNT;
260 }
261
262 static bool k230_ddr_phy_decode_dbyte(hwaddr addr, uint32_t reg,
263 unsigned int *dbyte,
264 unsigned int *nibble)
265 {
266 uint32_t csr = addr / sizeof(uint32_t);
267 uint32_t block_offset;
268
269 if (csr < 0x10000) {
270 return false;
271 }
272
273 csr -= 0x10000;
274 *dbyte = csr >> 12;
275 if (*dbyte >= K230_DDR_PHY_DBYTE_COUNT) {
276 return false;
277 }
278
279 block_offset = csr & 0xfff;
280 *nibble = block_offset >> 8;
281 return *nibble < K230_DDR_PHY_NIBBLES_PER_DBYTE &&
282 (block_offset & 0xff) == reg;
283 }
284
285 static uint64_t k230_ddr_phy_read(void *opaque, hwaddr addr,
286 unsigned int size)
287 {
288 K230DDRPhyState *s = opaque;
289 unsigned int dbyte;
290 unsigned int nibble;
291 unsigned int anib;
292 uint64_t value = 0;
293
294 switch (addr) {
295 case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL:
296 value = s->micro_cont_mux_sel;
297 break;
298 case A_K230_DDR_PHY_TRAINING_STATUS:
299 value = s->mailbox_message_pending ? 0 :
300 R_K230_DDR_PHY_TRAINING_STATUS_MAILBOX_EMPTY_MASK;
301 break;
302 case A_K230_DDR_PHY_TRAINING_MESSAGE:
303 value = s->training_complete ? 0x07 : 0;
304 break;
305 case A_K230_DDR_PHY_TRAINING_ACK:
306 case A_K230_DDR_PHY_TRAINING_TRIGGER:
307 break;
308 case A_K230_DDR_PHY_DFI_INIT_COMPLETE:
309 value = s->dfi_init_complete;
310 break;
311 case A_K230_DDR_PHY_VREF_IN_GLOBAL:
312 value = s->vref_in_global;
313 break;
314 default:
315 if (k230_ddr_phy_decode_anib(addr, &anib)) {
316 value = s->atx_impedance[anib];
317 } else if (k230_ddr_phy_decode_dbyte(addr, 0x049,
318 &dbyte, &nibble)) {
319 value = s->tx_impedance_ctrl1[dbyte][nibble];
320 } else if (k230_ddr_phy_decode_dbyte(addr, 0x04d,
321 &dbyte, &nibble)) {
322 value = s->tx_odt_drv_stren[dbyte][nibble];
323 } else {
324 qemu_log_mask(LOG_UNIMP,
325 "%s: unimplemented DDR PHY read at offset 0x%"
326 HWADDR_PRIx ", returning 0\n",
327 __func__, addr);
328 }
329 break;
330 }
331
332 return value;
333 }
334
335 static void k230_ddr_phy_write(void *opaque, hwaddr addr, uint64_t value,
336 unsigned int size)
337 {
338 K230DDRPhyState *s = opaque;
339 uint16_t val = value;
340 unsigned int dbyte;
341 unsigned int nibble;
342 unsigned int anib;
343
344 switch (addr) {
345 case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL:
346 s->micro_cont_mux_sel =
347 val & R_K230_DDR_PHY_MICRO_CONT_MUX_SEL_MICRO_CONT_MUX_SEL_MASK;
348 return;
349 case A_K230_DDR_PHY_TRAINING_STATUS:
350 case A_K230_DDR_PHY_TRAINING_MESSAGE:
351 return;
352 case A_K230_DDR_PHY_TRAINING_ACK:
353 if (val == 0) {
354 s->mailbox_message_pending = false;
355 }
356 return;
357 case A_K230_DDR_PHY_TRAINING_TRIGGER:
358 if (val != 0) {
359 s->training_trigger_seen = true;
360 } else if (s->training_trigger_seen) {
361 /* Abstract the loaded firmware run to its final mailbox message. */
362 s->training_trigger_seen = false;
363 s->training_complete = true;
364 s->mailbox_message_pending = true;
365 }
366 return;
367 default:
368 break;
369 }
370
371 if (FIELD_EX32(s->micro_cont_mux_sel,
372 K230_DDR_PHY_MICRO_CONT_MUX_SEL,
373 MICRO_CONT_MUX_SEL)) {
374 return;
375 }
376
377 switch (addr) {
378 case A_K230_DDR_PHY_DFI_INIT_COMPLETE:
379 s->dfi_init_complete =
380 val & R_K230_DDR_PHY_DFI_INIT_COMPLETE_DFI_INIT_COMPLETE_MASK;
381 return;
382 case A_K230_DDR_PHY_VREF_IN_GLOBAL:
383 s->vref_in_global = val & UINT16_C(0x7fff);
384 return;
385 default:
386 break;
387 }
388
389 if (k230_ddr_phy_decode_anib(addr, &anib)) {
390 s->atx_impedance[anib] = val & UINT16_C(0x03ff);
391 return;
392 }
393
394 if (k230_ddr_phy_decode_dbyte(addr, 0x049, &dbyte, &nibble)) {
395 s->tx_impedance_ctrl1[dbyte][nibble] = val & UINT16_C(0x0fff);
396 return;
397 }
398
399 if (k230_ddr_phy_decode_dbyte(addr, 0x04d, &dbyte, &nibble)) {
400 s->tx_odt_drv_stren[dbyte][nibble] = val & UINT16_C(0x0fff);
401 return;
402 }
403
404 qemu_log_mask(LOG_UNIMP,
405 "%s: unimplemented DDR PHY write at offset 0x%"
406 HWADDR_PRIx ", value 0x%" PRIx64 "\n",
407 __func__, addr, value);
408 }
409
410 static const MemoryRegionOps k230_ddr_cfg_ops = {
411 .read = k230_ddr_cfg_read,
412 .write = k230_ddr_cfg_write,
413 .endianness = DEVICE_LITTLE_ENDIAN,
414 .valid = {
415 .min_access_size = 4,
416 .max_access_size = 4,
417 .unaligned = false,
418 },
419 };
420
421 static const MemoryRegionOps k230_ddr_phy_ops = {
422 .read = k230_ddr_phy_read,
423 .write = k230_ddr_phy_write,
424 .endianness = DEVICE_LITTLE_ENDIAN,
425 .valid = {
426 .min_access_size = 4,
427 .max_access_size = 4,
428 .unaligned = false,
429 },
430 };
431
432 static void k230_ddr_cfg_init(Object *obj)
433 {
434 K230DDRCfgState *s = K230_DDR_CFG(obj);
435
436 memory_region_init_io(&s->mmio, obj, &k230_ddr_cfg_ops, s,
437 "k230-ddr-cfg", K230_DDRC_MMIO_SIZE);
438 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
439 }
440
441 static void k230_ddr_phy_init(Object *obj)
442 {
443 K230DDRPhyState *s = K230_DDR_PHY(obj);
444
445 memory_region_init_io(&s->mmio, obj, &k230_ddr_phy_ops, s,
446 "k230-ddr-phy", K230_DDR_PHY_MMIO_SIZE);
447 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
448 }
449
450 static void k230_ddr_cfg_reset_enter(Object *obj, ResetType type)
451 {
452 K230DDRCfgState *s = K230_DDR_CFG(obj);
453
454 s->initialized = false;
455 memcpy(s->regs, k230_ddrc_reset_values, sizeof(s->regs));
456 }
457
458 static void k230_ddr_phy_reset_enter(Object *obj, ResetType type)
459 {
460 K230DDRPhyState *s = K230_DDR_PHY(obj);
461 unsigned int dbyte;
462 unsigned int nibble;
463 unsigned int anib;
464
465 memset(s->tx_odt_drv_stren, 0, sizeof(s->tx_odt_drv_stren));
466
467 for (anib = 0; anib < ARRAY_SIZE(s->atx_impedance); anib++) {
468 s->atx_impedance[anib] = K230_DDR_PHY_ATX_IMPEDANCE_RESET;
469 }
470
471 for (dbyte = 0; dbyte < ARRAY_SIZE(s->tx_impedance_ctrl1); dbyte++) {
472 for (nibble = 0;
473 nibble < ARRAY_SIZE(s->tx_impedance_ctrl1[dbyte]); nibble++) {
474 s->tx_impedance_ctrl1[dbyte][nibble] =
475 K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET;
476 }
477 }
478
479 s->dfi_init_complete = 0;
480 s->vref_in_global = K230_DDR_PHY_VREF_IN_GLOBAL_RESET;
481 s->micro_cont_mux_sel = 0;
482 s->training_trigger_seen = false;
483 s->training_complete = false;
484 s->mailbox_message_pending = false;
485 }
486
487 static const VMStateDescription vmstate_k230_ddr_cfg = {
488 .name = "k230-ddr-cfg",
489 .version_id = 1,
490 .minimum_version_id = 1,
491 .fields = (const VMStateField[]) {
492 VMSTATE_UINT32_ARRAY(regs, K230DDRCfgState, K230_DDRC_REG_COUNT),
493 VMSTATE_BOOL(initialized, K230DDRCfgState),
494 VMSTATE_END_OF_LIST()
495 },
496 };
497
498 static const VMStateDescription vmstate_k230_ddr_phy = {
499 .name = "k230-ddr-phy",
500 .version_id = 1,
501 .minimum_version_id = 1,
502 .fields = (const VMStateField[]) {
503 VMSTATE_UINT16_ARRAY(atx_impedance, K230DDRPhyState,
504 K230_DDR_PHY_ANIB_COUNT),
505 VMSTATE_UINT16_2DARRAY(tx_impedance_ctrl1, K230DDRPhyState,
506 K230_DDR_PHY_DBYTE_COUNT,
507 K230_DDR_PHY_NIBBLES_PER_DBYTE),
508 VMSTATE_UINT16_2DARRAY(tx_odt_drv_stren, K230DDRPhyState,
509 K230_DDR_PHY_DBYTE_COUNT,
510 K230_DDR_PHY_NIBBLES_PER_DBYTE),
511 VMSTATE_UINT16(dfi_init_complete, K230DDRPhyState),
512 VMSTATE_UINT16(vref_in_global, K230DDRPhyState),
513 VMSTATE_UINT16(micro_cont_mux_sel, K230DDRPhyState),
514 VMSTATE_BOOL(training_trigger_seen, K230DDRPhyState),
515 VMSTATE_BOOL(training_complete, K230DDRPhyState),
516 VMSTATE_BOOL(mailbox_message_pending, K230DDRPhyState),
517 VMSTATE_END_OF_LIST()
518 },
519 };
520
521 static void k230_ddr_cfg_class_init(ObjectClass *klass, const void *data)
522 {
523 DeviceClass *dc = DEVICE_CLASS(klass);
524 ResettableClass *rc = RESETTABLE_CLASS(klass);
525
526 rc->phases.enter = k230_ddr_cfg_reset_enter;
527 dc->vmsd = &vmstate_k230_ddr_cfg;
528 }
529
530 static void k230_ddr_phy_class_init(ObjectClass *klass, const void *data)
531 {
532 DeviceClass *dc = DEVICE_CLASS(klass);
533 ResettableClass *rc = RESETTABLE_CLASS(klass);
534
535 rc->phases.enter = k230_ddr_phy_reset_enter;
536 dc->vmsd = &vmstate_k230_ddr_phy;
537 }
538
539 static const TypeInfo k230_ddr_types[] = {
540 {
541 .name = TYPE_K230_DDR_CFG,
542 .parent = TYPE_SYS_BUS_DEVICE,
543 .instance_size = sizeof(K230DDRCfgState),
544 .instance_init = k230_ddr_cfg_init,
545 .class_init = k230_ddr_cfg_class_init,
546 },
547 {
548 .name = TYPE_K230_DDR_PHY,
549 .parent = TYPE_SYS_BUS_DEVICE,
550 .instance_size = sizeof(K230DDRPhyState),
551 .instance_init = k230_ddr_phy_init,
552 .class_init = k230_ddr_phy_class_init,
553 },
554 };
555
556 DEFINE_TYPES(k230_ddr_types)