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1 /*
2 * HP-PARISC Lasi chipset emulation.
3 *
4 * (C) 2019 by Helge Deller <deller@gmx.de>
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 * Documentation available at:
9 * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/units.h"
14 #include "qemu/log.h"
15 #include "qapi/error.h"
16 #include "trace.h"
17 #include "hw/core/irq.h"
18 #include "system/system.h"
19 #include "system/runstate.h"
20 #include "migration/vmstate.h"
21 #include "qom/object.h"
22 #include "hw/misc/lasi.h"
23
24
25 static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
26 unsigned size, bool is_write,
27 MemTxAttrs attrs)
28 {
29 bool ret = false;
30
31 switch (addr) {
32 case LASI_IRR:
33 case LASI_IMR:
34 case LASI_IPR:
35 case LASI_ICR:
36 case LASI_IAR:
37
38 case LASI_LPT:
39 case LASI_AUDIO:
40 case LASI_AUDIO + 4:
41 case LASI_UART:
42 case LASI_LAN:
43 case LASI_LAN + 12: /* LASI LAN MAC */
44 case LASI_RTC:
45 case LASI_FDC:
46 case LASI_SCSI ... LASI_SCSI + 0xFF:
47 case LASI_PCR ... LASI_AMR:
48 ret = true;
49 }
50
51 trace_lasi_chip_mem_valid(addr, ret);
52 return ret;
53 }
54
55 static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
56 uint64_t *data, unsigned size,
57 MemTxAttrs attrs)
58 {
59 LasiState *s = opaque;
60 MemTxResult ret = MEMTX_OK;
61 uint32_t val;
62
63 switch (addr) {
64 case LASI_IRR:
65 /*
66 * The interrupt request register reports the interrupts that are both
67 * pending and unmasked, derived live from IPR and IMR rather than
68 * latched, so masking or deasserting a source removes it immediately.
69 * The parisc core I/O interrupt dispatcher reads IRR; a latched bit
70 * that never cleared would be redelivered forever as a phantom
71 * "unexpected" interrupt.
72 */
73 val = s->ipr & s->imr;
74 break;
75 case LASI_IMR:
76 val = s->imr;
77 break;
78 case LASI_IPR:
79 val = s->ipr;
80 /* Any read to IPR clears the register. */
81 s->ipr = 0;
82 break;
83 case LASI_ICR:
84 val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
85 break;
86 case LASI_IAR:
87 val = s->iar;
88 break;
89
90 case LASI_LPT:
91 case LASI_UART:
92 case LASI_LAN:
93 case LASI_LAN + 12:
94 case LASI_FDC:
95 case LASI_SCSI ... LASI_SCSI + 0xFF:
96 val = 0;
97 break;
98 case LASI_RTC:
99 val = time(NULL);
100 val += s->rtc_ref;
101 break;
102
103 case LASI_PCR:
104 case LASI_VER: /* only version 0 existed. */
105 case LASI_IORESET:
106 val = 0;
107 break;
108 case LASI_ERRLOG:
109 val = s->errlog;
110 break;
111 case LASI_AMR:
112 val = s->amr;
113 break;
114
115 default:
116 /* Controlled by lasi_chip_mem_valid above. */
117 g_assert_not_reached();
118 }
119
120 trace_lasi_chip_read(addr, val);
121
122 *data = val;
123 return ret;
124 }
125
126 static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
127 uint64_t val, unsigned size,
128 MemTxAttrs attrs)
129 {
130 LasiState *s = opaque;
131
132 trace_lasi_chip_write(addr, val);
133
134 switch (addr) {
135 case LASI_IRR:
136 /* read-only. */
137 break;
138 case LASI_IMR:
139 s->imr = val;
140 if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) {
141 qemu_log_mask(LOG_GUEST_ERROR,
142 "LASI: tried to set invalid %lx IMR value.\n",
143 (unsigned long) val);
144 }
145 break;
146 case LASI_IPR:
147 /* Any write to IPR clears the register. */
148 s->ipr = 0;
149 break;
150 case LASI_ICR:
151 s->icr = val;
152 /* if (val & ICR_TOC_BIT) issue_toc(); */
153 break;
154 case LASI_IAR:
155 s->iar = val;
156 break;
157
158 case LASI_LPT:
159 /* XXX: reset parallel port */
160 break;
161 case LASI_AUDIO:
162 case LASI_AUDIO + 4:
163 /* XXX: reset audio port */
164 break;
165 case LASI_UART:
166 /* XXX: reset serial port */
167 break;
168 case LASI_SCSI ... LASI_SCSI + 0xFF:
169 /* XXX: reset SCSI Controller */
170 break;
171 case LASI_LAN:
172 /* XXX: reset LAN card */
173 break;
174 case LASI_FDC:
175 /* XXX: reset Floppy controller */
176 break;
177 case LASI_RTC:
178 s->rtc_ref = val - time(NULL);
179 break;
180
181 case LASI_PCR:
182 if (val == 0x02) { /* immediately power off */
183 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
184 }
185 break;
186 case LASI_ERRLOG:
187 s->errlog = val;
188 break;
189 case LASI_VER:
190 /* read-only. */
191 break;
192 case LASI_IORESET:
193 break; /* XXX: TODO: Reset various devices. */
194 case LASI_AMR:
195 s->amr = val;
196 break;
197
198 default:
199 /* Controlled by lasi_chip_mem_valid above. */
200 g_assert_not_reached();
201 }
202 return MEMTX_OK;
203 }
204
205 static const MemoryRegionOps lasi_chip_ops = {
206 .read_with_attrs = lasi_chip_read_with_attrs,
207 .write_with_attrs = lasi_chip_write_with_attrs,
208 .endianness = DEVICE_BIG_ENDIAN,
209 .valid = {
210 .min_access_size = 1,
211 .max_access_size = 4,
212 .accepts = lasi_chip_mem_valid,
213 },
214 .impl = {
215 .min_access_size = 1,
216 .max_access_size = 4,
217 },
218 };
219
220 static const VMStateDescription vmstate_lasi = {
221 .name = "Lasi",
222 .version_id = 2,
223 .minimum_version_id = 1,
224 .fields = (const VMStateField[]) {
225 VMSTATE_UINT32(irr, LasiState),
226 VMSTATE_UINT32(imr, LasiState),
227 VMSTATE_UINT32(ipr, LasiState),
228 VMSTATE_UINT32(icr, LasiState),
229 VMSTATE_UINT32(iar, LasiState),
230 VMSTATE_UINT32(errlog, LasiState),
231 VMSTATE_UINT32(amr, LasiState),
232 VMSTATE_UINT32_V(rtc_ref, LasiState, 2),
233 VMSTATE_END_OF_LIST()
234 }
235 };
236
237
238 static void lasi_set_irq(void *opaque, int irq, int level)
239 {
240 LasiState *s = opaque;
241 uint32_t bit = 1u << irq;
242
243 if (level) {
244 s->ipr |= bit;
245 if ((bit & s->imr) && (s->icr & ICR_BUS_ERROR_BIT) == 0) {
246 uint32_t iar = s->iar;
247 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
248 }
249 } else {
250 /*
251 * The interrupt sources are level triggered, so a source that drops
252 * its request must clear its pending bit. Otherwise the bit stays set
253 * in IPR (and hence IRR) and is redelivered as a phantom "unexpected"
254 * core I/O interrupt on every later interrupt.
255 */
256 s->ipr &= ~bit;
257 }
258 }
259
260 static void lasi_reset(DeviceState *dev)
261 {
262 LasiState *s = LASI_CHIP(dev);
263
264 s->iar = 0xFFFB0000 + 3; /* CPU_HPA + 3 */
265
266 /* Real time clock (RTC), it's only one 32-bit counter @9000 */
267 s->rtc_ref = 0;
268 }
269
270 static void lasi_init(Object *obj)
271 {
272 LasiState *s = LASI_CHIP(obj);
273 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
274
275 memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
276 s, "lasi", 0x100000);
277
278 sysbus_init_mmio(sbd, &s->this_mem);
279
280 qdev_init_gpio_in(DEVICE(obj), lasi_set_irq, LASI_IRQS);
281 }
282
283 static void lasi_class_init(ObjectClass *klass, const void *data)
284 {
285 DeviceClass *dc = DEVICE_CLASS(klass);
286
287 device_class_set_legacy_reset(dc, lasi_reset);
288 dc->vmsd = &vmstate_lasi;
289 }
290
291 static const TypeInfo lasi_pcihost_info = {
292 .name = TYPE_LASI_CHIP,
293 .parent = TYPE_SYS_BUS_DEVICE,
294 .instance_init = lasi_init,
295 .instance_size = sizeof(LasiState),
296 .class_init = lasi_class_init,
297 };
298
299 static void lasi_register_types(void)
300 {
301 type_register_static(&lasi_pcihost_info);
302 }
303
304 type_init(lasi_register_types)