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1 /*
2 * Microchip PolarFire SoC IOSCB module emulation
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 or
12 * (at your option) version 3 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/bitops.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "hw/core/irq.h"
28 #include "hw/core/sysbus.h"
29 #include "hw/misc/mchp_pfsoc_ioscb.h"
30
31 /*
32 * The whole IOSCB module registers map into the system address at 0x3000_0000,
33 * named as "System Port 0 (AXI-D0)".
34 */
35 #define IOSCB_WHOLE_REG_SIZE 0x10000000
36 #define IOSCB_SUBMOD_REG_SIZE 0x1000
37 #define IOSCB_CCC_REG_SIZE 0x2000000
38 #define IOSCB_CTRL_REG_SIZE 0x800
39 #define IOSCB_QSPIXIP_REG_SIZE 0x200
40
41
42 /*
43 * There are many sub-modules in the IOSCB module.
44 * See Microchip PolarFire SoC documentation (Register_Map.zip),
45 * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
46 *
47 * The following are sub-modules offsets that are of concern.
48 */
49 #define IOSCB_LANE01_BASE 0x06500000
50 #define IOSCB_LANE23_BASE 0x06510000
51 #define IOSCB_CTRL_BASE 0x07020000
52 #define IOSCB_QSPIXIP_BASE 0x07020100
53 #define IOSCB_MAILBOX_BASE 0x07020800
54 #define IOSCB_CFG_BASE 0x07080000
55 #define IOSCB_CCC_BASE 0x08000000
56 #define IOSCB_PLL_NW0_BASE 0x08100000
57 #define IOSCB_PLL_NW1_BASE 0x08200000
58 #define IOSCB_PLL_MSS_BASE 0x0E001000
59 #define IOSCB_CFM_MSS_BASE 0x0E002000
60 #define IOSCB_PLL_DDR_BASE 0x0E010000
61 #define IOSCB_BC_DDR_BASE 0x0E020000
62 #define IOSCB_IO_CALIB_DDR_BASE 0x0E040000
63 #define IOSCB_PLL_SGMII_BASE 0x0E080000
64 #define IOSCB_DLL_SGMII_BASE 0x0E100000
65 #define IOSCB_CFM_SGMII_BASE 0x0E200000
66 #define IOSCB_BC_SGMII_BASE 0x0E400000
67 #define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000
68
69 static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
70 unsigned size)
71 {
72 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
73 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
74 __func__, size, offset);
75
76 return 0;
77 }
78
79 static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
80 uint64_t value, unsigned size)
81 {
82 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
83 "(size %d, value 0x%" PRIx64
84 ", offset 0x%" HWADDR_PRIx ")\n",
85 __func__, size, value, offset);
86 }
87
88 static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
89 .read = mchp_pfsoc_dummy_read,
90 .write = mchp_pfsoc_dummy_write,
91 .endianness = DEVICE_LITTLE_ENDIAN,
92 };
93
94 /* All PLL modules in IOSCB have the same register layout */
95
96 #define PLL_CTRL 0x04
97 #define PLL_REF_FB 0x08
98 #define PLL_DIV_0_1 0x10
99 #define PLL_DIV_2_3 0x14
100 #define PLL_CTRL2 0x18
101 #define PLL_CAL 0x1c
102 #define PLL_PHADJ 0x20
103 #define SSCG_REG_0 0x24
104 #define SSCG_REG_1 0x28
105 #define SSCG_REG_2 0x2c
106 #define SSCG_REG_3 0x30
107
108 static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
109 unsigned size)
110 {
111 uint32_t val = 0;
112
113 switch (offset) {
114 case PLL_CTRL:
115 /* PLL is locked */
116 val = BIT(25);
117 break;
118 case PLL_DIV_0_1:
119 case PLL_DIV_2_3:
120 val = 0x01000100; /* return valid post divider values */
121 break;
122 case PLL_CTRL2:
123 val = 0x00001110;
124 break;
125 case PLL_REF_FB:
126 val = 0x00000100; /* RFDIV := 1 */
127 break;
128 case SSCG_REG_2:
129 val = 0x00000001; /* INTIN := 1 */
130 break;
131 case PLL_PHADJ:
132 val = 0x00000401;
133 break;
134 default:
135 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
136 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
137 __func__, size, offset);
138 break;
139 }
140
141 return val;
142 }
143
144 static void mchp_pfsoc_pll_write(void *opaque, hwaddr offset,
145 uint64_t value, unsigned size)
146 {
147 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
148 "(size %d, value 0x%" PRIx64
149 ", offset 0x%" HWADDR_PRIx ")\n",
150 __func__, size, value, offset);
151 }
152
153 static const MemoryRegionOps mchp_pfsoc_pll_ops = {
154 .read = mchp_pfsoc_pll_read,
155 .write = mchp_pfsoc_pll_write,
156 .endianness = DEVICE_LITTLE_ENDIAN,
157 };
158
159 /* IO_CALIB_DDR submodule */
160
161 #define IO_CALIB_DDR_IOC_REG1 0x08
162
163 static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
164 unsigned size)
165 {
166 uint32_t val = 0;
167
168 switch (offset) {
169 case IO_CALIB_DDR_IOC_REG1:
170 /* calibration completed */
171 val = BIT(2);
172 break;
173 default:
174 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
175 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
176 __func__, size, offset);
177 break;
178 }
179
180 return val;
181 }
182
183 static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
184 .read = mchp_pfsoc_io_calib_ddr_read,
185 .write = mchp_pfsoc_dummy_write,
186 .endianness = DEVICE_LITTLE_ENDIAN,
187 };
188
189 #define SERVICES_CR 0x50
190 #define SERVICES_SR 0x54
191 #define SERVICES_STATUS_SHIFT 16
192
193 static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
194 unsigned size)
195 {
196 uint32_t val = 0;
197
198 switch (offset) {
199 case SERVICES_SR:
200 /*
201 * Although some services have no error codes, most do. All services
202 * that do implement errors, begin their error codes at 1. Treat all
203 * service requests as failures & return 1.
204 * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
205 * user guide for more information on service error codes.
206 */
207 val = 1u << SERVICES_STATUS_SHIFT;
208 break;
209 default:
210 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
211 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
212 __func__, size, offset);
213 }
214
215 return val;
216 }
217
218 static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
219 uint64_t value, unsigned size)
220 {
221 MchpPfSoCIoscbState *s = opaque;
222
223 switch (offset) {
224 case SERVICES_CR:
225 qemu_irq_raise(s->irq);
226 break;
227 default:
228 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
229 "(size %d, value 0x%" PRIx64
230 ", offset 0x%" HWADDR_PRIx ")\n",
231 __func__, size, value, offset);
232 }
233 }
234
235 static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
236 .read = mchp_pfsoc_ctrl_read,
237 .write = mchp_pfsoc_ctrl_write,
238 .endianness = DEVICE_LITTLE_ENDIAN,
239 };
240
241 static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
242 {
243 MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
244 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
245
246 memory_region_init(&s->container, OBJECT(s),
247 "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
248 sysbus_init_mmio(sbd, &s->container);
249
250 /* add subregions for all sub-modules in IOSCB */
251
252 memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
253 "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
254 memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
255
256 memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
257 "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
258 memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
259
260 memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
261 "mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
262 memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
263
264 memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
265 "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
266 memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
267
268 memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
269 "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
270 memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
271
272 memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
273 "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
274 memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
275
276 memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
277 "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE);
278 memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc);
279
280 memory_region_init_io(&s->pll_nw_0, OBJECT(s), &mchp_pfsoc_pll_ops, s,
281 "mchp.pfsoc.ioscb.pll_nw_0", IOSCB_SUBMOD_REG_SIZE);
282 memory_region_add_subregion(&s->container, IOSCB_PLL_NW0_BASE, &s->pll_nw_0);
283
284 memory_region_init_io(&s->pll_nw_1, OBJECT(s), &mchp_pfsoc_pll_ops, s,
285 "mchp.pfsoc.ioscb.pll_nw_1", IOSCB_SUBMOD_REG_SIZE);
286 memory_region_add_subregion(&s->container, IOSCB_PLL_NW1_BASE, &s->pll_nw_1);
287
288 memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
289 "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
290 memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
291
292 memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
293 "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
294 memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
295
296 memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
297 "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
298 memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
299
300 memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
301 "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
302 memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
303
304 memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
305 &mchp_pfsoc_io_calib_ddr_ops, s,
306 "mchp.pfsoc.ioscb.io_calib_ddr",
307 IOSCB_SUBMOD_REG_SIZE);
308 memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
309 &s->io_calib_ddr);
310
311 memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
312 "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
313 memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
314 &s->pll_sgmii);
315
316 memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
317 "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
318 memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
319 &s->dll_sgmii);
320
321 memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
322 "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
323 memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
324 &s->cfm_sgmii);
325
326 memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
327 "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
328 memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
329 &s->bc_sgmii);
330
331 memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
332 s, "mchp.pfsoc.ioscb.io_calib_sgmii",
333 IOSCB_SUBMOD_REG_SIZE);
334 memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
335 &s->io_calib_sgmii);
336
337 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
338 }
339
340 static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, const void *data)
341 {
342 DeviceClass *dc = DEVICE_CLASS(klass);
343
344 dc->desc = "Microchip PolarFire SoC IOSCB modules";
345 dc->realize = mchp_pfsoc_ioscb_realize;
346 }
347
348 static const TypeInfo mchp_pfsoc_ioscb_info = {
349 .name = TYPE_MCHP_PFSOC_IOSCB,
350 .parent = TYPE_SYS_BUS_DEVICE,
351 .instance_size = sizeof(MchpPfSoCIoscbState),
352 .class_init = mchp_pfsoc_ioscb_class_init,
353 };
354
355 static void mchp_pfsoc_ioscb_register_types(void)
356 {
357 type_register_static(&mchp_pfsoc_ioscb_info);
358 }
359
360 type_init(mchp_pfsoc_ioscb_register_types)