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1 /*
2 * Microchip PolarFire SoC SYSREG module emulation
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 or
12 * (at your option) version 3 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/bitops.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "hw/core/irq.h"
28 #include "hw/core/sysbus.h"
29 #include "hw/misc/mchp_pfsoc_sysreg.h"
30 #include "system/runstate.h"
31
32 #define CLOCK_CONFIG_CR 0x8
33 #define RTC_CLOCK_CR 0xc
34 #define MSS_RESET_CR 0x18
35 #define ENVM_CR 0xb8
36 #define MESSAGE_INT 0x118c
37
38 static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
39 unsigned size)
40 {
41 uint32_t val = 0;
42
43 switch (offset) {
44 case CLOCK_CONFIG_CR:
45 /* Icicle kit reference design cpu/axi/ahb divider setting */
46 val = 0x24;
47 break;
48 case RTC_CLOCK_CR:
49 /*
50 * Bit 16 enables the RTC clock, 0x7d is the required divider
51 * setting for a 125 MHz reference.
52 */
53 val = BIT(16) | 0x7d;
54 break;
55 case ENVM_CR:
56 /* Indicate the eNVM is running at the configured divider rate */
57 val = BIT(6);
58 break;
59 default:
60 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
61 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
62 __func__, size, offset);
63 break;
64 }
65
66 return val;
67 }
68
69 static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
70 uint64_t value, unsigned size)
71 {
72 MchpPfSoCSysregState *s = opaque;
73 switch (offset) {
74 case MSS_RESET_CR:
75 if (value == 0xdead) {
76 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
77 }
78 break;
79 case MESSAGE_INT:
80 qemu_irq_lower(s->irq);
81 break;
82 default:
83 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
84 "(size %d, value 0x%" PRIx64
85 ", offset 0x%" HWADDR_PRIx ")\n",
86 __func__, size, value, offset);
87 }
88 }
89
90 static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
91 .read = mchp_pfsoc_sysreg_read,
92 .write = mchp_pfsoc_sysreg_write,
93 .endianness = DEVICE_LITTLE_ENDIAN,
94 };
95
96 static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
97 {
98 MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
99
100 memory_region_init_io(&s->sysreg, OBJECT(dev),
101 &mchp_pfsoc_sysreg_ops, s,
102 "mchp.pfsoc.sysreg",
103 MCHP_PFSOC_SYSREG_REG_SIZE);
104 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
105 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
106 }
107
108 static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, const void *data)
109 {
110 DeviceClass *dc = DEVICE_CLASS(klass);
111
112 dc->desc = "Microchip PolarFire SoC SYSREG module";
113 dc->realize = mchp_pfsoc_sysreg_realize;
114 }
115
116 static const TypeInfo mchp_pfsoc_sysreg_info = {
117 .name = TYPE_MCHP_PFSOC_SYSREG,
118 .parent = TYPE_SYS_BUS_DEVICE,
119 .instance_size = sizeof(MchpPfSoCSysregState),
120 .class_init = mchp_pfsoc_sysreg_class_init,
121 };
122
123 static void mchp_pfsoc_sysreg_register_types(void)
124 {
125 type_register_static(&mchp_pfsoc_sysreg_info);
126 }
127
128 type_init(mchp_pfsoc_sysreg_register_types)