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1 /*
2 * ARM MPS2 AN505 FPGAIO emulation
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /* This is a model of the "FPGA system control and I/O" block found
13 * in the AN505 FPGA image for the MPS2 devboard.
14 * It is documented in AN505:
15 * https://developer.arm.com/documentation/dai0505/latest/
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/log.h"
20 #include "qemu/module.h"
21 #include "qapi/error.h"
22 #include "trace.h"
23 #include "hw/core/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "hw/core/registerfields.h"
26 #include "hw/misc/mps2-fpgaio.h"
27 #include "hw/misc/led.h"
28 #include "hw/core/qdev-properties.h"
29 #include "qemu/timer.h"
30
31 REG32(LED0, 0)
32 REG32(DBGCTRL, 4)
33 REG32(BUTTON, 8)
34 REG32(GPIOALT2, 0xc)
35 REG32(CLK1HZ, 0x10)
36 REG32(CLK100HZ, 0x14)
37 REG32(COUNTER, 0x18)
38 REG32(PRESCALE, 0x1c)
39 REG32(PSCNTR, 0x20)
40 REG32(SWITCH, 0x28)
41 REG32(MISC, 0x4c)
42
43 static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq)
44 {
45 return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND);
46 }
47
48 static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq)
49 {
50 return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq);
51 }
52
53 static void resync_counter(MPS2FPGAIO *s)
54 {
55 /*
56 * Update s->counter and s->pscntr to their true current values
57 * by calculating how many times PSCNTR has ticked since the
58 * last time we did a resync.
59 */
60 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
61 int64_t elapsed = now - s->pscntr_sync_ticks;
62
63 /*
64 * Round elapsed down to a whole number of PSCNTR ticks, so we don't
65 * lose time if we do multiple resyncs in a single tick.
66 */
67 uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND);
68
69 /*
70 * Work out what PSCNTR and COUNTER have moved to. We assume that
71 * PSCNTR reloads from PRESCALE one tick-period after it hits zero,
72 * and that COUNTER increments at the same moment.
73 */
74 if (ticks == 0) {
75 /* We haven't ticked since the last time we were asked */
76 return;
77 } else if (ticks < s->pscntr) {
78 /* We haven't yet reached zero, just reduce the PSCNTR */
79 s->pscntr -= ticks;
80 } else {
81 if (s->prescale == 0) {
82 /*
83 * If the reload value is zero then the PSCNTR will stick
84 * at zero once it reaches it, and so we will increment
85 * COUNTER every tick after that.
86 */
87 s->counter += ticks - s->pscntr;
88 s->pscntr = 0;
89 } else {
90 /*
91 * This is the complicated bit. This ASCII art diagram gives an
92 * example with PRESCALE==5 PSCNTR==7:
93 *
94 * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
95 * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5
96 * cinc 1 2
97 * y 0 1 2 3 4 5 6 7 8 9 10 11 12
98 * x 0 1 2 3 4 5 0 1 2 3 4 5 0
99 *
100 * where x = y % (s->prescale + 1)
101 * and so PSCNTR = s->prescale - x
102 * and COUNTER is incremented by y / (s->prescale + 1)
103 *
104 * The case where PSCNTR < PRESCALE works out the same,
105 * though we must be careful to calculate y as 64-bit unsigned
106 * for all parts of the expression.
107 * y < 0 is not possible because that implies ticks < s->pscntr.
108 */
109 uint64_t y = ticks - s->pscntr + s->prescale;
110 s->pscntr = s->prescale - (y % (s->prescale + 1));
111 s->counter += y / (s->prescale + 1);
112 }
113 }
114
115 /*
116 * Only advance the sync time to the timestamp of the last PSCNTR tick,
117 * not all the way to 'now', so we don't lose time if we do multiple
118 * resyncs in a single tick.
119 */
120 s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND,
121 s->prescale_clk);
122 }
123
124 static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size)
125 {
126 MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
127 uint64_t r;
128 int64_t now;
129
130 switch (offset) {
131 case A_LED0:
132 r = s->led0;
133 break;
134 case A_DBGCTRL:
135 if (!s->has_dbgctrl) {
136 goto bad_offset;
137 }
138 r = s->dbgctrl;
139 break;
140 case A_BUTTON:
141 /* User-pressable board buttons. We don't model that, so just return
142 * zeroes.
143 */
144 r = 0;
145 break;
146 case A_GPIOALT2:
147 r = s->gpioalt2;
148 break;
149 case A_PRESCALE:
150 r = s->prescale;
151 break;
152 case A_MISC:
153 r = s->misc;
154 break;
155 case A_CLK1HZ:
156 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
157 r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1);
158 break;
159 case A_CLK100HZ:
160 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
161 r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100);
162 break;
163 case A_COUNTER:
164 resync_counter(s);
165 r = s->counter;
166 break;
167 case A_PSCNTR:
168 resync_counter(s);
169 r = s->pscntr;
170 break;
171 case A_SWITCH:
172 if (!s->has_switches) {
173 goto bad_offset;
174 }
175 /* User-togglable board switches. We don't model that, so report 0. */
176 r = 0;
177 break;
178 default:
179 bad_offset:
180 qemu_log_mask(LOG_GUEST_ERROR,
181 "MPS2 FPGAIO read: bad offset %x\n", (int) offset);
182 r = 0;
183 break;
184 }
185
186 trace_mps2_fpgaio_read(offset, r, size);
187 return r;
188 }
189
190 static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value,
191 unsigned size)
192 {
193 MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
194 int64_t now;
195
196 trace_mps2_fpgaio_write(offset, value, size);
197
198 switch (offset) {
199 case A_LED0:
200 if (s->num_leds != 0) {
201 uint32_t i;
202
203 s->led0 = value & MAKE_64BIT_MASK(0, s->num_leds);
204 for (i = 0; i < s->num_leds; i++) {
205 led_set_state(s->led[i], extract64(value, i, 1));
206 }
207 }
208 break;
209 case A_DBGCTRL:
210 if (!s->has_dbgctrl) {
211 goto bad_offset;
212 }
213 qemu_log_mask(LOG_UNIMP,
214 "MPS2 FPGAIO: DBGCTRL unimplemented\n");
215 s->dbgctrl = value;
216 break;
217 case A_GPIOALT2:
218 if (!s->has_gpioalt2) {
219 goto bad_offset;
220 }
221 qemu_log_mask(LOG_UNIMP,
222 "MPS2 FPGAIO: GPIOALT2 unimplemented\n");
223 s->gpioalt2 = value;
224 break;
225 case A_PRESCALE:
226 resync_counter(s);
227 s->prescale = value;
228 break;
229 case A_MISC:
230 /* These are control bits for some of the other devices on the
231 * board (SPI, CLCD, etc). We don't implement that yet, so just
232 * make the bits read as written.
233 */
234 qemu_log_mask(LOG_UNIMP,
235 "MPS2 FPGAIO: MISC control bits unimplemented\n");
236 s->misc = value;
237 break;
238 case A_CLK1HZ:
239 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
240 s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1);
241 break;
242 case A_CLK100HZ:
243 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
244 s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100);
245 break;
246 case A_COUNTER:
247 resync_counter(s);
248 s->counter = value;
249 break;
250 case A_PSCNTR:
251 resync_counter(s);
252 s->pscntr = value;
253 break;
254 default:
255 bad_offset:
256 qemu_log_mask(LOG_GUEST_ERROR,
257 "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset);
258 break;
259 }
260 }
261
262 static const MemoryRegionOps mps2_fpgaio_ops = {
263 .read = mps2_fpgaio_read,
264 .write = mps2_fpgaio_write,
265 .endianness = DEVICE_LITTLE_ENDIAN,
266 };
267
268 static void mps2_fpgaio_reset(DeviceState *dev)
269 {
270 MPS2FPGAIO *s = MPS2_FPGAIO(dev);
271 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
272
273 trace_mps2_fpgaio_reset();
274 s->led0 = 0;
275 s->prescale = 0;
276 s->misc = 0;
277 s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1);
278 s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100);
279 s->counter = 0;
280 s->pscntr = 0;
281 s->pscntr_sync_ticks = now;
282
283 for (size_t i = 0; i < s->num_leds; i++) {
284 device_cold_reset(DEVICE(s->led[i]));
285 }
286 }
287
288 static void mps2_fpgaio_init(Object *obj)
289 {
290 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
291 MPS2FPGAIO *s = MPS2_FPGAIO(obj);
292
293 memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s,
294 "mps2-fpgaio", 0x1000);
295 sysbus_init_mmio(sbd, &s->iomem);
296 }
297
298 static void mps2_fpgaio_realize(DeviceState *dev, Error **errp)
299 {
300 MPS2FPGAIO *s = MPS2_FPGAIO(dev);
301 uint32_t i;
302
303 if (s->num_leds > MPS2FPGAIO_MAX_LEDS) {
304 error_setg(errp, "num-leds cannot be greater than %d",
305 MPS2FPGAIO_MAX_LEDS);
306 return;
307 }
308
309 for (i = 0; i < s->num_leds; i++) {
310 g_autofree char *ledname = g_strdup_printf("USERLED%d", i);
311 s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,
312 LED_COLOR_GREEN, ledname);
313 }
314 }
315
316 static bool needed_gpioalt2(void *opaque)
317 {
318 MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
319
320 return s->has_gpioalt2;
321 }
322
323 static const VMStateDescription mps2_fpgaio_gpioalt2_vmstate = {
324 .name = "mps2-fpgaio/gpioalt2",
325 .version_id = 1,
326 .minimum_version_id = 1,
327 .needed = needed_gpioalt2,
328 .fields = (const VMStateField[]) {
329 VMSTATE_UINT32(gpioalt2, MPS2FPGAIO),
330 VMSTATE_END_OF_LIST()
331 }
332 };
333
334 static const VMStateDescription mps2_fpgaio_vmstate = {
335 .name = "mps2-fpgaio",
336 .version_id = 3,
337 .minimum_version_id = 3,
338 .fields = (const VMStateField[]) {
339 VMSTATE_UINT32(led0, MPS2FPGAIO),
340 VMSTATE_UINT32(prescale, MPS2FPGAIO),
341 VMSTATE_UINT32(misc, MPS2FPGAIO),
342 VMSTATE_UINT32(dbgctrl, MPS2FPGAIO),
343 VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO),
344 VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO),
345 VMSTATE_UINT32(counter, MPS2FPGAIO),
346 VMSTATE_UINT32(pscntr, MPS2FPGAIO),
347 VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO),
348 VMSTATE_END_OF_LIST()
349 },
350 .subsections = (const VMStateDescription * const []) {
351 &mps2_fpgaio_gpioalt2_vmstate,
352 NULL
353 }
354 };
355
356 static const Property mps2_fpgaio_properties[] = {
357 /* Frequency of the prescale counter */
358 DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000),
359 /* Number of LEDs controlled by LED0 register */
360 DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2),
361 DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false),
362 DEFINE_PROP_BOOL("has-dbgctrl", MPS2FPGAIO, has_dbgctrl, false),
363 DEFINE_PROP_BOOL("has-gpioalt2", MPS2FPGAIO, has_gpioalt2, false),
364 };
365
366 static void mps2_fpgaio_class_init(ObjectClass *klass, const void *data)
367 {
368 DeviceClass *dc = DEVICE_CLASS(klass);
369
370 dc->vmsd = &mps2_fpgaio_vmstate;
371 dc->realize = mps2_fpgaio_realize;
372 device_class_set_legacy_reset(dc, mps2_fpgaio_reset);
373 device_class_set_props(dc, mps2_fpgaio_properties);
374 }
375
376 static const TypeInfo mps2_fpgaio_info = {
377 .name = TYPE_MPS2_FPGAIO,
378 .parent = TYPE_SYS_BUS_DEVICE,
379 .instance_size = sizeof(MPS2FPGAIO),
380 .instance_init = mps2_fpgaio_init,
381 .class_init = mps2_fpgaio_class_init,
382 };
383
384 static void mps2_fpgaio_register_types(void)
385 {
386 type_register_static(&mps2_fpgaio_info);
387 }
388
389 type_init(mps2_fpgaio_register_types);