| 1 | /* |
| 2 | * Cluster Power Controller emulation |
| 3 | * |
| 4 | * Copyright (c) 2016 Imagination Technologies |
| 5 | * |
| 6 | * Copyright (c) 2025 MIPS |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | * |
| 10 | * Reference: MIPS P8700 documentation |
| 11 | * (https://mips.com/products/hardware/p8700/) |
| 12 | */ |
| 13 | |
| 14 | #include "qemu/osdep.h" |
| 15 | #include "qapi/error.h" |
| 16 | #include "target/riscv/cpu.h" |
| 17 | #include "qemu/log.h" |
| 18 | #include "qemu/module.h" |
| 19 | #include "qemu/timer.h" |
| 20 | #include "qemu/bitops.h" |
| 21 | #include "hw/core/cpu.h" |
| 22 | #include "hw/core/sysbus.h" |
| 23 | #include "migration/vmstate.h" |
| 24 | |
| 25 | #include "hw/misc/riscv_cpc.h" |
| 26 | #include "hw/core/qdev-properties.h" |
| 27 | #include "hw/intc/riscv_aclint.h" |
| 28 | #include "hw/core/resettable.h" |
| 29 | |
| 30 | static inline uint64_t cpc_vp_run_mask(RISCVCPCState *cpc) |
| 31 | { |
| 32 | return MAKE_64BIT_MASK(0, cpc->num_vp); |
| 33 | } |
| 34 | |
| 35 | static void riscv_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) |
| 36 | { |
| 37 | RISCVCPCState *cpc = (RISCVCPCState *) data.host_ptr; |
| 38 | int i; |
| 39 | |
| 40 | cpu_reset(cs); |
| 41 | cs->halted = 0; |
| 42 | |
| 43 | /* Find this CPU's index in the CPC's CPU array */ |
| 44 | for (i = 0; i < cpc->num_vp; i++) { |
| 45 | if (cpc->cpus[i] == cs) { |
| 46 | cpc->vps_running_mask |= BIT_ULL(i); |
| 47 | break; |
| 48 | } |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | static void cpc_run_vp(RISCVCPCState *cpc, uint64_t vps_run_mask) |
| 53 | { |
| 54 | int vp; |
| 55 | |
| 56 | for (vp = 0; vp < cpc->num_vp; vp++) { |
| 57 | CPUState *cs = cpc->cpus[vp]; |
| 58 | |
| 59 | if (!extract64(vps_run_mask, vp, 1)) { |
| 60 | continue; |
| 61 | } |
| 62 | |
| 63 | if (extract64(cpc->vps_running_mask, vp, 1)) { |
| 64 | continue; |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | * To avoid racing with a CPU we are just kicking off. |
| 69 | * We do the final bit of preparation for the work in |
| 70 | * the target CPUs context. |
| 71 | */ |
| 72 | async_safe_run_on_cpu(cs, riscv_cpu_reset_async_work, |
| 73 | RUN_ON_CPU_HOST_PTR(cpc)); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | static void cpc_stop_vp(RISCVCPCState *cpc, uint64_t vps_stop_mask) |
| 78 | { |
| 79 | int vp; |
| 80 | |
| 81 | for (vp = 0; vp < cpc->num_vp; vp++) { |
| 82 | CPUState *cs = cpc->cpus[vp]; |
| 83 | |
| 84 | if (!extract64(vps_stop_mask, vp, 1)) { |
| 85 | continue; |
| 86 | } |
| 87 | |
| 88 | if (!extract64(cpc->vps_running_mask, vp, 1)) { |
| 89 | continue; |
| 90 | } |
| 91 | |
| 92 | cpu_interrupt(cs, CPU_INTERRUPT_HALT); |
| 93 | cpc->vps_running_mask &= ~BIT_ULL(vp); |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | static void cpc_write(void *opaque, hwaddr offset, uint64_t data, |
| 98 | unsigned size) |
| 99 | { |
| 100 | RISCVCPCState *s = opaque; |
| 101 | int cpu_index, c; |
| 102 | |
| 103 | for (c = 0; c < s->num_core; c++) { |
| 104 | cpu_index = c * s->num_hart + |
| 105 | s->cluster_id * s->num_core * s->num_hart; |
| 106 | if (offset == |
| 107 | CPC_CL_BASE_OFS + CPC_VP_RUN_OFS + c * CPC_CORE_REG_STRIDE) { |
| 108 | cpc_run_vp(s, (data << cpu_index) & cpc_vp_run_mask(s)); |
| 109 | return; |
| 110 | } |
| 111 | if (offset == |
| 112 | CPC_CL_BASE_OFS + CPC_VP_STOP_OFS + c * CPC_CORE_REG_STRIDE) { |
| 113 | cpc_stop_vp(s, (data << cpu_index) & cpc_vp_run_mask(s)); |
| 114 | return; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | switch (offset) { |
| 119 | default: |
| 120 | qemu_log_mask(LOG_UNIMP, |
| 121 | "%s: Bad offset 0x%x\n", __func__, (int)offset); |
| 122 | break; |
| 123 | } |
| 124 | |
| 125 | return; |
| 126 | } |
| 127 | |
| 128 | static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size) |
| 129 | { |
| 130 | RISCVCPCState *s = opaque; |
| 131 | int c; |
| 132 | |
| 133 | for (c = 0; c < s->num_core; c++) { |
| 134 | if (offset == |
| 135 | CPC_CL_BASE_OFS + CPC_STAT_CONF_OFS + c * CPC_CORE_REG_STRIDE) { |
| 136 | /* Return the state as U6. */ |
| 137 | return CPC_Cx_STAT_CONF_SEQ_STATE_U6; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | switch (offset) { |
| 142 | case CPC_CM_STAT_CONF_OFS: |
| 143 | return CPC_Cx_STAT_CONF_SEQ_STATE_U5; |
| 144 | case CPC_MTIME_REG_OFS: |
| 145 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
| 146 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, |
| 147 | NANOSECONDS_PER_SECOND); |
| 148 | return 0; |
| 149 | default: |
| 150 | qemu_log_mask(LOG_UNIMP, |
| 151 | "%s: Bad offset 0x%x\n", __func__, (int)offset); |
| 152 | return 0; |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | static const MemoryRegionOps cpc_ops = { |
| 157 | .read = cpc_read, |
| 158 | .write = cpc_write, |
| 159 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 160 | .impl = { |
| 161 | .min_access_size = 8, |
| 162 | }, |
| 163 | }; |
| 164 | |
| 165 | static void riscv_cpc_init(Object *obj) |
| 166 | { |
| 167 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 168 | RISCVCPCState *s = RISCV_CPC(obj); |
| 169 | int i; |
| 170 | |
| 171 | memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "xmips-cpc", |
| 172 | CPC_ADDRSPACE_SZ); |
| 173 | sysbus_init_mmio(sbd, &s->mr); |
| 174 | |
| 175 | /* Allocate CPU array */ |
| 176 | s->cpus = g_new0(CPUState *, CPC_MAX_VPS); |
| 177 | |
| 178 | /* Create link properties for each possible CPU slot */ |
| 179 | for (i = 0; i < CPC_MAX_VPS; i++) { |
| 180 | char *propname = g_strdup_printf("cpu[%d]", i); |
| 181 | object_property_add_link(obj, propname, TYPE_CPU, |
| 182 | (Object **)&s->cpus[i], |
| 183 | qdev_prop_allow_set_link_before_realize, |
| 184 | OBJ_PROP_LINK_STRONG); |
| 185 | g_free(propname); |
| 186 | } |
| 187 | } |
| 188 | |
| 189 | static void riscv_cpc_finalize(Object *obj) |
| 190 | { |
| 191 | RISCVCPCState *s = RISCV_CPC(obj); |
| 192 | |
| 193 | g_free(s->cpus); |
| 194 | } |
| 195 | |
| 196 | static void riscv_cpc_realize(DeviceState *dev, Error **errp) |
| 197 | { |
| 198 | RISCVCPCState *s = RISCV_CPC(dev); |
| 199 | int i; |
| 200 | |
| 201 | if (s->vps_start_running_mask & ~cpc_vp_run_mask(s)) { |
| 202 | error_setg(errp, |
| 203 | "incorrect vps-start-running-mask 0x%" PRIx64 |
| 204 | " for num_vp = %d", |
| 205 | s->vps_start_running_mask, s->num_vp); |
| 206 | return; |
| 207 | } |
| 208 | |
| 209 | /* Verify that required CPUs have been linked */ |
| 210 | for (i = 0; i < s->num_vp; i++) { |
| 211 | if (!s->cpus[i]) { |
| 212 | error_setg(errp, "CPU %d has not been linked", i); |
| 213 | return; |
| 214 | } |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | static void riscv_cpc_reset_hold(Object *obj, ResetType type) |
| 219 | { |
| 220 | RISCVCPCState *s = RISCV_CPC(obj); |
| 221 | |
| 222 | /* Reflect the fact that all VPs are halted on reset */ |
| 223 | s->vps_running_mask = 0; |
| 224 | |
| 225 | /* Put selected VPs into run state */ |
| 226 | cpc_run_vp(s, s->vps_start_running_mask); |
| 227 | } |
| 228 | |
| 229 | static const VMStateDescription vmstate_riscv_cpc = { |
| 230 | .name = "xmips-cpc", |
| 231 | .version_id = 0, |
| 232 | .minimum_version_id = 0, |
| 233 | .fields = (VMStateField[]) { |
| 234 | VMSTATE_UINT64(vps_running_mask, RISCVCPCState), |
| 235 | VMSTATE_END_OF_LIST() |
| 236 | }, |
| 237 | }; |
| 238 | |
| 239 | static const Property riscv_cpc_properties[] = { |
| 240 | DEFINE_PROP_UINT32("cluster-id", RISCVCPCState, cluster_id, 0x0), |
| 241 | DEFINE_PROP_UINT32("num-vp", RISCVCPCState, num_vp, 0x1), |
| 242 | DEFINE_PROP_UINT32("num-hart", RISCVCPCState, num_hart, 0x1), |
| 243 | DEFINE_PROP_UINT32("num-core", RISCVCPCState, num_core, 0x1), |
| 244 | DEFINE_PROP_UINT64("vps-start-running-mask", RISCVCPCState, |
| 245 | vps_start_running_mask, 0x1), |
| 246 | }; |
| 247 | |
| 248 | static void riscv_cpc_class_init(ObjectClass *klass, const void *data) |
| 249 | { |
| 250 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 251 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 252 | |
| 253 | dc->realize = riscv_cpc_realize; |
| 254 | rc->phases.hold = riscv_cpc_reset_hold; |
| 255 | dc->vmsd = &vmstate_riscv_cpc; |
| 256 | device_class_set_props(dc, riscv_cpc_properties); |
| 257 | dc->user_creatable = false; |
| 258 | } |
| 259 | |
| 260 | static const TypeInfo riscv_cpc_info = { |
| 261 | .name = TYPE_RISCV_CPC, |
| 262 | .parent = TYPE_SYS_BUS_DEVICE, |
| 263 | .instance_size = sizeof(RISCVCPCState), |
| 264 | .instance_init = riscv_cpc_init, |
| 265 | .instance_finalize = riscv_cpc_finalize, |
| 266 | .class_init = riscv_cpc_class_init, |
| 267 | }; |
| 268 | |
| 269 | static void riscv_cpc_register_types(void) |
| 270 | { |
| 271 | type_register_static(&riscv_cpc_info); |
| 272 | } |
| 273 | |
| 274 | type_init(riscv_cpc_register_types) |