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1 /*
2 * STM32 RCC (only reset and enable registers are implemented)
3 *
4 * Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/log.h"
27 #include "trace.h"
28 #include "hw/core/irq.h"
29 #include "migration/vmstate.h"
30 #include "hw/misc/stm32_rcc.h"
31
32 static void stm32_rcc_reset(DeviceState *dev)
33 {
34 STM32RccState *s = STM32_RCC(dev);
35
36 for (int i = 0; i < STM32_RCC_NREGS; i++) {
37 s->regs[i] = 0;
38 }
39 }
40
41 static uint64_t stm32_rcc_read(void *opaque, hwaddr addr, unsigned int size)
42 {
43 STM32RccState *s = STM32_RCC(opaque);
44
45 uint32_t value = 0;
46 if (addr > STM32_RCC_DCKCFGR2) {
47 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
48 __func__, addr);
49 } else {
50 value = s->regs[addr >> 2];
51 }
52 trace_stm32_rcc_read(addr, value);
53 return value;
54 }
55
56 static int reg_offset_to_irq_offset(hwaddr addr)
57 {
58 /*
59 * The reset and enable registers aren't all consecutive. In getting the
60 * irq index from the register offset, we need to account for the gap
61 * between the AHB regs and the APB regs.
62 */
63 switch (addr) {
64 case STM32_RCC_AHB1_RSTR ... STM32_RCC_AHB3_RSTR:
65 return ((addr - STM32_RCC_AHB1_RSTR) / 4) * 32;
66 case STM32_RCC_APB1_RSTR ... STM32_RCC_APB2_RSTR:
67 return ((addr - STM32_RCC_APB1_RSTR) / 4) * 32 + STM32_RCC_N_AHB_IRQS;
68 case STM32_RCC_AHB1_ENR ... STM32_RCC_AHB3_ENR:
69 return ((addr - STM32_RCC_AHB1_ENR) / 4) * 32;
70 case STM32_RCC_APB1_ENR ... STM32_RCC_APB2_ENR:
71 return ((addr - STM32_RCC_APB1_ENR) / 4) * 32 + STM32_RCC_N_AHB_IRQS;
72 default:
73 g_assert_not_reached();
74 }
75 }
76
77 static void stm32_rcc_write(void *opaque, hwaddr addr,
78 uint64_t val64, unsigned int size)
79 {
80 STM32RccState *s = STM32_RCC(opaque);
81 uint32_t value = val64;
82 uint32_t prev_value, new_value, irq_offset;
83
84 trace_stm32_rcc_write(addr, value);
85
86 if (addr > STM32_RCC_DCKCFGR2) {
87 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
88 __func__, addr);
89 return;
90 }
91
92 switch (addr) {
93 case STM32_RCC_AHB1_RSTR ... STM32_RCC_AHB3_RSTR:
94 case STM32_RCC_APB1_RSTR ... STM32_RCC_APB2_RSTR:
95 prev_value = s->regs[addr / 4];
96 s->regs[addr / 4] = value;
97
98 irq_offset = reg_offset_to_irq_offset(addr);
99 for (int i = 0; i < 32; i++) {
100 new_value = extract32(value, i, 1);
101 if (extract32(prev_value, i, 1) && !new_value) {
102 trace_stm32_rcc_pulse_reset(irq_offset + i, new_value);
103 qemu_set_irq(s->reset_irq[irq_offset + i], new_value);
104 }
105 }
106 return;
107 case STM32_RCC_AHB1_ENR ... STM32_RCC_AHB3_ENR:
108 case STM32_RCC_APB1_ENR ... STM32_RCC_APB2_ENR:
109 prev_value = s->regs[addr / 4];
110 s->regs[addr / 4] = value;
111
112 irq_offset = reg_offset_to_irq_offset(addr);
113 for (int i = 0; i < 32; i++) {
114 new_value = extract32(value, i, 1);
115 if (!extract32(prev_value, i, 1) && new_value) {
116 trace_stm32_rcc_pulse_enable(irq_offset + i, new_value);
117 qemu_set_irq(s->enable_irq[irq_offset + i], new_value);
118 }
119 }
120 return;
121 default:
122 qemu_log_mask(
123 LOG_UNIMP,
124 "%s: The RCC peripheral only supports enable and reset in QEMU\n",
125 __func__
126 );
127 s->regs[addr >> 2] = value;
128 }
129 }
130
131 static const MemoryRegionOps stm32_rcc_ops = {
132 .read = stm32_rcc_read,
133 .write = stm32_rcc_write,
134 .endianness = DEVICE_NATIVE_ENDIAN,
135 };
136
137 static void stm32_rcc_init(Object *obj)
138 {
139 STM32RccState *s = STM32_RCC(obj);
140
141 memory_region_init_io(&s->mmio, obj, &stm32_rcc_ops, s,
142 TYPE_STM32_RCC, STM32_RCC_PERIPHERAL_SIZE);
143 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
144
145 qdev_init_gpio_out(DEVICE(obj), s->reset_irq, STM32_RCC_NIRQS);
146 qdev_init_gpio_out(DEVICE(obj), s->enable_irq, STM32_RCC_NIRQS);
147
148 for (int i = 0; i < STM32_RCC_NIRQS; i++) {
149 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->reset_irq[i]);
150 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->enable_irq[i]);
151 }
152 }
153
154 static const VMStateDescription vmstate_stm32_rcc = {
155 .name = TYPE_STM32_RCC,
156 .version_id = 1,
157 .minimum_version_id = 1,
158 .fields = (const VMStateField[]) {
159 VMSTATE_UINT32_ARRAY(regs, STM32RccState, STM32_RCC_NREGS),
160 VMSTATE_END_OF_LIST()
161 }
162 };
163
164 static void stm32_rcc_class_init(ObjectClass *klass, const void *data)
165 {
166 DeviceClass *dc = DEVICE_CLASS(klass);
167
168 dc->vmsd = &vmstate_stm32_rcc;
169 device_class_set_legacy_reset(dc, stm32_rcc_reset);
170 }
171
172 static const TypeInfo stm32_rcc_info = {
173 .name = TYPE_STM32_RCC,
174 .parent = TYPE_SYS_BUS_DEVICE,
175 .instance_size = sizeof(STM32RccState),
176 .instance_init = stm32_rcc_init,
177 .class_init = stm32_rcc_class_init,
178 };
179
180 static void stm32_rcc_register_types(void)
181 {
182 type_register_static(&stm32_rcc_info);
183 }
184
185 type_init(stm32_rcc_register_types)