| 1 | # See docs/devel/tracing.rst for syntax documentation. |
| 2 | |
| 3 | # allwinner-cpucfg.c |
| 4 | allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32 |
| 5 | allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 6 | allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 7 | |
| 8 | # allwinner-h3-dramc.c |
| 9 | allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" |
| 10 | allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 |
| 11 | allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 12 | allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 13 | allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 14 | allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 15 | allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 16 | allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 17 | |
| 18 | # allwinner-r40-dramc.c |
| 19 | allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells" |
| 20 | allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells" |
| 21 | allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" |
| 22 | allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d" |
| 23 | allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" |
| 24 | allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" |
| 25 | allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 26 | allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 27 | allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 28 | allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 29 | allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 30 | allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 31 | |
| 32 | # allwinner-sid.c |
| 33 | allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 34 | allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 |
| 35 | |
| 36 | # allwinner-sramc.c |
| 37 | allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 38 | allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 39 | |
| 40 | # avr_power.c |
| 41 | avr_power_read(uint8_t value) "power_reduc read value:%u" |
| 42 | avr_power_write(uint8_t value) "power_reduc write value:%u" |
| 43 | |
| 44 | # axp2xx |
| 45 | axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8 |
| 46 | axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8 |
| 47 | axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8 |
| 48 | |
| 49 | # eccmemctl.c |
| 50 | ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" |
| 51 | ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" |
| 52 | ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x" |
| 53 | ecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x" |
| 54 | ecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x" |
| 55 | ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x" |
| 56 | ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x" |
| 57 | ecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x" |
| 58 | ecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x" |
| 59 | ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x" |
| 60 | ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x" |
| 61 | ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x" |
| 62 | ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x" |
| 63 | ecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x" |
| 64 | ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x" |
| 65 | ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x" |
| 66 | ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x" |
| 67 | ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x" |
| 68 | |
| 69 | # empty_slot.c |
| 70 | empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" |
| 71 | |
| 72 | # slavio_misc.c |
| 73 | slavio_misc_update_irq_raise(void) "Raise IRQ" |
| 74 | slavio_misc_update_irq_lower(void) "Lower IRQ" |
| 75 | slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" |
| 76 | slavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x" |
| 77 | slavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x" |
| 78 | slavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x" |
| 79 | slavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x" |
| 80 | slavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x" |
| 81 | slavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x" |
| 82 | slavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x" |
| 83 | slavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x" |
| 84 | slavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x" |
| 85 | slavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x" |
| 86 | apc_mem_writeb(uint32_t val) "Write power management 0x%02x" |
| 87 | apc_mem_readb(uint32_t ret) "Read power management 0x%02x" |
| 88 | slavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x" |
| 89 | slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x" |
| 90 | slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" |
| 91 | slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" |
| 92 | |
| 93 | # aspeed_sbc.c |
| 94 | aspeed_sbc_ignore_cmd(uint32_t cmd) "Ignoring command 0x%" PRIx32 |
| 95 | aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling command 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d" |
| 96 | aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr 0x%" PRIx32 " value 0x%" PRIx32 |
| 97 | aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr 0x%" PRIx32 " value 0x%" PRIx32 |
| 98 | |
| 99 | # aspeed_scu.c |
| 100 | aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 101 | aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 102 | aspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 103 | aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 104 | aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 105 | aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 106 | |
| 107 | # mps2-scc.c |
| 108 | mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 109 | mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 110 | mps2_scc_reset(void) "MPS2 SCC: reset" |
| 111 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 |
| 112 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 |
| 113 | |
| 114 | # mps2-fpgaio.c |
| 115 | mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 116 | mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 117 | mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" |
| 118 | |
| 119 | # msf2-sysreg.c |
| 120 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 |
| 121 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 |
| 122 | msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register" |
| 123 | |
| 124 | # imx7_gpr.c |
| 125 | imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 |
| 126 | imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 |
| 127 | |
| 128 | # imx7_snvs.c |
| 129 | imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" |
| 130 | imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" |
| 131 | |
| 132 | # mos6522.c |
| 133 | mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" |
| 134 | mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 |
| 135 | mos6522_set_sr_int(void) "set sr_int" |
| 136 | mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 |
| 137 | mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" |
| 138 | |
| 139 | # npcm_clk.c |
| 140 | npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| 141 | npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| 142 | |
| 143 | # npcm_gcr.c |
| 144 | npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 |
| 145 | npcm_gcr_write(uint64_t offset, uint64_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 |
| 146 | |
| 147 | # npcm7xx_mft.c |
| 148 | npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |
| 149 | npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |
| 150 | npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 |
| 151 | npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d" |
| 152 | npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 |
| 153 | npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d" |
| 154 | |
| 155 | # npcm7xx_rng.c |
| 156 | npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" |
| 157 | npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" |
| 158 | |
| 159 | # npcm7xx_pwm.c |
| 160 | npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| 161 | npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |
| 162 | npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" |
| 163 | npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" |
| 164 | |
| 165 | # stm32_rcc.c |
| 166 | stm32_rcc_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 167 | stm32_rcc_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 168 | stm32_rcc_pulse_enable(int line, int level) "Enable: %d to %d" |
| 169 | stm32_rcc_pulse_reset(int line, int level) "Reset: %d to %d" |
| 170 | |
| 171 | # stm32f4xx_syscfg.c |
| 172 | stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d" |
| 173 | stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" |
| 174 | stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " |
| 175 | stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 176 | |
| 177 | # stm32f4xx_exti.c |
| 178 | stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" |
| 179 | stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " |
| 180 | stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 181 | |
| 182 | # stm32l4x5_syscfg.c |
| 183 | stm32l4x5_syscfg_set_irq(int gpio, int line, int level) "irq from GPIO: %d, line: %d, level: %d" |
| 184 | stm32l4x5_syscfg_forward_exti(int irq) "irq %d forwarded to EXTI" |
| 185 | stm32l4x5_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " |
| 186 | stm32l4x5_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 187 | |
| 188 | # stm32l4x5_exti.c |
| 189 | stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" |
| 190 | stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 191 | stm32l4x5_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" |
| 192 | |
| 193 | # stm32l4x5_rcc.c |
| 194 | stm32l4x5_rcc_read(uint64_t addr, uint32_t data) "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32 |
| 195 | stm32l4x5_rcc_write(uint64_t addr, uint32_t data) "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32 |
| 196 | stm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled" |
| 197 | stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled" |
| 198 | stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)" |
| 199 | stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source changed: from %u to %u" |
| 200 | stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32 |
| 201 | stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier changed (%u -> %u)" |
| 202 | stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u enabled" |
| 203 | stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u disabled" |
| 204 | stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: divider changed (%u -> %u)" |
| 205 | stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64 |
| 206 | |
| 207 | # tz-mpc.c |
| 208 | tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
| 209 | tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" |
| 210 | tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" |
| 211 | tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" |
| 212 | tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" |
| 213 | tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 |
| 214 | |
| 215 | # tz-msc.c |
| 216 | tz_msc_reset(void) "TZ MSC: reset" |
| 217 | tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d" |
| 218 | tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d" |
| 219 | tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d" |
| 220 | tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d" |
| 221 | tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked" |
| 222 | |
| 223 | # tz-ppc.c |
| 224 | tz_ppc_reset(void) "TZ PPC: reset" |
| 225 | tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" |
| 226 | tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" |
| 227 | tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" |
| 228 | tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" |
| 229 | tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" |
| 230 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" |
| 231 | tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" |
| 232 | tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" |
| 233 | |
| 234 | # iotkit-secctl.c |
| 235 | iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
| 236 | iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" |
| 237 | iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" |
| 238 | iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" |
| 239 | |
| 240 | # imx_ccm.c |
| 241 | imx_ccm_get_clock_frequency(uint32_t clock, uint32_t freq) "(clock = %u) = %u" |
| 242 | imx_ccm_calc_pll(uint32_t pllreq, uint32_t base_freq, uint32_t freq) "(pllreg = 0x%08x, base_freq = %u) = %u" |
| 243 | |
| 244 | # imx6_ccm.c |
| 245 | imx6_analog_get_periph_clk(uint32_t freq) "freq = %u Hz" |
| 246 | imx6_analog_get_pll2_clk(uint32_t freq) "freq = %u Hz" |
| 247 | imx6_analog_get_pll2_pfd0_clk(uint32_t freq) "freq = %u Hz" |
| 248 | imx6_analog_get_pll2_pfd2_clk(uint32_t freq) "freq = %u Hz" |
| 249 | imx6_analog_get_pll3_clk(uint32_t freq) "freq = %u Hz" |
| 250 | imx6_analog_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 251 | imx6_analog_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 252 | imx6_ccm_get_ahb_clk(uint32_t freq) "freq = %u Hz" |
| 253 | imx6_ccm_get_ipg_clk(uint32_t freq) "freq = %u Hz" |
| 254 | imx6_ccm_get_per_clk(uint32_t freq) "freq = %u Hz" |
| 255 | imx6_ccm_get_can_clk(uint32_t freq) "freq = %u Hz" |
| 256 | imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(Clock = %d) = %u" |
| 257 | imx6_ccm_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 258 | imx6_ccm_reset(void) "" |
| 259 | imx6_ccm_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 260 | |
| 261 | # imx6ul_ccm.c |
| 262 | ccm_entry(void) "" |
| 263 | ccm_freq(uint32_t freq) "freq = %d" |
| 264 | ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" |
| 265 | ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 266 | ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 267 | |
| 268 | # imx6_src.c |
| 269 | imx6_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 270 | imx6_src_write(const char *reg_name, uint64_t value) "reg[%s] <= 0x%" PRIx64 |
| 271 | imx6_clear_reset_bit(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 272 | imx6_src_reset(void) "" |
| 273 | |
| 274 | # imx7_src.c |
| 275 | imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 276 | imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 277 | |
| 278 | # imx25_ccm.c |
| 279 | imx25_ccm_get_mpll_clk(uint32_t freq) "freq = %u" |
| 280 | imx25_ccm_get_mcu_clk(uint32_t freq) "freq = %u" |
| 281 | imx25_ccm_get_ahb_clk(uint32_t freq) "freq = %u" |
| 282 | imx25_ccm_get_ipg_clk(uint32_t freq) "freq = %u" |
| 283 | imx25_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(clock = %d) = %u" |
| 284 | imx25_ccm_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 285 | imx25_ccm_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 286 | |
| 287 | # imx31_ccm.c |
| 288 | imx31_ccm_get_mpll_clk(uint32_t freq) "freq = %u" |
| 289 | imx31_ccm_get_pll_ref_clk(uint32_t freq) "freq = %u" |
| 290 | imx31_ccm_get_mcu_main_clk(uint32_t freq) "freq = %u" |
| 291 | imx31_ccm_get_hclk_clk(uint32_t freq) "freq = %u" |
| 292 | imx31_ccm_get_ipg_clk(uint32_t freq) "freq = %u" |
| 293 | imx31_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(clock = %u) = %u" |
| 294 | imx31_ccm_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32 |
| 295 | imx31_ccm_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32 |
| 296 | |
| 297 | # iotkit-sysinfo.c |
| 298 | iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 299 | iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 300 | |
| 301 | # iotkit-sysctl.c |
| 302 | iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 303 | iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 304 | iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" |
| 305 | |
| 306 | # armsse-cpu-pwrctrl.c |
| 307 | armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 308 | armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 309 | |
| 310 | # armsse-cpuid.c |
| 311 | armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 312 | armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 313 | |
| 314 | # armsse-mhu.c |
| 315 | armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 316 | armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 317 | |
| 318 | # aspeed_xdma.c |
| 319 | aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 320 | |
| 321 | # aspeed_pwm.c |
| 322 | aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 323 | aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 324 | |
| 325 | # aspeed_sdmc.c |
| 326 | aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 |
| 327 | aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 |
| 328 | |
| 329 | # aspeed_peci.c |
| 330 | aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 331 | aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 332 | aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32 |
| 333 | |
| 334 | # aspeed_hace.c |
| 335 | aspeed_hace_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 336 | aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 |
| 337 | aspeed_hace_hash_sg(int index, uint64_t list_addr, uint64_t buf_addr, uint32_t len) "%d: list_addr 0x%" PRIx64 " buf_addr 0x%" PRIx64 " len 0x%" PRIx32 |
| 338 | aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64 |
| 339 | aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d" |
| 340 | aspeed_hace_hexdump(const char *desc, uint32_t offset, char *s) "%s: 0x%08x: %s" |
| 341 | |
| 342 | # bcm2835_property.c |
| 343 | bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" |
| 344 | |
| 345 | # bcm2835_mbox.c |
| 346 | bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 |
| 347 | bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 |
| 348 | bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" |
| 349 | |
| 350 | # mac_via.c |
| 351 | via1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x" |
| 352 | via1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x" |
| 353 | via1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x" |
| 354 | via1_rtc_internal_cmd(int cmd) "cmd=0x%02x" |
| 355 | via1_rtc_cmd_invalid(int value) "value=0x%02x" |
| 356 | via1_rtc_internal_time(uint32_t time) "time=0x%08x" |
| 357 | via1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x" |
| 358 | via1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x" |
| 359 | via1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u" |
| 360 | via1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x" |
| 361 | via1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x" |
| 362 | via1_rtc_cmd_test_write(int value) "value=0x%02x" |
| 363 | via1_rtc_cmd_wprotect_write(int value) "value=0x%02x" |
| 364 | via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x" |
| 365 | via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x" |
| 366 | via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" |
| 367 | via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" |
| 368 | via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s" |
| 369 | via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" |
| 370 | via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" |
| 371 | via1_adb_netbsd_enum_hack(void) "using NetBSD enum hack" |
| 372 | via1_auxmode(int mode) "setting auxmode to %d" |
| 373 | via1_timer_hack_state(int state) "setting timer_hack_state to %d" |
| 374 | |
| 375 | # grlib_ahb_apb_pnp.c |
| 376 | grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" |
| 377 | grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" |
| 378 | |
| 379 | # led.c |
| 380 | led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%" |
| 381 | led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%" |
| 382 | |
| 383 | # bcm2835_cprman.c |
| 384 | bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 |
| 385 | bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 |
| 386 | bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 |
| 387 | |
| 388 | # virt_ctrl.c |
| 389 | virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 |
| 390 | virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 |
| 391 | virt_ctrl_reset(void *dev) "ctrl: %p" |
| 392 | virt_ctrl_realize(void *dev) "ctrl: %p" |
| 393 | virt_ctrl_instance_init(void *dev) "ctrl: %p" |
| 394 | |
| 395 | # lasi.c |
| 396 | lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" |
| 397 | lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" |
| 398 | lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" |
| 399 | |
| 400 | # djmemc.c |
| 401 | djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" |
| 402 | djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" |
| 403 | |
| 404 | # iosb.c |
| 405 | iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" |
| 406 | iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" |
| 407 | |
| 408 | # aspeed_sli.c |
| 409 | aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 410 | aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 411 | aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 412 | aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 |
| 413 | |
| 414 | # ivshmem-flat.c |
| 415 | ivshmem_flat_irq_handler(uint16_t vector_id) "Caught interrupt request: vector %d" |
| 416 | ivshmem_flat_new_peer(uint16_t peer_id) "New peer ID: %d" |
| 417 | ivshmem_flat_add_vector_failure(uint16_t vector_id, uint32_t vector_fd, uint16_t peer_id) "Failed to add vector %u (fd = %u) to peer ID %u, maximum number of vectors reached" |
| 418 | ivshmem_flat_add_vector_success(uint16_t vector_id, uint32_t vector_fd, uint16_t peer_id) "Successful addition of vector %u (fd = %u) to peer ID %u" |
| 419 | ivshmem_flat_irq_resolved(const char *irq_qompath) "IRQ QOM path '%s' correctly resolved" |
| 420 | ivshmem_flat_proto_ver_own_id(uint64_t proto_ver, uint16_t peer_id) "Protocol Version = 0x%"PRIx64", Own Peer ID = %u" |
| 421 | ivshmem_flat_shmem_size(int fd, uint64_t size) "Shmem fd (%d) total size is %"PRIu64" byte(s)" |
| 422 | ivshmem_flat_shmem_map(uint64_t addr) "Mapping shmem @ 0x%"PRIx64 |
| 423 | ivshmem_flat_mmio_map(uint64_t addr) "Mapping MMRs @ 0x%"PRIx64 |
| 424 | ivshmem_flat_read_mmr(uint64_t addr_offset) "Read access at offset %"PRIu64 |
| 425 | ivshmem_flat_read_mmr_doorbell(void) "DOORBELL register is write-only!" |
| 426 | ivshmem_flat_read_write_mmr_invalid(uint64_t addr_offset) "No ivshmem register mapped at offset %"PRIu64 |
| 427 | ivshmem_flat_interrupt_invalid_peer(uint16_t peer_id) "Can't interrupt non-existing peer %u" |
| 428 | ivshmem_flat_write_mmr(uint64_t addr_offset) "Write access at offset %"PRIu64 |
| 429 | ivshmem_flat_interrupt_peer(uint16_t peer_id, uint16_t vector_id) "Interrupting peer ID %u, vector %u..." |
| 430 | |
| 431 | # i2c-echo.c |
| 432 | i2c_echo_event(const char *id, const char *event) "%s: %s" |
| 433 | i2c_echo_recv(const char *id, uint8_t data) "%s: recv 0x%02" PRIx8 |
| 434 | i2c_echo_send(const char *id, uint8_t data) "%s: send 0x%02" PRIx8 |
| 435 | |
| 436 | # iommu-testdev.c |
| 437 | iommu_testdev_mmio_read(uint64_t addr, uint64_t value, unsigned size) "addr=0x%" PRIx64 " value=0x%" PRIx64 " size=%u" |
| 438 | iommu_testdev_mmio_write(uint64_t addr, uint64_t value, unsigned size) "addr=0x%" PRIx64 " value=0x%" PRIx64 " size=%u" |
| 439 | iommu_testdev_dma_start(void) "DMA operation started" |
| 440 | iommu_testdev_dma_write(uint64_t gva, uint32_t len) "gva=0x%" PRIx64 " len=%u" |
| 441 | iommu_testdev_dma_read(uint64_t gva, uint32_t len) "gva=0x%" PRIx64 " len=%u" |
| 442 | iommu_testdev_dma_verify(uint32_t expected, uint32_t actual) "expected=0x%x actual=0x%x" |
| 443 | iommu_testdev_dma_result(uint32_t result) "DMA completed result=0x%x" |
| 444 | iommu_testdev_dma_armed(bool armed) "armed=%d" |
| 445 | |
| 446 | # k230_decomp_gzip.c |
| 447 | k230_decomp_gzip_read(uint64_t offset, unsigned int size, uint64_t value) "K230 DECOMP GZIP read: [0x%"PRIx64"] size %u -> 0x%"PRIx64 |
| 448 | k230_decomp_gzip_write(uint64_t offset, unsigned int size, uint64_t value) "K230 DECOMP GZIP write: [0x%"PRIx64"] size %u <- 0x%"PRIx64 |
| 449 | |
| 450 | # vmlaunchupdate.c |
| 451 | launch_update_write(void) "" |
| 452 | vmlaunch_reset_enter(void) "" |
| 453 | vm_launchupdate_finalize(void) "" |
| 454 | restore_host_x86_igvm(void) "" |