| 1 | /* |
| 2 | * QEMU model of the Configuration Frame Control module |
| 3 | * |
| 4 | * Copyright (C) 2023, Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * Written by Francisco Iglesias <francisco.iglesias@amd.com> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | */ |
| 10 | |
| 11 | #include "qemu/osdep.h" |
| 12 | #include "hw/core/sysbus.h" |
| 13 | #include "hw/core/register.h" |
| 14 | #include "hw/core/registerfields.h" |
| 15 | #include "qemu/bitops.h" |
| 16 | #include "qemu/log.h" |
| 17 | #include "qemu/units.h" |
| 18 | #include "qapi/error.h" |
| 19 | #include "hw/core/qdev-properties.h" |
| 20 | #include "migration/vmstate.h" |
| 21 | #include "hw/core/irq.h" |
| 22 | #include "hw/misc/xlnx-versal-cframe-reg.h" |
| 23 | |
| 24 | #ifndef XLNX_VERSAL_CFRAME_REG_ERR_DEBUG |
| 25 | #define XLNX_VERSAL_CFRAME_REG_ERR_DEBUG 0 |
| 26 | #endif |
| 27 | |
| 28 | #define KEYHOLE_STREAM_4K (4 * KiB) |
| 29 | #define N_WORDS_128BIT 4 |
| 30 | |
| 31 | #define MAX_BLOCKTYPE 6 |
| 32 | #define MAX_BLOCKTYPE_FRAMES 0xFFFFF |
| 33 | |
| 34 | enum { |
| 35 | CFRAME_CMD_WCFG = 1, |
| 36 | CFRAME_CMD_ROWON = 2, |
| 37 | CFRAME_CMD_ROWOFF = 3, |
| 38 | CFRAME_CMD_RCFG = 4, |
| 39 | CFRAME_CMD_DLPARK = 5, |
| 40 | }; |
| 41 | |
| 42 | static gint int_cmp(gconstpointer a, gconstpointer b, gpointer user_data) |
| 43 | { |
| 44 | guint ua = GPOINTER_TO_UINT(a); |
| 45 | guint ub = GPOINTER_TO_UINT(b); |
| 46 | return (ua > ub) - (ua < ub); |
| 47 | } |
| 48 | |
| 49 | static void cfrm_imr_update_irq(XlnxVersalCFrameReg *s) |
| 50 | { |
| 51 | bool pending = s->regs[R_CFRM_ISR0] & ~s->regs[R_CFRM_IMR0]; |
| 52 | qemu_set_irq(s->irq_cfrm_imr, pending); |
| 53 | } |
| 54 | |
| 55 | static void cfrm_isr_postw(RegisterInfo *reg, uint64_t val64) |
| 56 | { |
| 57 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 58 | cfrm_imr_update_irq(s); |
| 59 | } |
| 60 | |
| 61 | static uint64_t cfrm_ier_prew(RegisterInfo *reg, uint64_t val64) |
| 62 | { |
| 63 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 64 | |
| 65 | s->regs[R_CFRM_IMR0] &= ~s->regs[R_CFRM_IER0]; |
| 66 | s->regs[R_CFRM_IER0] = 0; |
| 67 | cfrm_imr_update_irq(s); |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | static uint64_t cfrm_idr_prew(RegisterInfo *reg, uint64_t val64) |
| 72 | { |
| 73 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 74 | |
| 75 | s->regs[R_CFRM_IMR0] |= s->regs[R_CFRM_IDR0]; |
| 76 | s->regs[R_CFRM_IDR0] = 0; |
| 77 | cfrm_imr_update_irq(s); |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | static uint64_t cfrm_itr_prew(RegisterInfo *reg, uint64_t val64) |
| 82 | { |
| 83 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 84 | |
| 85 | s->regs[R_CFRM_ISR0] |= s->regs[R_CFRM_ITR0]; |
| 86 | s->regs[R_CFRM_ITR0] = 0; |
| 87 | cfrm_imr_update_irq(s); |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static void cframe_incr_far(XlnxVersalCFrameReg *s) |
| 92 | { |
| 93 | uint32_t faddr = ARRAY_FIELD_EX32(s->regs, FAR0, FRAME_ADDR); |
| 94 | uint32_t blktype = ARRAY_FIELD_EX32(s->regs, FAR0, BLOCKTYPE); |
| 95 | |
| 96 | assert(blktype <= MAX_BLOCKTYPE); |
| 97 | |
| 98 | faddr++; |
| 99 | if (faddr > s->cfg.blktype_num_frames[blktype]) { |
| 100 | /* Restart from 0 and increment block type */ |
| 101 | faddr = 0; |
| 102 | blktype++; |
| 103 | |
| 104 | assert(blktype <= MAX_BLOCKTYPE); |
| 105 | |
| 106 | ARRAY_FIELD_DP32(s->regs, FAR0, BLOCKTYPE, blktype); |
| 107 | } |
| 108 | |
| 109 | ARRAY_FIELD_DP32(s->regs, FAR0, FRAME_ADDR, faddr); |
| 110 | } |
| 111 | |
| 112 | static void cfrm_fdri_post_write(RegisterInfo *reg, uint64_t val) |
| 113 | { |
| 114 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 115 | |
| 116 | if (s->row_configured && s->rowon && s->wcfg) { |
| 117 | |
| 118 | if (fifo32_num_free(&s->new_f_data) >= N_WORDS_128BIT) { |
| 119 | fifo32_push(&s->new_f_data, s->regs[R_FDRI0]); |
| 120 | fifo32_push(&s->new_f_data, s->regs[R_FDRI1]); |
| 121 | fifo32_push(&s->new_f_data, s->regs[R_FDRI2]); |
| 122 | fifo32_push(&s->new_f_data, s->regs[R_FDRI3]); |
| 123 | } |
| 124 | |
| 125 | if (fifo32_is_full(&s->new_f_data)) { |
| 126 | uint32_t addr = extract32(s->regs[R_FAR0], 0, 23); |
| 127 | XlnxCFrame *f = g_new(XlnxCFrame, 1); |
| 128 | |
| 129 | for (int i = 0; i < FRAME_NUM_WORDS; i++) { |
| 130 | f->data[i] = fifo32_pop(&s->new_f_data); |
| 131 | } |
| 132 | |
| 133 | g_tree_replace(s->cframes, GUINT_TO_POINTER(addr), f); |
| 134 | |
| 135 | cframe_incr_far(s); |
| 136 | |
| 137 | fifo32_reset(&s->new_f_data); |
| 138 | } |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | static void cfrm_readout_frames(XlnxVersalCFrameReg *s, uint32_t start_addr, |
| 143 | uint32_t end_addr) |
| 144 | { |
| 145 | /* |
| 146 | * NB: when our minimum glib version is at least 2.68 we can improve the |
| 147 | * performance of the cframe traversal by using g_tree_lookup_node and |
| 148 | * g_tree_node_next (instead of calling g_tree_lookup for finding each |
| 149 | * cframe). |
| 150 | */ |
| 151 | for (uint32_t addr = start_addr; addr < end_addr; addr++) { |
| 152 | XlnxCFrame *f = g_tree_lookup(s->cframes, GUINT_TO_POINTER(addr)); |
| 153 | |
| 154 | /* Transmit the data if a frame was found */ |
| 155 | if (f) { |
| 156 | for (int i = 0; i < FRAME_NUM_WORDS; i += 4) { |
| 157 | XlnxCfiPacket pkt = {}; |
| 158 | |
| 159 | pkt.data[0] = f->data[i]; |
| 160 | pkt.data[1] = f->data[i + 1]; |
| 161 | pkt.data[2] = f->data[i + 2]; |
| 162 | pkt.data[3] = f->data[i + 3]; |
| 163 | |
| 164 | if (s->cfg.cfu_fdro) { |
| 165 | xlnx_cfi_transfer_packet(s->cfg.cfu_fdro, &pkt); |
| 166 | } |
| 167 | } |
| 168 | } |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | static void cfrm_frcnt_post_write(RegisterInfo *reg, uint64_t val) |
| 173 | { |
| 174 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 175 | |
| 176 | if (s->row_configured && s->rowon && s->rcfg) { |
| 177 | uint32_t start_addr = extract32(s->regs[R_FAR0], 0, 23); |
| 178 | uint32_t end_addr = start_addr + s->regs[R_FRCNT0] / FRAME_NUM_QWORDS; |
| 179 | |
| 180 | cfrm_readout_frames(s, start_addr, end_addr); |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | static void cfrm_cmd_post_write(RegisterInfo *reg, uint64_t val) |
| 185 | { |
| 186 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 187 | |
| 188 | if (s->row_configured) { |
| 189 | uint8_t cmd = ARRAY_FIELD_EX32(s->regs, CMD0, CMD); |
| 190 | |
| 191 | switch (cmd) { |
| 192 | case CFRAME_CMD_WCFG: |
| 193 | s->wcfg = true; |
| 194 | break; |
| 195 | case CFRAME_CMD_ROWON: |
| 196 | s->rowon = true; |
| 197 | break; |
| 198 | case CFRAME_CMD_ROWOFF: |
| 199 | s->rowon = false; |
| 200 | break; |
| 201 | case CFRAME_CMD_RCFG: |
| 202 | s->rcfg = true; |
| 203 | break; |
| 204 | case CFRAME_CMD_DLPARK: |
| 205 | s->wcfg = false; |
| 206 | s->rcfg = false; |
| 207 | break; |
| 208 | default: |
| 209 | break; |
| 210 | }; |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | static uint64_t cfrm_last_frame_bot_post_read(RegisterInfo *reg, |
| 215 | uint64_t val64) |
| 216 | { |
| 217 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 218 | uint64_t val = 0; |
| 219 | |
| 220 | switch (reg->access->addr) { |
| 221 | case A_LAST_FRAME_BOT0: |
| 222 | val = FIELD_DP32(val, LAST_FRAME_BOT0, BLOCKTYPE1_LAST_FRAME_LSB, |
| 223 | s->cfg.blktype_num_frames[1]); |
| 224 | val = FIELD_DP32(val, LAST_FRAME_BOT0, BLOCKTYPE0_LAST_FRAME, |
| 225 | s->cfg.blktype_num_frames[0]); |
| 226 | break; |
| 227 | case A_LAST_FRAME_BOT1: |
| 228 | val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE3_LAST_FRAME_LSB, |
| 229 | s->cfg.blktype_num_frames[3]); |
| 230 | val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE2_LAST_FRAME, |
| 231 | s->cfg.blktype_num_frames[2]); |
| 232 | val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE1_LAST_FRAME_MSB, |
| 233 | (s->cfg.blktype_num_frames[1] >> 12)); |
| 234 | break; |
| 235 | case A_LAST_FRAME_BOT2: |
| 236 | val = FIELD_DP32(val, LAST_FRAME_BOT2, BLOCKTYPE3_LAST_FRAME_MSB, |
| 237 | (s->cfg.blktype_num_frames[3] >> 4)); |
| 238 | break; |
| 239 | case A_LAST_FRAME_BOT3: |
| 240 | default: |
| 241 | break; |
| 242 | } |
| 243 | |
| 244 | return val; |
| 245 | } |
| 246 | |
| 247 | static uint64_t cfrm_last_frame_top_post_read(RegisterInfo *reg, |
| 248 | uint64_t val64) |
| 249 | { |
| 250 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 251 | uint64_t val = 0; |
| 252 | |
| 253 | switch (reg->access->addr) { |
| 254 | case A_LAST_FRAME_TOP0: |
| 255 | val = FIELD_DP32(val, LAST_FRAME_TOP0, BLOCKTYPE5_LAST_FRAME_LSB, |
| 256 | s->cfg.blktype_num_frames[5]); |
| 257 | val = FIELD_DP32(val, LAST_FRAME_TOP0, BLOCKTYPE4_LAST_FRAME, |
| 258 | s->cfg.blktype_num_frames[4]); |
| 259 | break; |
| 260 | case A_LAST_FRAME_TOP1: |
| 261 | val = FIELD_DP32(val, LAST_FRAME_TOP1, BLOCKTYPE6_LAST_FRAME, |
| 262 | s->cfg.blktype_num_frames[6]); |
| 263 | val = FIELD_DP32(val, LAST_FRAME_TOP1, BLOCKTYPE5_LAST_FRAME_MSB, |
| 264 | (s->cfg.blktype_num_frames[5] >> 12)); |
| 265 | break; |
| 266 | case A_LAST_FRAME_TOP2: |
| 267 | case A_LAST_FRAME_BOT3: |
| 268 | default: |
| 269 | break; |
| 270 | } |
| 271 | |
| 272 | return val; |
| 273 | } |
| 274 | |
| 275 | static void cfrm_far_sfr_post_write(RegisterInfo *reg, uint64_t val) |
| 276 | { |
| 277 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque); |
| 278 | |
| 279 | if (s->row_configured && s->rowon && s->rcfg) { |
| 280 | uint32_t start_addr = extract32(s->regs[R_FAR_SFR0], 0, 23); |
| 281 | |
| 282 | /* Readback 1 frame */ |
| 283 | cfrm_readout_frames(s, start_addr, start_addr + 1); |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | static const RegisterAccessInfo cframe_reg_regs_info[] = { |
| 288 | { .name = "CRC0", .addr = A_CRC0, |
| 289 | .rsvd = 0x00000000, |
| 290 | },{ .name = "CRC1", .addr = A_CRC0, |
| 291 | .rsvd = 0xffffffff, |
| 292 | },{ .name = "CRC2", .addr = A_CRC0, |
| 293 | .rsvd = 0xffffffff, |
| 294 | },{ .name = "CRC3", .addr = A_CRC0, |
| 295 | .rsvd = 0xffffffff, |
| 296 | },{ .name = "FAR0", .addr = A_FAR0, |
| 297 | .rsvd = 0xfe000000, |
| 298 | },{ .name = "FAR1", .addr = A_FAR1, |
| 299 | .rsvd = 0xffffffff, |
| 300 | },{ .name = "FAR2", .addr = A_FAR2, |
| 301 | .rsvd = 0xffffffff, |
| 302 | },{ .name = "FAR3", .addr = A_FAR3, |
| 303 | .rsvd = 0xffffffff, |
| 304 | },{ .name = "FAR_SFR0", .addr = A_FAR_SFR0, |
| 305 | .rsvd = 0xff800000, |
| 306 | },{ .name = "FAR_SFR1", .addr = A_FAR_SFR1, |
| 307 | .rsvd = 0xffffffff, |
| 308 | },{ .name = "FAR_SFR2", .addr = A_FAR_SFR2, |
| 309 | .rsvd = 0xffffffff, |
| 310 | },{ .name = "FAR_SFR3", .addr = A_FAR_SFR3, |
| 311 | .rsvd = 0xffffffff, |
| 312 | .post_write = cfrm_far_sfr_post_write, |
| 313 | },{ .name = "FDRI0", .addr = A_FDRI0, |
| 314 | },{ .name = "FDRI1", .addr = A_FDRI1, |
| 315 | },{ .name = "FDRI2", .addr = A_FDRI2, |
| 316 | },{ .name = "FDRI3", .addr = A_FDRI3, |
| 317 | .post_write = cfrm_fdri_post_write, |
| 318 | },{ .name = "FRCNT0", .addr = A_FRCNT0, |
| 319 | .rsvd = 0x00000000, |
| 320 | },{ .name = "FRCNT1", .addr = A_FRCNT1, |
| 321 | .rsvd = 0xffffffff, |
| 322 | },{ .name = "FRCNT2", .addr = A_FRCNT2, |
| 323 | .rsvd = 0xffffffff, |
| 324 | },{ .name = "FRCNT3", .addr = A_FRCNT3, |
| 325 | .rsvd = 0xffffffff, |
| 326 | .post_write = cfrm_frcnt_post_write |
| 327 | },{ .name = "CMD0", .addr = A_CMD0, |
| 328 | .rsvd = 0xffffffe0, |
| 329 | },{ .name = "CMD1", .addr = A_CMD1, |
| 330 | .rsvd = 0xffffffff, |
| 331 | },{ .name = "CMD2", .addr = A_CMD2, |
| 332 | .rsvd = 0xffffffff, |
| 333 | },{ .name = "CMD3", .addr = A_CMD3, |
| 334 | .rsvd = 0xffffffff, |
| 335 | .post_write = cfrm_cmd_post_write |
| 336 | },{ .name = "CR_MASK0", .addr = A_CR_MASK0, |
| 337 | .rsvd = 0x00000000, |
| 338 | },{ .name = "CR_MASK1", .addr = A_CR_MASK1, |
| 339 | .rsvd = 0x00000000, |
| 340 | },{ .name = "CR_MASK2", .addr = A_CR_MASK2, |
| 341 | .rsvd = 0x00000000, |
| 342 | },{ .name = "CR_MASK3", .addr = A_CR_MASK3, |
| 343 | .rsvd = 0xffffffff, |
| 344 | },{ .name = "CTL0", .addr = A_CTL0, |
| 345 | .rsvd = 0xfffffff8, |
| 346 | },{ .name = "CTL1", .addr = A_CTL1, |
| 347 | .rsvd = 0xffffffff, |
| 348 | },{ .name = "CTL2", .addr = A_CTL2, |
| 349 | .rsvd = 0xffffffff, |
| 350 | },{ .name = "CTL3", .addr = A_CTL3, |
| 351 | .rsvd = 0xffffffff, |
| 352 | },{ .name = "CFRM_ISR0", .addr = A_CFRM_ISR0, |
| 353 | .rsvd = 0xffc04000, |
| 354 | .w1c = 0x3bfff, |
| 355 | },{ .name = "CFRM_ISR1", .addr = A_CFRM_ISR1, |
| 356 | .rsvd = 0xffffffff, |
| 357 | },{ .name = "CFRM_ISR2", .addr = A_CFRM_ISR2, |
| 358 | .rsvd = 0xffffffff, |
| 359 | },{ .name = "CFRM_ISR3", .addr = A_CFRM_ISR3, |
| 360 | .rsvd = 0xffffffff, |
| 361 | .post_write = cfrm_isr_postw, |
| 362 | },{ .name = "CFRM_IMR0", .addr = A_CFRM_IMR0, |
| 363 | .rsvd = 0xffc04000, |
| 364 | .ro = 0xfffff, |
| 365 | .reset = 0x3bfff, |
| 366 | },{ .name = "CFRM_IMR1", .addr = A_CFRM_IMR1, |
| 367 | .rsvd = 0xffffffff, |
| 368 | },{ .name = "CFRM_IMR2", .addr = A_CFRM_IMR2, |
| 369 | .rsvd = 0xffffffff, |
| 370 | },{ .name = "CFRM_IMR3", .addr = A_CFRM_IMR3, |
| 371 | .rsvd = 0xffffffff, |
| 372 | },{ .name = "CFRM_IER0", .addr = A_CFRM_IER0, |
| 373 | .rsvd = 0xffc04000, |
| 374 | },{ .name = "CFRM_IER1", .addr = A_CFRM_IER1, |
| 375 | .rsvd = 0xffffffff, |
| 376 | },{ .name = "CFRM_IER2", .addr = A_CFRM_IER2, |
| 377 | .rsvd = 0xffffffff, |
| 378 | },{ .name = "CFRM_IER3", .addr = A_CFRM_IER3, |
| 379 | .rsvd = 0xffffffff, |
| 380 | .pre_write = cfrm_ier_prew, |
| 381 | },{ .name = "CFRM_IDR0", .addr = A_CFRM_IDR0, |
| 382 | .rsvd = 0xffc04000, |
| 383 | },{ .name = "CFRM_IDR1", .addr = A_CFRM_IDR1, |
| 384 | .rsvd = 0xffffffff, |
| 385 | },{ .name = "CFRM_IDR2", .addr = A_CFRM_IDR2, |
| 386 | .rsvd = 0xffffffff, |
| 387 | },{ .name = "CFRM_IDR3", .addr = A_CFRM_IDR3, |
| 388 | .rsvd = 0xffffffff, |
| 389 | .pre_write = cfrm_idr_prew, |
| 390 | },{ .name = "CFRM_ITR0", .addr = A_CFRM_ITR0, |
| 391 | .rsvd = 0xffc04000, |
| 392 | },{ .name = "CFRM_ITR1", .addr = A_CFRM_ITR1, |
| 393 | .rsvd = 0xffffffff, |
| 394 | },{ .name = "CFRM_ITR2", .addr = A_CFRM_ITR2, |
| 395 | .rsvd = 0xffffffff, |
| 396 | },{ .name = "CFRM_ITR3", .addr = A_CFRM_ITR3, |
| 397 | .rsvd = 0xffffffff, |
| 398 | .pre_write = cfrm_itr_prew, |
| 399 | },{ .name = "SEU_SYNDRM00", .addr = A_SEU_SYNDRM00, |
| 400 | },{ .name = "SEU_SYNDRM01", .addr = A_SEU_SYNDRM01, |
| 401 | },{ .name = "SEU_SYNDRM02", .addr = A_SEU_SYNDRM02, |
| 402 | },{ .name = "SEU_SYNDRM03", .addr = A_SEU_SYNDRM03, |
| 403 | },{ .name = "SEU_SYNDRM10", .addr = A_SEU_SYNDRM10, |
| 404 | },{ .name = "SEU_SYNDRM11", .addr = A_SEU_SYNDRM11, |
| 405 | },{ .name = "SEU_SYNDRM12", .addr = A_SEU_SYNDRM12, |
| 406 | },{ .name = "SEU_SYNDRM13", .addr = A_SEU_SYNDRM13, |
| 407 | },{ .name = "SEU_SYNDRM20", .addr = A_SEU_SYNDRM20, |
| 408 | },{ .name = "SEU_SYNDRM21", .addr = A_SEU_SYNDRM21, |
| 409 | },{ .name = "SEU_SYNDRM22", .addr = A_SEU_SYNDRM22, |
| 410 | },{ .name = "SEU_SYNDRM23", .addr = A_SEU_SYNDRM23, |
| 411 | },{ .name = "SEU_SYNDRM30", .addr = A_SEU_SYNDRM30, |
| 412 | },{ .name = "SEU_SYNDRM31", .addr = A_SEU_SYNDRM31, |
| 413 | },{ .name = "SEU_SYNDRM32", .addr = A_SEU_SYNDRM32, |
| 414 | },{ .name = "SEU_SYNDRM33", .addr = A_SEU_SYNDRM33, |
| 415 | },{ .name = "SEU_VIRTUAL_SYNDRM0", .addr = A_SEU_VIRTUAL_SYNDRM0, |
| 416 | },{ .name = "SEU_VIRTUAL_SYNDRM1", .addr = A_SEU_VIRTUAL_SYNDRM1, |
| 417 | },{ .name = "SEU_VIRTUAL_SYNDRM2", .addr = A_SEU_VIRTUAL_SYNDRM2, |
| 418 | },{ .name = "SEU_VIRTUAL_SYNDRM3", .addr = A_SEU_VIRTUAL_SYNDRM3, |
| 419 | },{ .name = "SEU_CRC0", .addr = A_SEU_CRC0, |
| 420 | },{ .name = "SEU_CRC1", .addr = A_SEU_CRC1, |
| 421 | },{ .name = "SEU_CRC2", .addr = A_SEU_CRC2, |
| 422 | },{ .name = "SEU_CRC3", .addr = A_SEU_CRC3, |
| 423 | },{ .name = "CFRAME_FAR_BOT0", .addr = A_CFRAME_FAR_BOT0, |
| 424 | },{ .name = "CFRAME_FAR_BOT1", .addr = A_CFRAME_FAR_BOT1, |
| 425 | },{ .name = "CFRAME_FAR_BOT2", .addr = A_CFRAME_FAR_BOT2, |
| 426 | },{ .name = "CFRAME_FAR_BOT3", .addr = A_CFRAME_FAR_BOT3, |
| 427 | },{ .name = "CFRAME_FAR_TOP0", .addr = A_CFRAME_FAR_TOP0, |
| 428 | },{ .name = "CFRAME_FAR_TOP1", .addr = A_CFRAME_FAR_TOP1, |
| 429 | },{ .name = "CFRAME_FAR_TOP2", .addr = A_CFRAME_FAR_TOP2, |
| 430 | },{ .name = "CFRAME_FAR_TOP3", .addr = A_CFRAME_FAR_TOP3, |
| 431 | },{ .name = "LAST_FRAME_BOT0", .addr = A_LAST_FRAME_BOT0, |
| 432 | .ro = 0xffffffff, |
| 433 | .post_read = cfrm_last_frame_bot_post_read, |
| 434 | },{ .name = "LAST_FRAME_BOT1", .addr = A_LAST_FRAME_BOT1, |
| 435 | .ro = 0xffffffff, |
| 436 | .post_read = cfrm_last_frame_bot_post_read, |
| 437 | },{ .name = "LAST_FRAME_BOT2", .addr = A_LAST_FRAME_BOT2, |
| 438 | .ro = 0xffffffff, |
| 439 | .post_read = cfrm_last_frame_bot_post_read, |
| 440 | },{ .name = "LAST_FRAME_BOT3", .addr = A_LAST_FRAME_BOT3, |
| 441 | .ro = 0xffffffff, |
| 442 | .post_read = cfrm_last_frame_bot_post_read, |
| 443 | },{ .name = "LAST_FRAME_TOP0", .addr = A_LAST_FRAME_TOP0, |
| 444 | .ro = 0xffffffff, |
| 445 | .post_read = cfrm_last_frame_top_post_read, |
| 446 | },{ .name = "LAST_FRAME_TOP1", .addr = A_LAST_FRAME_TOP1, |
| 447 | .ro = 0xffffffff, |
| 448 | .post_read = cfrm_last_frame_top_post_read, |
| 449 | },{ .name = "LAST_FRAME_TOP2", .addr = A_LAST_FRAME_TOP2, |
| 450 | .ro = 0xffffffff, |
| 451 | .post_read = cfrm_last_frame_top_post_read, |
| 452 | },{ .name = "LAST_FRAME_TOP3", .addr = A_LAST_FRAME_TOP3, |
| 453 | .ro = 0xffffffff, |
| 454 | .post_read = cfrm_last_frame_top_post_read, |
| 455 | } |
| 456 | }; |
| 457 | |
| 458 | static void cframe_reg_cfi_transfer_packet(XlnxCfiIf *cfi_if, |
| 459 | XlnxCfiPacket *pkt) |
| 460 | { |
| 461 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(cfi_if); |
| 462 | uint64_t we = MAKE_64BIT_MASK(0, 4 * 8); |
| 463 | |
| 464 | if (!s->row_configured) { |
| 465 | return; |
| 466 | } |
| 467 | |
| 468 | switch (pkt->reg_addr) { |
| 469 | case CFRAME_FAR: |
| 470 | s->regs[R_FAR0] = pkt->data[0]; |
| 471 | break; |
| 472 | case CFRAME_SFR: |
| 473 | s->regs[R_FAR_SFR0] = pkt->data[0]; |
| 474 | register_write(&s->regs_info[R_FAR_SFR3], 0, |
| 475 | we, object_get_typename(OBJECT(s)), |
| 476 | XLNX_VERSAL_CFRAME_REG_ERR_DEBUG); |
| 477 | break; |
| 478 | case CFRAME_FDRI: |
| 479 | s->regs[R_FDRI0] = pkt->data[0]; |
| 480 | s->regs[R_FDRI1] = pkt->data[1]; |
| 481 | s->regs[R_FDRI2] = pkt->data[2]; |
| 482 | register_write(&s->regs_info[R_FDRI3], pkt->data[3], |
| 483 | we, object_get_typename(OBJECT(s)), |
| 484 | XLNX_VERSAL_CFRAME_REG_ERR_DEBUG); |
| 485 | break; |
| 486 | case CFRAME_CMD: |
| 487 | ARRAY_FIELD_DP32(s->regs, CMD0, CMD, pkt->data[0]); |
| 488 | |
| 489 | register_write(&s->regs_info[R_CMD3], 0, |
| 490 | we, object_get_typename(OBJECT(s)), |
| 491 | XLNX_VERSAL_CFRAME_REG_ERR_DEBUG); |
| 492 | break; |
| 493 | default: |
| 494 | break; |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | static uint64_t cframe_reg_fdri_read(void *opaque, hwaddr addr, unsigned size) |
| 499 | { |
| 500 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%" |
| 501 | HWADDR_PRIx "\n", __func__, addr); |
| 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | static void cframe_reg_fdri_write(void *opaque, hwaddr addr, uint64_t value, |
| 506 | unsigned size) |
| 507 | { |
| 508 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(opaque); |
| 509 | uint32_t wfifo[WFIFO_SZ]; |
| 510 | |
| 511 | if (update_wfifo(addr, value, s->wfifo, wfifo)) { |
| 512 | uint64_t we = MAKE_64BIT_MASK(0, 4 * 8); |
| 513 | |
| 514 | s->regs[R_FDRI0] = wfifo[0]; |
| 515 | s->regs[R_FDRI1] = wfifo[1]; |
| 516 | s->regs[R_FDRI2] = wfifo[2]; |
| 517 | register_write(&s->regs_info[R_FDRI3], wfifo[3], |
| 518 | we, object_get_typename(OBJECT(s)), |
| 519 | XLNX_VERSAL_CFRAME_REG_ERR_DEBUG); |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | static void cframe_reg_reset_enter(Object *obj, ResetType type) |
| 524 | { |
| 525 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj); |
| 526 | unsigned int i; |
| 527 | |
| 528 | for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { |
| 529 | register_reset(&s->regs_info[i]); |
| 530 | } |
| 531 | memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t)); |
| 532 | fifo32_reset(&s->new_f_data); |
| 533 | |
| 534 | if (g_tree_nnodes(s->cframes)) { |
| 535 | /* |
| 536 | * Take a reference so when g_tree_destroy() unrefs it we keep the |
| 537 | * GTree and only destroy its contents. NB: when our minimum |
| 538 | * glib version is at least 2.70 we could use g_tree_remove_all(). |
| 539 | */ |
| 540 | g_tree_ref(s->cframes); |
| 541 | g_tree_destroy(s->cframes); |
| 542 | } |
| 543 | } |
| 544 | |
| 545 | static void cframe_reg_reset_hold(Object *obj, ResetType type) |
| 546 | { |
| 547 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj); |
| 548 | |
| 549 | cfrm_imr_update_irq(s); |
| 550 | } |
| 551 | |
| 552 | static const MemoryRegionOps cframe_reg_ops = { |
| 553 | .read = register_read_memory, |
| 554 | .write = register_write_memory, |
| 555 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 556 | .valid = { |
| 557 | .min_access_size = 4, |
| 558 | .max_access_size = 4, |
| 559 | }, |
| 560 | }; |
| 561 | |
| 562 | static const MemoryRegionOps cframe_reg_fdri_ops = { |
| 563 | .read = cframe_reg_fdri_read, |
| 564 | .write = cframe_reg_fdri_write, |
| 565 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 566 | .valid = { |
| 567 | .min_access_size = 4, |
| 568 | .max_access_size = 4, |
| 569 | }, |
| 570 | }; |
| 571 | |
| 572 | static uint64_t cframes_bcast_reg_read(void *opaque, hwaddr addr, unsigned size) |
| 573 | { |
| 574 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%" |
| 575 | HWADDR_PRIx "\n", __func__, addr); |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | static void cframes_bcast_write(XlnxVersalCFrameBcastReg *s, uint8_t reg_addr, |
| 580 | uint32_t *wfifo) |
| 581 | { |
| 582 | XlnxCfiPacket pkt = { |
| 583 | .reg_addr = reg_addr, |
| 584 | .data[0] = wfifo[0], |
| 585 | .data[1] = wfifo[1], |
| 586 | .data[2] = wfifo[2], |
| 587 | .data[3] = wfifo[3] |
| 588 | }; |
| 589 | |
| 590 | for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) { |
| 591 | if (s->cfg.cframe[i]) { |
| 592 | xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt); |
| 593 | } |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | static void cframes_bcast_reg_write(void *opaque, hwaddr addr, uint64_t value, |
| 598 | unsigned size) |
| 599 | { |
| 600 | XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque); |
| 601 | uint32_t wfifo[WFIFO_SZ]; |
| 602 | |
| 603 | if (update_wfifo(addr, value, s->wfifo, wfifo)) { |
| 604 | uint8_t reg_addr = extract32(addr, 4, 6); |
| 605 | |
| 606 | cframes_bcast_write(s, reg_addr, wfifo); |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | static uint64_t cframes_bcast_fdri_read(void *opaque, hwaddr addr, |
| 611 | unsigned size) |
| 612 | { |
| 613 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%" |
| 614 | HWADDR_PRIx "\n", __func__, addr); |
| 615 | return 0; |
| 616 | } |
| 617 | |
| 618 | static void cframes_bcast_fdri_write(void *opaque, hwaddr addr, uint64_t value, |
| 619 | unsigned size) |
| 620 | { |
| 621 | XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque); |
| 622 | uint32_t wfifo[WFIFO_SZ]; |
| 623 | |
| 624 | if (update_wfifo(addr, value, s->wfifo, wfifo)) { |
| 625 | cframes_bcast_write(s, CFRAME_FDRI, wfifo); |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | static const MemoryRegionOps cframes_bcast_reg_reg_ops = { |
| 630 | .read = cframes_bcast_reg_read, |
| 631 | .write = cframes_bcast_reg_write, |
| 632 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 633 | .valid = { |
| 634 | .min_access_size = 4, |
| 635 | .max_access_size = 4, |
| 636 | }, |
| 637 | }; |
| 638 | |
| 639 | static const MemoryRegionOps cframes_bcast_reg_fdri_ops = { |
| 640 | .read = cframes_bcast_fdri_read, |
| 641 | .write = cframes_bcast_fdri_write, |
| 642 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 643 | .valid = { |
| 644 | .min_access_size = 4, |
| 645 | .max_access_size = 4, |
| 646 | }, |
| 647 | }; |
| 648 | |
| 649 | static void cframe_reg_realize(DeviceState *dev, Error **errp) |
| 650 | { |
| 651 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(dev); |
| 652 | |
| 653 | for (int i = 0; i < ARRAY_SIZE(s->cfg.blktype_num_frames); i++) { |
| 654 | if (s->cfg.blktype_num_frames[i] > MAX_BLOCKTYPE_FRAMES) { |
| 655 | error_setg(errp, |
| 656 | "blktype-frames%d > 0xFFFFF (max frame per block)", |
| 657 | i); |
| 658 | return; |
| 659 | } |
| 660 | if (s->cfg.blktype_num_frames[i]) { |
| 661 | s->row_configured = true; |
| 662 | } |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | static void cframe_reg_init(Object *obj) |
| 667 | { |
| 668 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj); |
| 669 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 670 | RegisterInfoArray *reg_array; |
| 671 | |
| 672 | memory_region_init(&s->iomem, obj, TYPE_XLNX_VERSAL_CFRAME_REG, |
| 673 | CFRAME_REG_R_MAX * 4); |
| 674 | reg_array = |
| 675 | register_init_block32(DEVICE(obj), cframe_reg_regs_info, |
| 676 | ARRAY_SIZE(cframe_reg_regs_info), |
| 677 | s->regs_info, s->regs, |
| 678 | &cframe_reg_ops, |
| 679 | XLNX_VERSAL_CFRAME_REG_ERR_DEBUG, |
| 680 | CFRAME_REG_R_MAX * 4); |
| 681 | memory_region_add_subregion(&s->iomem, |
| 682 | 0x0, |
| 683 | ®_array->mem); |
| 684 | sysbus_init_mmio(sbd, &s->iomem); |
| 685 | memory_region_init_io(&s->iomem_fdri, obj, &cframe_reg_fdri_ops, s, |
| 686 | TYPE_XLNX_VERSAL_CFRAME_REG "-fdri", |
| 687 | KEYHOLE_STREAM_4K); |
| 688 | sysbus_init_mmio(sbd, &s->iomem_fdri); |
| 689 | sysbus_init_irq(sbd, &s->irq_cfrm_imr); |
| 690 | |
| 691 | s->cframes = g_tree_new_full((GCompareDataFunc)int_cmp, NULL, |
| 692 | NULL, (GDestroyNotify)g_free); |
| 693 | fifo32_create(&s->new_f_data, FRAME_NUM_WORDS); |
| 694 | } |
| 695 | |
| 696 | static void cframe_reg_finalize(Object *obj) |
| 697 | { |
| 698 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj); |
| 699 | |
| 700 | fifo32_destroy(&s->new_f_data); |
| 701 | g_tree_destroy(s->cframes); |
| 702 | } |
| 703 | |
| 704 | static const VMStateDescription vmstate_cframe = { |
| 705 | .name = "cframe", |
| 706 | .version_id = 1, |
| 707 | .minimum_version_id = 1, |
| 708 | .fields = (const VMStateField[]) { |
| 709 | VMSTATE_UINT32_ARRAY(data, XlnxCFrame, FRAME_NUM_WORDS), |
| 710 | VMSTATE_END_OF_LIST() |
| 711 | } |
| 712 | }; |
| 713 | |
| 714 | static const VMStateDescription vmstate_cframe_reg = { |
| 715 | .name = TYPE_XLNX_VERSAL_CFRAME_REG, |
| 716 | .version_id = 1, |
| 717 | .minimum_version_id = 1, |
| 718 | .fields = (const VMStateField[]) { |
| 719 | VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFrameReg, 4), |
| 720 | VMSTATE_UINT32_ARRAY(regs, XlnxVersalCFrameReg, CFRAME_REG_R_MAX), |
| 721 | VMSTATE_BOOL(rowon, XlnxVersalCFrameReg), |
| 722 | VMSTATE_BOOL(wcfg, XlnxVersalCFrameReg), |
| 723 | VMSTATE_BOOL(rcfg, XlnxVersalCFrameReg), |
| 724 | VMSTATE_GTREE_DIRECT_KEY_V(cframes, XlnxVersalCFrameReg, 1, |
| 725 | &vmstate_cframe, XlnxCFrame), |
| 726 | VMSTATE_FIFO32(new_f_data, XlnxVersalCFrameReg), |
| 727 | VMSTATE_END_OF_LIST(), |
| 728 | } |
| 729 | }; |
| 730 | |
| 731 | static const Property cframe_regs_props[] = { |
| 732 | DEFINE_PROP_LINK("cfu-fdro", XlnxVersalCFrameReg, cfg.cfu_fdro, |
| 733 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 734 | DEFINE_PROP_UINT32("blktype0-frames", XlnxVersalCFrameReg, |
| 735 | cfg.blktype_num_frames[0], 0), |
| 736 | DEFINE_PROP_UINT32("blktype1-frames", XlnxVersalCFrameReg, |
| 737 | cfg.blktype_num_frames[1], 0), |
| 738 | DEFINE_PROP_UINT32("blktype2-frames", XlnxVersalCFrameReg, |
| 739 | cfg.blktype_num_frames[2], 0), |
| 740 | DEFINE_PROP_UINT32("blktype3-frames", XlnxVersalCFrameReg, |
| 741 | cfg.blktype_num_frames[3], 0), |
| 742 | DEFINE_PROP_UINT32("blktype4-frames", XlnxVersalCFrameReg, |
| 743 | cfg.blktype_num_frames[4], 0), |
| 744 | DEFINE_PROP_UINT32("blktype5-frames", XlnxVersalCFrameReg, |
| 745 | cfg.blktype_num_frames[5], 0), |
| 746 | DEFINE_PROP_UINT32("blktype6-frames", XlnxVersalCFrameReg, |
| 747 | cfg.blktype_num_frames[6], 0), |
| 748 | }; |
| 749 | |
| 750 | static void cframe_bcast_reg_init(Object *obj) |
| 751 | { |
| 752 | XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(obj); |
| 753 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 754 | |
| 755 | memory_region_init_io(&s->iomem_reg, obj, &cframes_bcast_reg_reg_ops, s, |
| 756 | TYPE_XLNX_VERSAL_CFRAME_BCAST_REG, KEYHOLE_STREAM_4K); |
| 757 | memory_region_init_io(&s->iomem_fdri, obj, &cframes_bcast_reg_fdri_ops, s, |
| 758 | TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "-fdri", |
| 759 | KEYHOLE_STREAM_4K); |
| 760 | sysbus_init_mmio(sbd, &s->iomem_reg); |
| 761 | sysbus_init_mmio(sbd, &s->iomem_fdri); |
| 762 | } |
| 763 | |
| 764 | static void cframe_bcast_reg_reset_enter(Object *obj, ResetType type) |
| 765 | { |
| 766 | XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(obj); |
| 767 | |
| 768 | memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t)); |
| 769 | } |
| 770 | |
| 771 | static const VMStateDescription vmstate_cframe_bcast_reg = { |
| 772 | .name = TYPE_XLNX_VERSAL_CFRAME_BCAST_REG, |
| 773 | .version_id = 1, |
| 774 | .minimum_version_id = 1, |
| 775 | .fields = (const VMStateField[]) { |
| 776 | VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFrameBcastReg, 4), |
| 777 | VMSTATE_END_OF_LIST(), |
| 778 | } |
| 779 | }; |
| 780 | |
| 781 | static const Property cframe_bcast_regs_props[] = { |
| 782 | DEFINE_PROP_LINK("cframe0", XlnxVersalCFrameBcastReg, cfg.cframe[0], |
| 783 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 784 | DEFINE_PROP_LINK("cframe1", XlnxVersalCFrameBcastReg, cfg.cframe[1], |
| 785 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 786 | DEFINE_PROP_LINK("cframe2", XlnxVersalCFrameBcastReg, cfg.cframe[2], |
| 787 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 788 | DEFINE_PROP_LINK("cframe3", XlnxVersalCFrameBcastReg, cfg.cframe[3], |
| 789 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 790 | DEFINE_PROP_LINK("cframe4", XlnxVersalCFrameBcastReg, cfg.cframe[4], |
| 791 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 792 | DEFINE_PROP_LINK("cframe5", XlnxVersalCFrameBcastReg, cfg.cframe[5], |
| 793 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 794 | DEFINE_PROP_LINK("cframe6", XlnxVersalCFrameBcastReg, cfg.cframe[6], |
| 795 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 796 | DEFINE_PROP_LINK("cframe7", XlnxVersalCFrameBcastReg, cfg.cframe[7], |
| 797 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 798 | DEFINE_PROP_LINK("cframe8", XlnxVersalCFrameBcastReg, cfg.cframe[8], |
| 799 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 800 | DEFINE_PROP_LINK("cframe9", XlnxVersalCFrameBcastReg, cfg.cframe[9], |
| 801 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 802 | DEFINE_PROP_LINK("cframe10", XlnxVersalCFrameBcastReg, cfg.cframe[10], |
| 803 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 804 | DEFINE_PROP_LINK("cframe11", XlnxVersalCFrameBcastReg, cfg.cframe[11], |
| 805 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 806 | DEFINE_PROP_LINK("cframe12", XlnxVersalCFrameBcastReg, cfg.cframe[12], |
| 807 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 808 | DEFINE_PROP_LINK("cframe13", XlnxVersalCFrameBcastReg, cfg.cframe[13], |
| 809 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 810 | DEFINE_PROP_LINK("cframe14", XlnxVersalCFrameBcastReg, cfg.cframe[14], |
| 811 | TYPE_XLNX_CFI_IF, XlnxCfiIf *), |
| 812 | }; |
| 813 | |
| 814 | static void cframe_reg_class_init(ObjectClass *klass, const void *data) |
| 815 | { |
| 816 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 817 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 818 | XlnxCfiIfClass *xcic = XLNX_CFI_IF_CLASS(klass); |
| 819 | |
| 820 | dc->vmsd = &vmstate_cframe_reg; |
| 821 | dc->realize = cframe_reg_realize; |
| 822 | rc->phases.enter = cframe_reg_reset_enter; |
| 823 | rc->phases.hold = cframe_reg_reset_hold; |
| 824 | device_class_set_props(dc, cframe_regs_props); |
| 825 | xcic->cfi_transfer_packet = cframe_reg_cfi_transfer_packet; |
| 826 | } |
| 827 | |
| 828 | static void cframe_bcast_reg_class_init(ObjectClass *klass, const void *data) |
| 829 | { |
| 830 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 831 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 832 | |
| 833 | dc->vmsd = &vmstate_cframe_bcast_reg; |
| 834 | device_class_set_props(dc, cframe_bcast_regs_props); |
| 835 | rc->phases.enter = cframe_bcast_reg_reset_enter; |
| 836 | } |
| 837 | |
| 838 | static const TypeInfo cframe_reg_info = { |
| 839 | .name = TYPE_XLNX_VERSAL_CFRAME_REG, |
| 840 | .parent = TYPE_SYS_BUS_DEVICE, |
| 841 | .instance_size = sizeof(XlnxVersalCFrameReg), |
| 842 | .class_init = cframe_reg_class_init, |
| 843 | .instance_init = cframe_reg_init, |
| 844 | .instance_finalize = cframe_reg_finalize, |
| 845 | .interfaces = (const InterfaceInfo[]) { |
| 846 | { TYPE_XLNX_CFI_IF }, |
| 847 | { } |
| 848 | } |
| 849 | }; |
| 850 | |
| 851 | static const TypeInfo cframe_bcast_reg_info = { |
| 852 | .name = TYPE_XLNX_VERSAL_CFRAME_BCAST_REG, |
| 853 | .parent = TYPE_SYS_BUS_DEVICE, |
| 854 | .instance_size = sizeof(XlnxVersalCFrameBcastReg), |
| 855 | .class_init = cframe_bcast_reg_class_init, |
| 856 | .instance_init = cframe_bcast_reg_init, |
| 857 | }; |
| 858 | |
| 859 | static void cframe_reg_register_types(void) |
| 860 | { |
| 861 | type_register_static(&cframe_reg_info); |
| 862 | type_register_static(&cframe_bcast_reg_info); |
| 863 | } |
| 864 | |
| 865 | type_init(cframe_reg_register_types) |