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1 /*
2 * QEMU model of the Clock-Reset-LPD (CRL).
3 *
4 * Copyright (c) 2022-2025 Advanced Micro Devices, Inc.
5 * SPDX-License-Identifier: GPL-2.0-or-later
6 *
7 * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
8 */
9
10 #include "qemu/osdep.h"
11 #include "migration/vmstate.h"
12 #include "hw/core/qdev-properties.h"
13 #include "hw/core/sysbus.h"
14 #include "hw/core/irq.h"
15 #include "hw/core/register.h"
16 #include "hw/core/resettable.h"
17
18 #include "target/arm/arm-powerctl.h"
19 #include "target/arm/multiprocessing.h"
20 #include "hw/misc/xlnx-versal-crl.h"
21
22 #ifndef XLNX_VERSAL_CRL_ERR_DEBUG
23 #define XLNX_VERSAL_CRL_ERR_DEBUG 0
24 #endif
25
26 static void crl_update_irq(XlnxVersalCRL *s)
27 {
28 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
29 qemu_set_irq(s->irq, pending);
30 }
31
32 static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
33 {
34 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
35 crl_update_irq(s);
36 }
37
38 static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
39 {
40 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
41 uint32_t val = val64;
42
43 s->regs[R_IR_MASK] &= ~val;
44 crl_update_irq(s);
45 return 0;
46 }
47
48 static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
49 {
50 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
51 uint32_t val = val64;
52
53 s->regs[R_IR_MASK] |= val;
54 crl_update_irq(s);
55 return 0;
56 }
57
58 static DeviceState **versal_decode_periph_rst(XlnxVersalCRLBase *s,
59 hwaddr addr, size_t *count)
60 {
61 size_t idx;
62 XlnxVersalCRL *xvc = XLNX_VERSAL_CRL(s);
63
64 *count = 1;
65
66 switch (addr) {
67 case A_RST_CPU_R5:
68 return xvc->cfg.rpu;
69
70 case A_RST_ADMA:
71 /* A single register fans out to all DMA reset inputs */
72 *count = ARRAY_SIZE(xvc->cfg.adma);
73 return xvc->cfg.adma;
74
75 case A_RST_UART0 ... A_RST_UART1:
76 idx = (addr - A_RST_UART0) / sizeof(uint32_t);
77 return xvc->cfg.uart + idx;
78
79 case A_RST_GEM0 ... A_RST_GEM1:
80 idx = (addr - A_RST_GEM0) / sizeof(uint32_t);
81 return xvc->cfg.gem + idx;
82
83 case A_RST_USB0:
84 return xvc->cfg.usb;
85
86 default:
87 /* invalid or unimplemented */
88 g_assert_not_reached();
89 }
90 }
91
92 static DeviceState **versal2_decode_periph_rst(XlnxVersalCRLBase *s,
93 hwaddr addr, size_t *count)
94 {
95 size_t idx;
96 XlnxVersal2CRL *xvc = XLNX_VERSAL2_CRL(s);
97
98 *count = 1;
99
100 switch (addr) {
101 case A_VERSAL2_RST_RPU_A ... A_VERSAL2_RST_RPU_E:
102 idx = (addr - A_VERSAL2_RST_RPU_A) / sizeof(uint32_t);
103 idx *= 2; /* two RPUs per RST_RPU_x registers */
104 return xvc->cfg.rpu + idx;
105
106 case A_VERSAL2_RST_ADMA:
107 /* A single register fans out to all DMA reset inputs */
108 *count = ARRAY_SIZE(xvc->cfg.adma);
109 return xvc->cfg.adma;
110
111 case A_VERSAL2_RST_SDMA:
112 *count = ARRAY_SIZE(xvc->cfg.sdma);
113 return xvc->cfg.sdma;
114
115 case A_VERSAL2_RST_UART0 ... A_VERSAL2_RST_UART1:
116 idx = (addr - A_VERSAL2_RST_UART0) / sizeof(uint32_t);
117 return xvc->cfg.uart + idx;
118
119 case A_VERSAL2_RST_GEM0 ... A_VERSAL2_RST_GEM1:
120 idx = (addr - A_VERSAL2_RST_GEM0) / sizeof(uint32_t);
121 return xvc->cfg.gem + idx;
122
123 case A_VERSAL2_RST_USB0 ... A_VERSAL2_RST_USB1:
124 idx = (addr - A_VERSAL2_RST_USB0) / sizeof(uint32_t);
125 return xvc->cfg.usb + idx;
126
127 case A_VERSAL2_RST_CAN0 ... A_VERSAL2_RST_CAN3:
128 idx = (addr - A_VERSAL2_RST_CAN0) / sizeof(uint32_t);
129 return xvc->cfg.can + idx;
130
131 default:
132 /* invalid or unimplemented */
133 return NULL;
134 }
135 }
136
137 static uint64_t crl_rst_cpu_prew(RegisterInfo *reg, uint64_t val64)
138 {
139 XlnxVersalCRLBase *s = XLNX_VERSAL_CRL_BASE(reg->opaque);
140 XlnxVersalCRLBaseClass *xvcbc = XLNX_VERSAL_CRL_BASE_GET_CLASS(s);
141 DeviceState **dev;
142 size_t i, count;
143
144 dev = xvcbc->decode_periph_rst(s, reg->access->addr, &count);
145
146 for (i = 0; i < 2; i++) {
147 bool prev, new;
148 uint64_t aff;
149
150 prev = extract32(s->regs[reg->access->addr / 4], i, 1);
151 new = extract32(val64, i, 1);
152
153 if (prev == new) {
154 continue;
155 }
156
157 aff = arm_cpu_mp_affinity(ARM_CPU(dev[i]));
158
159 if (new) {
160 arm_set_cpu_off(aff);
161 } else {
162 arm_set_cpu_on_and_reset(aff);
163 }
164 }
165
166 return val64;
167 }
168
169 static uint64_t crl_rst_dev_prew(RegisterInfo *reg, uint64_t val64)
170 {
171 XlnxVersalCRLBase *s = XLNX_VERSAL_CRL_BASE(reg->opaque);
172 XlnxVersalCRLBaseClass *xvcbc = XLNX_VERSAL_CRL_BASE_GET_CLASS(s);
173 DeviceState **dev;
174 bool prev, new;
175 size_t i, count;
176
177 dev = xvcbc->decode_periph_rst(s, reg->access->addr, &count);
178
179 if (dev == NULL) {
180 return val64;
181 }
182
183 prev = s->regs[reg->access->addr / 4] & 0x1;
184 new = val64 & 0x1;
185
186 if (prev == new) {
187 return val64;
188 }
189
190 for (i = 0; i < count; i++) {
191 if (dev[i]) {
192 device_cold_reset(dev[i]);
193 }
194 }
195
196 return val64;
197 }
198
199 static const RegisterAccessInfo crl_regs_info[] = {
200 { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
201 },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
202 .w1c = 0x1,
203 .post_write = crl_status_postw,
204 },{ .name = "IR_MASK", .addr = A_IR_MASK,
205 .reset = 0x1,
206 .ro = 0x1,
207 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
208 .pre_write = crl_enable_prew,
209 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
210 .pre_write = crl_disable_prew,
211 },{ .name = "WPROT", .addr = A_WPROT,
212 },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN,
213 .reset = 0x1,
214 .rsvd = 0xe,
215 },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL,
216 .reset = 0x24809,
217 .rsvd = 0xf88c00f6,
218 },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG,
219 .reset = 0x2000000,
220 .rsvd = 0x1801210,
221 },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG,
222 .rsvd = 0x7e330000,
223 },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
224 .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
225 R_PLL_STATUS_RPLL_LOCK_MASK,
226 .rsvd = 0xfa,
227 .ro = 0x5,
228 },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL,
229 .reset = 0x2000100,
230 .rsvd = 0xfdfc00ff,
231 },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL,
232 .reset = 0x6000300,
233 .rsvd = 0xf9fc00f8,
234 },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL,
235 .reset = 0x2000800,
236 .rsvd = 0xfdfc00f8,
237 },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL,
238 .reset = 0xe000300,
239 .rsvd = 0xe1fc00f8,
240 },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL,
241 .reset = 0x2000500,
242 .rsvd = 0xfdfc00f8,
243 },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL,
244 .reset = 0xe000a00,
245 .rsvd = 0xf1fc00f8,
246 },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL,
247 .reset = 0xe000a00,
248 .rsvd = 0xf1fc00f8,
249 },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL,
250 .reset = 0x300,
251 .rsvd = 0xfdfc00f8,
252 },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL,
253 .reset = 0x2001900,
254 .rsvd = 0xfdfc00f8,
255 },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL,
256 .reset = 0xc00,
257 .rsvd = 0xfdfc00f8,
258 },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL,
259 .reset = 0xc00,
260 .rsvd = 0xfdfc00f8,
261 },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL,
262 .reset = 0x600,
263 .rsvd = 0xfdfc00f8,
264 },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL,
265 .reset = 0x600,
266 .rsvd = 0xfdfc00f8,
267 },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL,
268 .reset = 0xc00,
269 .rsvd = 0xfdfc00f8,
270 },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL,
271 .reset = 0xc00,
272 .rsvd = 0xfdfc00f8,
273 },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL,
274 .reset = 0xc00,
275 .rsvd = 0xfdfc00f8,
276 },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL,
277 .reset = 0xc00,
278 .rsvd = 0xfdfc00f8,
279 },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL,
280 .reset = 0x300,
281 .rsvd = 0xfdfc00f8,
282 },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL,
283 .reset = 0x2000c00,
284 .rsvd = 0xfdfc00f8,
285 },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK,
286 },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL,
287 .reset = 0xf04,
288 .rsvd = 0xfffc00f8,
289 },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
290 .reset = 0x300,
291 .rsvd = 0xfdfc00f8,
292 },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL,
293 .reset = 0x300,
294 .rsvd = 0xfdfc00f8,
295 },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL,
296 .reset = 0x3c00,
297 .rsvd = 0xfdfc00f8,
298 },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5,
299 .reset = 0x17,
300 .rsvd = 0x8,
301 .pre_write = crl_rst_cpu_prew,
302 },{ .name = "RST_ADMA", .addr = A_RST_ADMA,
303 .reset = 0x1,
304 .pre_write = crl_rst_dev_prew,
305 },{ .name = "RST_GEM0", .addr = A_RST_GEM0,
306 .reset = 0x1,
307 .pre_write = crl_rst_dev_prew,
308 },{ .name = "RST_GEM1", .addr = A_RST_GEM1,
309 .reset = 0x1,
310 .pre_write = crl_rst_dev_prew,
311 },{ .name = "RST_SPARE", .addr = A_RST_SPARE,
312 .reset = 0x1,
313 },{ .name = "RST_USB0", .addr = A_RST_USB0,
314 .reset = 0x1,
315 .pre_write = crl_rst_dev_prew,
316 },{ .name = "RST_UART0", .addr = A_RST_UART0,
317 .reset = 0x1,
318 .pre_write = crl_rst_dev_prew,
319 },{ .name = "RST_UART1", .addr = A_RST_UART1,
320 .reset = 0x1,
321 .pre_write = crl_rst_dev_prew,
322 },{ .name = "RST_SPI0", .addr = A_RST_SPI0,
323 .reset = 0x1,
324 },{ .name = "RST_SPI1", .addr = A_RST_SPI1,
325 .reset = 0x1,
326 },{ .name = "RST_CAN0", .addr = A_RST_CAN0,
327 .reset = 0x1,
328 },{ .name = "RST_CAN1", .addr = A_RST_CAN1,
329 .reset = 0x1,
330 },{ .name = "RST_I2C0", .addr = A_RST_I2C0,
331 .reset = 0x1,
332 },{ .name = "RST_I2C1", .addr = A_RST_I2C1,
333 .reset = 0x1,
334 },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD,
335 .reset = 0x33,
336 .rsvd = 0xcc,
337 },{ .name = "RST_GPIO", .addr = A_RST_GPIO,
338 .reset = 0x1,
339 },{ .name = "RST_TTC", .addr = A_RST_TTC,
340 .reset = 0xf,
341 },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP,
342 .reset = 0x1,
343 },{ .name = "RST_SWDT", .addr = A_RST_SWDT,
344 .reset = 0x1,
345 },{ .name = "RST_OCM", .addr = A_RST_OCM,
346 },{ .name = "RST_IPI", .addr = A_RST_IPI,
347 },{ .name = "RST_FPD", .addr = A_RST_FPD,
348 .reset = 0x3,
349 },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE,
350 .reset = 0x1,
351 .rsvd = 0xf8,
352 }
353 };
354
355 static const RegisterAccessInfo versal2_crl_regs_info[] = {
356 { .name = "ERR_CTRL", .addr = A_VERSAL2_ERR_CTRL,
357 .reset = 0x1,
358 },{ .name = "WPROT", .addr = A_VERSAL2_WPROT,
359 },{ .name = "RPLL_CTRL", .addr = A_VERSAL2_RPLL_CTRL,
360 .reset = 0x24809,
361 .rsvd = 0xf88c00f6,
362 },{ .name = "RPLL_CFG", .addr = A_VERSAL2_RPLL_CFG,
363 .reset = 0x7e5dcc6c,
364 .rsvd = 0x1801210,
365 },{ .name = "FLXPLL_CTRL", .addr = A_VERSAL2_FLXPLL_CTRL,
366 .reset = 0x24809,
367 .rsvd = 0xf88c00f6,
368 },{ .name = "FLXPLL_CFG", .addr = A_VERSAL2_FLXPLL_CFG,
369 .reset = 0x7e5dcc6c,
370 .rsvd = 0x1801210,
371 },{ .name = "PLL_STATUS", .addr = A_VERSAL2_PLL_STATUS,
372 .reset = 0xf,
373 .rsvd = 0xf0,
374 .ro = 0xf,
375 },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_VERSAL2_RPLL_TO_XPD_CTRL,
376 .reset = 0x2000100,
377 .rsvd = 0xfdfc00ff,
378 },{ .name = "LPX_TOP_SWITCH_CTRL", .addr = A_VERSAL2_LPX_TOP_SWITCH_CTRL,
379 .reset = 0xe000300,
380 .rsvd = 0xf1fc00f8,
381 },{ .name = "LPX_LSBUS_CLK_CTRL", .addr = A_VERSAL2_LPX_LSBUS_CLK_CTRL,
382 .reset = 0x2000800,
383 .rsvd = 0xfdfc00f8,
384 },{ .name = "RPU_CLK_CTRL", .addr = A_VERSAL2_RPU_CLK_CTRL,
385 .reset = 0x3f00300,
386 .rsvd = 0xfc0c00f8,
387 },{ .name = "OCM_CLK_CTRL", .addr = A_VERSAL2_OCM_CLK_CTRL,
388 .reset = 0x1e00000,
389 .rsvd = 0xfe1fffff,
390 },{ .name = "IOU_SWITCH_CLK_CTRL", .addr = A_VERSAL2_IOU_SWITCH_CLK_CTRL,
391 .reset = 0x2000500,
392 .rsvd = 0xfdfc00f8,
393 },{ .name = "GEM0_REF_CTRL", .addr = A_VERSAL2_GEM0_REF_CTRL,
394 .reset = 0xe000a00,
395 .rsvd = 0xf1fc00f8,
396 },{ .name = "GEM1_REF_CTRL", .addr = A_VERSAL2_GEM1_REF_CTRL,
397 .reset = 0xe000a00,
398 .rsvd = 0xf1fc00f8,
399 },{ .name = "GEM_TSU_REF_CLK_CTRL", .addr = A_VERSAL2_GEM_TSU_REF_CLK_CTRL,
400 .reset = 0x300,
401 .rsvd = 0xfdfc00f8,
402 },{ .name = "USB0_BUS_REF_CLK_CTRL",
403 .addr = A_VERSAL2_USB0_BUS_REF_CLK_CTRL,
404 .reset = 0x2001900,
405 .rsvd = 0xfdfc00f8,
406 },{ .name = "USB1_BUS_REF_CLK_CTRL",
407 .addr = A_VERSAL2_USB1_BUS_REF_CLK_CTRL,
408 .reset = 0x2001900,
409 .rsvd = 0xfdfc00f8,
410 },{ .name = "UART0_REF_CLK_CTRL", .addr = A_VERSAL2_UART0_REF_CLK_CTRL,
411 .reset = 0xc00,
412 .rsvd = 0xfdfc00f8,
413 },{ .name = "UART1_REF_CLK_CTRL", .addr = A_VERSAL2_UART1_REF_CLK_CTRL,
414 .reset = 0xc00,
415 .rsvd = 0xfdfc00f8,
416 },{ .name = "SPI0_REF_CLK_CTRL", .addr = A_VERSAL2_SPI0_REF_CLK_CTRL,
417 .reset = 0x600,
418 .rsvd = 0xfdfc00f8,
419 },{ .name = "SPI1_REF_CLK_CTRL", .addr = A_VERSAL2_SPI1_REF_CLK_CTRL,
420 .reset = 0x600,
421 .rsvd = 0xfdfc00f8,
422 },{ .name = "CAN0_REF_2X_CTRL", .addr = A_VERSAL2_CAN0_REF_2X_CTRL,
423 .reset = 0xc00,
424 .rsvd = 0xfdfc00f8,
425 },{ .name = "CAN1_REF_2X_CTRL", .addr = A_VERSAL2_CAN1_REF_2X_CTRL,
426 .reset = 0xc00,
427 .rsvd = 0xfdfc00f8,
428 },{ .name = "CAN2_REF_2X_CTRL", .addr = A_VERSAL2_CAN2_REF_2X_CTRL,
429 .reset = 0xc00,
430 .rsvd = 0xfdfc00f8,
431 },{ .name = "CAN3_REF_2X_CTRL", .addr = A_VERSAL2_CAN3_REF_2X_CTRL,
432 .reset = 0xc00,
433 .rsvd = 0xfdfc00f8,
434 },{ .name = "I3C0_REF_CTRL", .addr = A_VERSAL2_I3C0_REF_CTRL,
435 .reset = 0x2000c00,
436 .rsvd = 0xfdfc00f8,
437 },{ .name = "I3C1_REF_CTRL", .addr = A_VERSAL2_I3C1_REF_CTRL,
438 .reset = 0x2000c00,
439 .rsvd = 0xfdfc00f8,
440 },{ .name = "I3C2_REF_CTRL", .addr = A_VERSAL2_I3C2_REF_CTRL,
441 .reset = 0x2000c00,
442 .rsvd = 0xfdfc00f8,
443 },{ .name = "I3C3_REF_CTRL", .addr = A_VERSAL2_I3C3_REF_CTRL,
444 .reset = 0x2000c00,
445 .rsvd = 0xfdfc00f8,
446 },{ .name = "I3C4_REF_CTRL", .addr = A_VERSAL2_I3C4_REF_CTRL,
447 .reset = 0x2000c00,
448 .rsvd = 0xfdfc00f8,
449 },{ .name = "I3C5_REF_CTRL", .addr = A_VERSAL2_I3C5_REF_CTRL,
450 .reset = 0x2000c00,
451 .rsvd = 0xfdfc00f8,
452 },{ .name = "I3C6_REF_CTRL", .addr = A_VERSAL2_I3C6_REF_CTRL,
453 .reset = 0x2000c00,
454 .rsvd = 0xfdfc00f8,
455 },{ .name = "I3C7_REF_CTRL", .addr = A_VERSAL2_I3C7_REF_CTRL,
456 .reset = 0x2000c00,
457 .rsvd = 0xfdfc00f8,
458 },{ .name = "DBG_LPX_CTRL", .addr = A_VERSAL2_DBG_LPX_CTRL,
459 .reset = 0x300,
460 .rsvd = 0xfdfc00f8,
461 },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_VERSAL2_TIMESTAMP_REF_CTRL,
462 .reset = 0x2000c00,
463 .rsvd = 0xfdfc00f8,
464 },{ .name = "SAFETY_CHK", .addr = A_VERSAL2_SAFETY_CHK,
465 },{ .name = "ASU_CLK_CTRL", .addr = A_VERSAL2_ASU_CLK_CTRL,
466 .reset = 0x2000f04,
467 .rsvd = 0xfdfc00f8,
468 },{ .name = "DBG_TSTMP_CLK_CTRL", .addr = A_VERSAL2_DBG_TSTMP_CLK_CTRL,
469 .reset = 0x300,
470 .rsvd = 0xfdfc00f8,
471 },{ .name = "MMI_TOPSW_CLK_CTRL", .addr = A_VERSAL2_MMI_TOPSW_CLK_CTRL,
472 .reset = 0x2000300,
473 .rsvd = 0xfdfc00f8,
474 },{ .name = "WWDT_PLL_CLK_CTRL", .addr = A_VERSAL2_WWDT_PLL_CLK_CTRL,
475 .reset = 0xc00,
476 .rsvd = 0xfffc00f8,
477 },{ .name = "RCLK_CTRL", .addr = A_VERSAL2_RCLK_CTRL,
478 .rsvd = 0xc040,
479 },{ .name = "RST_RPU_A", .addr = A_VERSAL2_RST_RPU_A,
480 .reset = 0x10303,
481 .rsvd = 0xfffefcfc,
482 .pre_write = crl_rst_cpu_prew,
483 },{ .name = "RST_RPU_B", .addr = A_VERSAL2_RST_RPU_B,
484 .reset = 0x10303,
485 .rsvd = 0xfffefcfc,
486 .pre_write = crl_rst_cpu_prew,
487 },{ .name = "RST_RPU_C", .addr = A_VERSAL2_RST_RPU_C,
488 .reset = 0x10303,
489 .rsvd = 0xfffefcfc,
490 .pre_write = crl_rst_cpu_prew,
491 },{ .name = "RST_RPU_D", .addr = A_VERSAL2_RST_RPU_D,
492 .reset = 0x10303,
493 .rsvd = 0xfffefcfc,
494 .pre_write = crl_rst_cpu_prew,
495 },{ .name = "RST_RPU_E", .addr = A_VERSAL2_RST_RPU_E,
496 .reset = 0x10303,
497 .rsvd = 0xfffefcfc,
498 .pre_write = crl_rst_cpu_prew,
499 },{ .name = "RST_RPU_GD_0", .addr = A_VERSAL2_RST_RPU_GD_0,
500 .reset = 0x3,
501 },{ .name = "RST_RPU_GD_1", .addr = A_VERSAL2_RST_RPU_GD_1,
502 .reset = 0x3,
503 },{ .name = "RST_ASU_GD", .addr = A_VERSAL2_RST_ASU_GD,
504 .reset = 0x3,
505 },{ .name = "RST_ADMA", .addr = A_VERSAL2_RST_ADMA,
506 .reset = 0x1,
507 .pre_write = crl_rst_dev_prew,
508 },{ .name = "RST_SDMA", .addr = A_VERSAL2_RST_SDMA,
509 .pre_write = crl_rst_dev_prew,
510 .reset = 0x1,
511 },{ .name = "RST_GEM0", .addr = A_VERSAL2_RST_GEM0,
512 .reset = 0x1,
513 .pre_write = crl_rst_dev_prew,
514 },{ .name = "RST_GEM1", .addr = A_VERSAL2_RST_GEM1,
515 .reset = 0x1,
516 .pre_write = crl_rst_dev_prew,
517 },{ .name = "RST_USB0", .addr = A_VERSAL2_RST_USB0,
518 .reset = 0x1,
519 .pre_write = crl_rst_dev_prew,
520 },{ .name = "RST_USB1", .addr = A_VERSAL2_RST_USB1,
521 .reset = 0x1,
522 .pre_write = crl_rst_dev_prew,
523 },{ .name = "RST_UART0", .addr = A_VERSAL2_RST_UART0,
524 .reset = 0x1,
525 .pre_write = crl_rst_dev_prew,
526 },{ .name = "RST_UART1", .addr = A_VERSAL2_RST_UART1,
527 .reset = 0x1,
528 .pre_write = crl_rst_dev_prew,
529 },{ .name = "RST_SPI0", .addr = A_VERSAL2_RST_SPI0,
530 .reset = 0x1,
531 },{ .name = "RST_SPI1", .addr = A_VERSAL2_RST_SPI1,
532 .reset = 0x1,
533 },{ .name = "RST_CAN0", .addr = A_VERSAL2_RST_CAN0,
534 .reset = 0x1,
535 .pre_write = crl_rst_dev_prew,
536 },{ .name = "RST_CAN1", .addr = A_VERSAL2_RST_CAN1,
537 .reset = 0x1,
538 .pre_write = crl_rst_dev_prew,
539 },{ .name = "RST_CAN2", .addr = A_VERSAL2_RST_CAN2,
540 .reset = 0x1,
541 .pre_write = crl_rst_dev_prew,
542 },{ .name = "RST_CAN3", .addr = A_VERSAL2_RST_CAN3,
543 .reset = 0x1,
544 .pre_write = crl_rst_dev_prew,
545 },{ .name = "RST_I3C0", .addr = A_VERSAL2_RST_I3C0,
546 .reset = 0x1,
547 },{ .name = "RST_I3C1", .addr = A_VERSAL2_RST_I3C1,
548 .reset = 0x1,
549 },{ .name = "RST_I3C2", .addr = A_VERSAL2_RST_I3C2,
550 .reset = 0x1,
551 },{ .name = "RST_I3C3", .addr = A_VERSAL2_RST_I3C3,
552 .reset = 0x1,
553 },{ .name = "RST_I3C4", .addr = A_VERSAL2_RST_I3C4,
554 .reset = 0x1,
555 },{ .name = "RST_I3C5", .addr = A_VERSAL2_RST_I3C5,
556 .reset = 0x1,
557 },{ .name = "RST_I3C6", .addr = A_VERSAL2_RST_I3C6,
558 .reset = 0x1,
559 },{ .name = "RST_I3C7", .addr = A_VERSAL2_RST_I3C7,
560 .reset = 0x1,
561 },{ .name = "RST_DBG_LPX", .addr = A_VERSAL2_RST_DBG_LPX,
562 .reset = 0x3,
563 .rsvd = 0xfc,
564 },{ .name = "RST_GPIO", .addr = A_VERSAL2_RST_GPIO,
565 .reset = 0x1,
566 },{ .name = "RST_TTC", .addr = A_VERSAL2_RST_TTC,
567 .reset = 0xff,
568 },{ .name = "RST_TIMESTAMP", .addr = A_VERSAL2_RST_TIMESTAMP,
569 .reset = 0x1,
570 },{ .name = "RST_SWDT0", .addr = A_VERSAL2_RST_SWDT0,
571 .reset = 0x1,
572 },{ .name = "RST_SWDT1", .addr = A_VERSAL2_RST_SWDT1,
573 .reset = 0x1,
574 },{ .name = "RST_SWDT2", .addr = A_VERSAL2_RST_SWDT2,
575 .reset = 0x1,
576 },{ .name = "RST_SWDT3", .addr = A_VERSAL2_RST_SWDT3,
577 .reset = 0x1,
578 },{ .name = "RST_SWDT4", .addr = A_VERSAL2_RST_SWDT4,
579 .reset = 0x1,
580 },{ .name = "RST_IPI", .addr = A_VERSAL2_RST_IPI,
581 },{ .name = "RST_SYSMON", .addr = A_VERSAL2_RST_SYSMON,
582 },{ .name = "ASU_MB_RST_MODE", .addr = A_VERSAL2_ASU_MB_RST_MODE,
583 .reset = 0x1,
584 .rsvd = 0xf8,
585 },{ .name = "FPX_TOPSW_MUX_CTRL", .addr = A_VERSAL2_FPX_TOPSW_MUX_CTRL,
586 .reset = 0x1,
587 },{ .name = "RST_FPX", .addr = A_VERSAL2_RST_FPX,
588 .reset = 0x3,
589 },{ .name = "RST_MMI", .addr = A_VERSAL2_RST_MMI,
590 .reset = 0x1,
591 },{ .name = "RST_OCM", .addr = A_VERSAL2_RST_OCM,
592 }
593 };
594
595 static void versal_crl_reset_enter(Object *obj, ResetType type)
596 {
597 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
598 unsigned int i;
599
600 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
601 register_reset(&s->regs_info[i]);
602 }
603 }
604
605 static void versal2_crl_reset_enter(Object *obj, ResetType type)
606 {
607 XlnxVersal2CRL *s = XLNX_VERSAL2_CRL(obj);
608 size_t i;
609
610 for (i = 0; i < VERSAL2_CRL_R_MAX; ++i) {
611 register_reset(&s->regs_info[i]);
612 }
613 }
614
615 static void versal_crl_reset_hold(Object *obj, ResetType type)
616 {
617 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
618
619 crl_update_irq(s);
620 }
621
622 static const MemoryRegionOps crl_ops = {
623 .read = register_read_memory,
624 .write = register_write_memory,
625 .endianness = DEVICE_LITTLE_ENDIAN,
626 .valid = {
627 .min_access_size = 4,
628 .max_access_size = 4,
629 },
630 };
631
632 static void versal_crl_init(Object *obj)
633 {
634 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
635 XlnxVersalCRLBase *xvcb = XLNX_VERSAL_CRL_BASE(obj);
636 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
637 RegisterInfoArray *reg_array;
638 int i;
639
640 reg_array = register_init_block32(DEVICE(obj), crl_regs_info,
641 ARRAY_SIZE(crl_regs_info),
642 s->regs_info, s->regs,
643 &crl_ops,
644 XLNX_VERSAL_CRL_ERR_DEBUG,
645 CRL_R_MAX * 4);
646 xvcb->regs = s->regs;
647 sysbus_init_mmio(sbd, &reg_array->mem);
648 sysbus_init_irq(sbd, &s->irq);
649
650 for (i = 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) {
651 object_property_add_link(obj, "rpu[*]", TYPE_ARM_CPU,
652 (Object **)&s->cfg.rpu[i],
653 qdev_prop_allow_set_link_before_realize,
654 OBJ_PROP_LINK_STRONG);
655 }
656
657 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
658 object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
659 (Object **)&s->cfg.adma[i],
660 qdev_prop_allow_set_link_before_realize,
661 OBJ_PROP_LINK_STRONG);
662 }
663
664 for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
665 object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
666 (Object **)&s->cfg.uart[i],
667 qdev_prop_allow_set_link_before_realize,
668 OBJ_PROP_LINK_STRONG);
669 }
670
671 for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
672 object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
673 (Object **)&s->cfg.gem[i],
674 qdev_prop_allow_set_link_before_realize,
675 OBJ_PROP_LINK_STRONG);
676 }
677
678 for (i = 0; i < ARRAY_SIZE(s->cfg.usb); ++i) {
679 object_property_add_link(obj, "usb[*]", TYPE_DEVICE,
680 (Object **)&s->cfg.usb[i],
681 qdev_prop_allow_set_link_before_realize,
682 OBJ_PROP_LINK_STRONG);
683 }
684 }
685
686 static void versal2_crl_init(Object *obj)
687 {
688 XlnxVersal2CRL *s = XLNX_VERSAL2_CRL(obj);
689 XlnxVersalCRLBase *xvcb = XLNX_VERSAL_CRL_BASE(obj);
690 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
691 RegisterInfoArray *reg_array;
692 size_t i;
693
694 reg_array = register_init_block32(DEVICE(obj), versal2_crl_regs_info,
695 ARRAY_SIZE(versal2_crl_regs_info),
696 s->regs_info, s->regs,
697 &crl_ops,
698 XLNX_VERSAL_CRL_ERR_DEBUG,
699 VERSAL2_CRL_R_MAX * 4);
700 xvcb->regs = s->regs;
701
702 sysbus_init_mmio(sbd, &reg_array->mem);
703
704 for (i = 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) {
705 object_property_add_link(obj, "rpu[*]", TYPE_ARM_CPU,
706 (Object **)&s->cfg.rpu[i],
707 qdev_prop_allow_set_link_before_realize,
708 OBJ_PROP_LINK_STRONG);
709 }
710
711 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
712 object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
713 (Object **)&s->cfg.adma[i],
714 qdev_prop_allow_set_link_before_realize,
715 OBJ_PROP_LINK_STRONG);
716 }
717
718 for (i = 0; i < ARRAY_SIZE(s->cfg.sdma); ++i) {
719 object_property_add_link(obj, "sdma[*]", TYPE_DEVICE,
720 (Object **)&s->cfg.sdma[i],
721 qdev_prop_allow_set_link_before_realize,
722 OBJ_PROP_LINK_STRONG);
723 }
724
725 for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
726 object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
727 (Object **)&s->cfg.uart[i],
728 qdev_prop_allow_set_link_before_realize,
729 OBJ_PROP_LINK_STRONG);
730 }
731
732 for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
733 object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
734 (Object **)&s->cfg.gem[i],
735 qdev_prop_allow_set_link_before_realize,
736 OBJ_PROP_LINK_STRONG);
737 }
738
739 for (i = 0; i < ARRAY_SIZE(s->cfg.usb); ++i) {
740 object_property_add_link(obj, "usb[*]", TYPE_DEVICE,
741 (Object **)&s->cfg.usb[i],
742 qdev_prop_allow_set_link_before_realize,
743 OBJ_PROP_LINK_STRONG);
744 }
745
746 for (i = 0; i < ARRAY_SIZE(s->cfg.can); ++i) {
747 object_property_add_link(obj, "can[*]", TYPE_DEVICE,
748 (Object **)&s->cfg.can[i],
749 qdev_prop_allow_set_link_before_realize,
750 OBJ_PROP_LINK_STRONG);
751 }
752 }
753
754 static const VMStateDescription vmstate_versal_crl = {
755 .name = TYPE_XLNX_VERSAL_CRL,
756 .version_id = 1,
757 .minimum_version_id = 1,
758 .fields = (const VMStateField[]) {
759 VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
760 VMSTATE_END_OF_LIST(),
761 }
762 };
763
764 static const VMStateDescription vmstate_versal2_crl = {
765 .name = TYPE_XLNX_VERSAL2_CRL,
766 .version_id = 1,
767 .minimum_version_id = 1,
768 .fields = (const VMStateField[]) {
769 VMSTATE_UINT32_ARRAY(regs, XlnxVersal2CRL, VERSAL2_CRL_R_MAX),
770 VMSTATE_END_OF_LIST(),
771 }
772 };
773
774 static void versal_crl_class_init(ObjectClass *klass, const void *data)
775 {
776 DeviceClass *dc = DEVICE_CLASS(klass);
777 XlnxVersalCRLBaseClass *xvcc = XLNX_VERSAL_CRL_BASE_CLASS(klass);
778 ResettableClass *rc = RESETTABLE_CLASS(klass);
779
780 dc->vmsd = &vmstate_versal_crl;
781 rc->phases.enter = versal_crl_reset_enter;
782 rc->phases.hold = versal_crl_reset_hold;
783 xvcc->decode_periph_rst = versal_decode_periph_rst;
784 }
785
786 static void versal2_crl_class_init(ObjectClass *klass, const void *data)
787 {
788 XlnxVersalCRLBaseClass *xvcc = XLNX_VERSAL_CRL_BASE_CLASS(klass);
789 DeviceClass *dc = DEVICE_CLASS(klass);
790 ResettableClass *rc = RESETTABLE_CLASS(klass);
791
792 dc->vmsd = &vmstate_versal2_crl;
793 rc->phases.enter = versal2_crl_reset_enter;
794 xvcc->decode_periph_rst = versal2_decode_periph_rst;
795 }
796
797 static const TypeInfo crl_base_info = {
798 .name = TYPE_XLNX_VERSAL_CRL_BASE,
799 .parent = TYPE_SYS_BUS_DEVICE,
800 .instance_size = sizeof(XlnxVersalCRLBase),
801 .class_size = sizeof(XlnxVersalCRLBaseClass),
802 .abstract = true,
803 };
804
805 static const TypeInfo versal_crl_info = {
806 .name = TYPE_XLNX_VERSAL_CRL,
807 .parent = TYPE_XLNX_VERSAL_CRL_BASE,
808 .instance_size = sizeof(XlnxVersalCRL),
809 .instance_init = versal_crl_init,
810 .class_init = versal_crl_class_init,
811 };
812
813 static const TypeInfo versal2_crl_info = {
814 .name = TYPE_XLNX_VERSAL2_CRL,
815 .parent = TYPE_XLNX_VERSAL_CRL_BASE,
816 .instance_size = sizeof(XlnxVersal2CRL),
817 .instance_init = versal2_crl_init,
818 .class_init = versal2_crl_class_init,
819 };
820
821 static void crl_register_types(void)
822 {
823 type_register_static(&crl_base_info);
824 type_register_static(&versal_crl_info);
825 type_register_static(&versal2_crl_info);
826 }
827
828 type_init(crl_register_types)