@samitouri / QOSamiQemu
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master
master
c 1,447 lines 53.1 KB
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1 /*
2 * QEMU model of Versal's PMC IOU SLCR (system level control registers)
3 *
4 * Copyright (c) 2021 Xilinx Inc.
5 * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/core/sysbus.h"
28 #include "hw/core/register.h"
29 #include "hw/core/irq.h"
30 #include "qemu/bitops.h"
31 #include "qemu/log.h"
32 #include "migration/vmstate.h"
33 #include "hw/core/qdev-properties.h"
34 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
35
36 #ifndef XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG
37 #define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0
38 #endif
39
40 REG32(MIO_PIN_0, 0x0)
41 FIELD(MIO_PIN_0, L3_SEL, 7, 3)
42 FIELD(MIO_PIN_0, L2_SEL, 5, 2)
43 FIELD(MIO_PIN_0, L1_SEL, 3, 2)
44 FIELD(MIO_PIN_0, L0_SEL, 1, 2)
45 REG32(MIO_PIN_1, 0x4)
46 FIELD(MIO_PIN_1, L3_SEL, 7, 3)
47 FIELD(MIO_PIN_1, L2_SEL, 5, 2)
48 FIELD(MIO_PIN_1, L1_SEL, 3, 2)
49 FIELD(MIO_PIN_1, L0_SEL, 1, 2)
50 REG32(MIO_PIN_2, 0x8)
51 FIELD(MIO_PIN_2, L3_SEL, 7, 3)
52 FIELD(MIO_PIN_2, L2_SEL, 5, 2)
53 FIELD(MIO_PIN_2, L1_SEL, 3, 2)
54 FIELD(MIO_PIN_2, L0_SEL, 1, 2)
55 REG32(MIO_PIN_3, 0xc)
56 FIELD(MIO_PIN_3, L3_SEL, 7, 3)
57 FIELD(MIO_PIN_3, L2_SEL, 5, 2)
58 FIELD(MIO_PIN_3, L1_SEL, 3, 2)
59 FIELD(MIO_PIN_3, L0_SEL, 1, 2)
60 REG32(MIO_PIN_4, 0x10)
61 FIELD(MIO_PIN_4, L3_SEL, 7, 3)
62 FIELD(MIO_PIN_4, L2_SEL, 5, 2)
63 FIELD(MIO_PIN_4, L1_SEL, 3, 2)
64 FIELD(MIO_PIN_4, L0_SEL, 1, 2)
65 REG32(MIO_PIN_5, 0x14)
66 FIELD(MIO_PIN_5, L3_SEL, 7, 3)
67 FIELD(MIO_PIN_5, L2_SEL, 5, 2)
68 FIELD(MIO_PIN_5, L1_SEL, 3, 2)
69 FIELD(MIO_PIN_5, L0_SEL, 1, 2)
70 REG32(MIO_PIN_6, 0x18)
71 FIELD(MIO_PIN_6, L3_SEL, 7, 3)
72 FIELD(MIO_PIN_6, L2_SEL, 5, 2)
73 FIELD(MIO_PIN_6, L1_SEL, 3, 2)
74 FIELD(MIO_PIN_6, L0_SEL, 1, 2)
75 REG32(MIO_PIN_7, 0x1c)
76 FIELD(MIO_PIN_7, L3_SEL, 7, 3)
77 FIELD(MIO_PIN_7, L2_SEL, 5, 2)
78 FIELD(MIO_PIN_7, L1_SEL, 3, 2)
79 FIELD(MIO_PIN_7, L0_SEL, 1, 2)
80 REG32(MIO_PIN_8, 0x20)
81 FIELD(MIO_PIN_8, L3_SEL, 7, 3)
82 FIELD(MIO_PIN_8, L2_SEL, 5, 2)
83 FIELD(MIO_PIN_8, L1_SEL, 3, 2)
84 FIELD(MIO_PIN_8, L0_SEL, 1, 2)
85 REG32(MIO_PIN_9, 0x24)
86 FIELD(MIO_PIN_9, L3_SEL, 7, 3)
87 FIELD(MIO_PIN_9, L2_SEL, 5, 2)
88 FIELD(MIO_PIN_9, L1_SEL, 3, 2)
89 FIELD(MIO_PIN_9, L0_SEL, 1, 2)
90 REG32(MIO_PIN_10, 0x28)
91 FIELD(MIO_PIN_10, L3_SEL, 7, 3)
92 FIELD(MIO_PIN_10, L2_SEL, 5, 2)
93 FIELD(MIO_PIN_10, L1_SEL, 3, 2)
94 FIELD(MIO_PIN_10, L0_SEL, 1, 2)
95 REG32(MIO_PIN_11, 0x2c)
96 FIELD(MIO_PIN_11, L3_SEL, 7, 3)
97 FIELD(MIO_PIN_11, L2_SEL, 5, 2)
98 FIELD(MIO_PIN_11, L1_SEL, 3, 2)
99 FIELD(MIO_PIN_11, L0_SEL, 1, 2)
100 REG32(MIO_PIN_12, 0x30)
101 FIELD(MIO_PIN_12, L3_SEL, 7, 3)
102 FIELD(MIO_PIN_12, L2_SEL, 5, 2)
103 FIELD(MIO_PIN_12, L1_SEL, 3, 2)
104 FIELD(MIO_PIN_12, L0_SEL, 1, 2)
105 REG32(MIO_PIN_13, 0x34)
106 FIELD(MIO_PIN_13, L3_SEL, 7, 3)
107 FIELD(MIO_PIN_13, L2_SEL, 5, 2)
108 FIELD(MIO_PIN_13, L1_SEL, 3, 2)
109 FIELD(MIO_PIN_13, L0_SEL, 1, 2)
110 REG32(MIO_PIN_14, 0x38)
111 FIELD(MIO_PIN_14, L3_SEL, 7, 3)
112 FIELD(MIO_PIN_14, L2_SEL, 5, 2)
113 FIELD(MIO_PIN_14, L1_SEL, 3, 2)
114 FIELD(MIO_PIN_14, L0_SEL, 1, 2)
115 REG32(MIO_PIN_15, 0x3c)
116 FIELD(MIO_PIN_15, L3_SEL, 7, 3)
117 FIELD(MIO_PIN_15, L2_SEL, 5, 2)
118 FIELD(MIO_PIN_15, L1_SEL, 3, 2)
119 FIELD(MIO_PIN_15, L0_SEL, 1, 2)
120 REG32(MIO_PIN_16, 0x40)
121 FIELD(MIO_PIN_16, L3_SEL, 7, 3)
122 FIELD(MIO_PIN_16, L2_SEL, 5, 2)
123 FIELD(MIO_PIN_16, L1_SEL, 3, 2)
124 FIELD(MIO_PIN_16, L0_SEL, 1, 2)
125 REG32(MIO_PIN_17, 0x44)
126 FIELD(MIO_PIN_17, L3_SEL, 7, 3)
127 FIELD(MIO_PIN_17, L2_SEL, 5, 2)
128 FIELD(MIO_PIN_17, L1_SEL, 3, 2)
129 FIELD(MIO_PIN_17, L0_SEL, 1, 2)
130 REG32(MIO_PIN_18, 0x48)
131 FIELD(MIO_PIN_18, L3_SEL, 7, 3)
132 FIELD(MIO_PIN_18, L2_SEL, 5, 2)
133 FIELD(MIO_PIN_18, L1_SEL, 3, 2)
134 FIELD(MIO_PIN_18, L0_SEL, 1, 2)
135 REG32(MIO_PIN_19, 0x4c)
136 FIELD(MIO_PIN_19, L3_SEL, 7, 3)
137 FIELD(MIO_PIN_19, L2_SEL, 5, 2)
138 FIELD(MIO_PIN_19, L1_SEL, 3, 2)
139 FIELD(MIO_PIN_19, L0_SEL, 1, 2)
140 REG32(MIO_PIN_20, 0x50)
141 FIELD(MIO_PIN_20, L3_SEL, 7, 3)
142 FIELD(MIO_PIN_20, L2_SEL, 5, 2)
143 FIELD(MIO_PIN_20, L1_SEL, 3, 2)
144 FIELD(MIO_PIN_20, L0_SEL, 1, 2)
145 REG32(MIO_PIN_21, 0x54)
146 FIELD(MIO_PIN_21, L3_SEL, 7, 3)
147 FIELD(MIO_PIN_21, L2_SEL, 5, 2)
148 FIELD(MIO_PIN_21, L1_SEL, 3, 2)
149 FIELD(MIO_PIN_21, L0_SEL, 1, 2)
150 REG32(MIO_PIN_22, 0x58)
151 FIELD(MIO_PIN_22, L3_SEL, 7, 3)
152 FIELD(MIO_PIN_22, L2_SEL, 5, 2)
153 FIELD(MIO_PIN_22, L1_SEL, 3, 2)
154 FIELD(MIO_PIN_22, L0_SEL, 1, 2)
155 REG32(MIO_PIN_23, 0x5c)
156 FIELD(MIO_PIN_23, L3_SEL, 7, 3)
157 FIELD(MIO_PIN_23, L2_SEL, 5, 2)
158 FIELD(MIO_PIN_23, L1_SEL, 3, 2)
159 FIELD(MIO_PIN_23, L0_SEL, 1, 2)
160 REG32(MIO_PIN_24, 0x60)
161 FIELD(MIO_PIN_24, L3_SEL, 7, 3)
162 FIELD(MIO_PIN_24, L2_SEL, 5, 2)
163 FIELD(MIO_PIN_24, L1_SEL, 3, 2)
164 FIELD(MIO_PIN_24, L0_SEL, 1, 2)
165 REG32(MIO_PIN_25, 0x64)
166 FIELD(MIO_PIN_25, L3_SEL, 7, 3)
167 FIELD(MIO_PIN_25, L2_SEL, 5, 2)
168 FIELD(MIO_PIN_25, L1_SEL, 3, 2)
169 FIELD(MIO_PIN_25, L0_SEL, 1, 2)
170 REG32(MIO_PIN_26, 0x68)
171 FIELD(MIO_PIN_26, L3_SEL, 7, 3)
172 FIELD(MIO_PIN_26, L2_SEL, 5, 2)
173 FIELD(MIO_PIN_26, L1_SEL, 3, 2)
174 FIELD(MIO_PIN_26, L0_SEL, 1, 2)
175 REG32(MIO_PIN_27, 0x6c)
176 FIELD(MIO_PIN_27, L3_SEL, 7, 3)
177 FIELD(MIO_PIN_27, L2_SEL, 5, 2)
178 FIELD(MIO_PIN_27, L1_SEL, 3, 2)
179 FIELD(MIO_PIN_27, L0_SEL, 1, 2)
180 REG32(MIO_PIN_28, 0x70)
181 FIELD(MIO_PIN_28, L3_SEL, 7, 3)
182 FIELD(MIO_PIN_28, L2_SEL, 5, 2)
183 FIELD(MIO_PIN_28, L1_SEL, 3, 2)
184 FIELD(MIO_PIN_28, L0_SEL, 1, 2)
185 REG32(MIO_PIN_29, 0x74)
186 FIELD(MIO_PIN_29, L3_SEL, 7, 3)
187 FIELD(MIO_PIN_29, L2_SEL, 5, 2)
188 FIELD(MIO_PIN_29, L1_SEL, 3, 2)
189 FIELD(MIO_PIN_29, L0_SEL, 1, 2)
190 REG32(MIO_PIN_30, 0x78)
191 FIELD(MIO_PIN_30, L3_SEL, 7, 3)
192 FIELD(MIO_PIN_30, L2_SEL, 5, 2)
193 FIELD(MIO_PIN_30, L1_SEL, 3, 2)
194 FIELD(MIO_PIN_30, L0_SEL, 1, 2)
195 REG32(MIO_PIN_31, 0x7c)
196 FIELD(MIO_PIN_31, L3_SEL, 7, 3)
197 FIELD(MIO_PIN_31, L2_SEL, 5, 2)
198 FIELD(MIO_PIN_31, L1_SEL, 3, 2)
199 FIELD(MIO_PIN_31, L0_SEL, 1, 2)
200 REG32(MIO_PIN_32, 0x80)
201 FIELD(MIO_PIN_32, L3_SEL, 7, 3)
202 FIELD(MIO_PIN_32, L2_SEL, 5, 2)
203 FIELD(MIO_PIN_32, L1_SEL, 3, 2)
204 FIELD(MIO_PIN_32, L0_SEL, 1, 2)
205 REG32(MIO_PIN_33, 0x84)
206 FIELD(MIO_PIN_33, L3_SEL, 7, 3)
207 FIELD(MIO_PIN_33, L2_SEL, 5, 2)
208 FIELD(MIO_PIN_33, L1_SEL, 3, 2)
209 FIELD(MIO_PIN_33, L0_SEL, 1, 2)
210 REG32(MIO_PIN_34, 0x88)
211 FIELD(MIO_PIN_34, L3_SEL, 7, 3)
212 FIELD(MIO_PIN_34, L2_SEL, 5, 2)
213 FIELD(MIO_PIN_34, L1_SEL, 3, 2)
214 FIELD(MIO_PIN_34, L0_SEL, 1, 2)
215 REG32(MIO_PIN_35, 0x8c)
216 FIELD(MIO_PIN_35, L3_SEL, 7, 3)
217 FIELD(MIO_PIN_35, L2_SEL, 5, 2)
218 FIELD(MIO_PIN_35, L1_SEL, 3, 2)
219 FIELD(MIO_PIN_35, L0_SEL, 1, 2)
220 REG32(MIO_PIN_36, 0x90)
221 FIELD(MIO_PIN_36, L3_SEL, 7, 3)
222 FIELD(MIO_PIN_36, L2_SEL, 5, 2)
223 FIELD(MIO_PIN_36, L1_SEL, 3, 2)
224 FIELD(MIO_PIN_36, L0_SEL, 1, 2)
225 REG32(MIO_PIN_37, 0x94)
226 FIELD(MIO_PIN_37, L3_SEL, 7, 3)
227 FIELD(MIO_PIN_37, L2_SEL, 5, 2)
228 FIELD(MIO_PIN_37, L1_SEL, 3, 2)
229 FIELD(MIO_PIN_37, L0_SEL, 1, 2)
230 REG32(MIO_PIN_38, 0x98)
231 FIELD(MIO_PIN_38, L3_SEL, 7, 3)
232 FIELD(MIO_PIN_38, L2_SEL, 5, 2)
233 FIELD(MIO_PIN_38, L1_SEL, 3, 2)
234 FIELD(MIO_PIN_38, L0_SEL, 1, 2)
235 REG32(MIO_PIN_39, 0x9c)
236 FIELD(MIO_PIN_39, L3_SEL, 7, 3)
237 FIELD(MIO_PIN_39, L2_SEL, 5, 2)
238 FIELD(MIO_PIN_39, L1_SEL, 3, 2)
239 FIELD(MIO_PIN_39, L0_SEL, 1, 2)
240 REG32(MIO_PIN_40, 0xa0)
241 FIELD(MIO_PIN_40, L3_SEL, 7, 3)
242 FIELD(MIO_PIN_40, L2_SEL, 5, 2)
243 FIELD(MIO_PIN_40, L1_SEL, 3, 2)
244 FIELD(MIO_PIN_40, L0_SEL, 1, 2)
245 REG32(MIO_PIN_41, 0xa4)
246 FIELD(MIO_PIN_41, L3_SEL, 7, 3)
247 FIELD(MIO_PIN_41, L2_SEL, 5, 2)
248 FIELD(MIO_PIN_41, L1_SEL, 3, 2)
249 FIELD(MIO_PIN_41, L0_SEL, 1, 2)
250 REG32(MIO_PIN_42, 0xa8)
251 FIELD(MIO_PIN_42, L3_SEL, 7, 3)
252 FIELD(MIO_PIN_42, L2_SEL, 5, 2)
253 FIELD(MIO_PIN_42, L1_SEL, 3, 2)
254 FIELD(MIO_PIN_42, L0_SEL, 1, 2)
255 REG32(MIO_PIN_43, 0xac)
256 FIELD(MIO_PIN_43, L3_SEL, 7, 3)
257 FIELD(MIO_PIN_43, L2_SEL, 5, 2)
258 FIELD(MIO_PIN_43, L1_SEL, 3, 2)
259 FIELD(MIO_PIN_43, L0_SEL, 1, 2)
260 REG32(MIO_PIN_44, 0xb0)
261 FIELD(MIO_PIN_44, L3_SEL, 7, 3)
262 FIELD(MIO_PIN_44, L2_SEL, 5, 2)
263 FIELD(MIO_PIN_44, L1_SEL, 3, 2)
264 FIELD(MIO_PIN_44, L0_SEL, 1, 2)
265 REG32(MIO_PIN_45, 0xb4)
266 FIELD(MIO_PIN_45, L3_SEL, 7, 3)
267 FIELD(MIO_PIN_45, L2_SEL, 5, 2)
268 FIELD(MIO_PIN_45, L1_SEL, 3, 2)
269 FIELD(MIO_PIN_45, L0_SEL, 1, 2)
270 REG32(MIO_PIN_46, 0xb8)
271 FIELD(MIO_PIN_46, L3_SEL, 7, 3)
272 FIELD(MIO_PIN_46, L2_SEL, 5, 2)
273 FIELD(MIO_PIN_46, L1_SEL, 3, 2)
274 FIELD(MIO_PIN_46, L0_SEL, 1, 2)
275 REG32(MIO_PIN_47, 0xbc)
276 FIELD(MIO_PIN_47, L3_SEL, 7, 3)
277 FIELD(MIO_PIN_47, L2_SEL, 5, 2)
278 FIELD(MIO_PIN_47, L1_SEL, 3, 2)
279 FIELD(MIO_PIN_47, L0_SEL, 1, 2)
280 REG32(MIO_PIN_48, 0xc0)
281 FIELD(MIO_PIN_48, L3_SEL, 7, 3)
282 FIELD(MIO_PIN_48, L2_SEL, 5, 2)
283 FIELD(MIO_PIN_48, L1_SEL, 3, 2)
284 FIELD(MIO_PIN_48, L0_SEL, 1, 2)
285 REG32(MIO_PIN_49, 0xc4)
286 FIELD(MIO_PIN_49, L3_SEL, 7, 3)
287 FIELD(MIO_PIN_49, L2_SEL, 5, 2)
288 FIELD(MIO_PIN_49, L1_SEL, 3, 2)
289 FIELD(MIO_PIN_49, L0_SEL, 1, 2)
290 REG32(MIO_PIN_50, 0xc8)
291 FIELD(MIO_PIN_50, L3_SEL, 7, 3)
292 FIELD(MIO_PIN_50, L2_SEL, 5, 2)
293 FIELD(MIO_PIN_50, L1_SEL, 3, 2)
294 FIELD(MIO_PIN_50, L0_SEL, 1, 2)
295 REG32(MIO_PIN_51, 0xcc)
296 FIELD(MIO_PIN_51, L3_SEL, 7, 3)
297 FIELD(MIO_PIN_51, L2_SEL, 5, 2)
298 FIELD(MIO_PIN_51, L1_SEL, 3, 2)
299 FIELD(MIO_PIN_51, L0_SEL, 1, 2)
300 REG32(BNK0_EN_RX, 0x100)
301 FIELD(BNK0_EN_RX, BNK0_EN_RX, 0, 26)
302 REG32(BNK0_SEL_RX0, 0x104)
303 REG32(BNK0_SEL_RX1, 0x108)
304 FIELD(BNK0_SEL_RX1, BNK0_SEL_RX, 0, 20)
305 REG32(BNK0_EN_RX_SCHMITT_HYST, 0x10c)
306 FIELD(BNK0_EN_RX_SCHMITT_HYST, BNK0_EN_RX_SCHMITT_HYST, 0, 26)
307 REG32(BNK0_EN_WK_PD, 0x110)
308 FIELD(BNK0_EN_WK_PD, BNK0_EN_WK_PD, 0, 26)
309 REG32(BNK0_EN_WK_PU, 0x114)
310 FIELD(BNK0_EN_WK_PU, BNK0_EN_WK_PU, 0, 26)
311 REG32(BNK0_SEL_DRV0, 0x118)
312 REG32(BNK0_SEL_DRV1, 0x11c)
313 FIELD(BNK0_SEL_DRV1, BNK0_SEL_DRV, 0, 20)
314 REG32(BNK0_SEL_SLEW, 0x120)
315 FIELD(BNK0_SEL_SLEW, BNK0_SEL_SLEW, 0, 26)
316 REG32(BNK0_EN_DFT_OPT_INV, 0x124)
317 FIELD(BNK0_EN_DFT_OPT_INV, BNK0_EN_DFT_OPT_INV, 0, 26)
318 REG32(BNK0_EN_PAD2PAD_LOOPBACK, 0x128)
319 FIELD(BNK0_EN_PAD2PAD_LOOPBACK, BNK0_EN_PAD2PAD_LOOPBACK, 0, 13)
320 REG32(BNK0_RX_SPARE0, 0x12c)
321 REG32(BNK0_RX_SPARE1, 0x130)
322 FIELD(BNK0_RX_SPARE1, BNK0_RX_SPARE, 0, 20)
323 REG32(BNK0_TX_SPARE0, 0x134)
324 REG32(BNK0_TX_SPARE1, 0x138)
325 FIELD(BNK0_TX_SPARE1, BNK0_TX_SPARE, 0, 20)
326 REG32(BNK0_SEL_EN1P8, 0x13c)
327 FIELD(BNK0_SEL_EN1P8, BNK0_SEL_EN1P8, 0, 1)
328 REG32(BNK0_EN_B_POR_DETECT, 0x140)
329 FIELD(BNK0_EN_B_POR_DETECT, BNK0_EN_B_POR_DETECT, 0, 1)
330 REG32(BNK0_LPF_BYP_POR_DETECT, 0x144)
331 FIELD(BNK0_LPF_BYP_POR_DETECT, BNK0_LPF_BYP_POR_DETECT, 0, 1)
332 REG32(BNK0_EN_LATCH, 0x148)
333 FIELD(BNK0_EN_LATCH, BNK0_EN_LATCH, 0, 1)
334 REG32(BNK0_VBG_LPF_BYP_B, 0x14c)
335 FIELD(BNK0_VBG_LPF_BYP_B, BNK0_VBG_LPF_BYP_B, 0, 1)
336 REG32(BNK0_EN_AMP_B, 0x150)
337 FIELD(BNK0_EN_AMP_B, BNK0_EN_AMP_B, 0, 2)
338 REG32(BNK0_SPARE_BIAS, 0x154)
339 FIELD(BNK0_SPARE_BIAS, BNK0_SPARE_BIAS, 0, 4)
340 REG32(BNK0_DRIVER_BIAS, 0x158)
341 FIELD(BNK0_DRIVER_BIAS, BNK0_DRIVER_BIAS, 0, 15)
342 REG32(BNK0_VMODE, 0x15c)
343 FIELD(BNK0_VMODE, BNK0_VMODE, 0, 1)
344 REG32(BNK0_SEL_AUX_IO_RX, 0x160)
345 FIELD(BNK0_SEL_AUX_IO_RX, BNK0_SEL_AUX_IO_RX, 0, 26)
346 REG32(BNK0_EN_TX_HS_MODE, 0x164)
347 FIELD(BNK0_EN_TX_HS_MODE, BNK0_EN_TX_HS_MODE, 0, 26)
348 REG32(MIO_MST_TRI0, 0x200)
349 FIELD(MIO_MST_TRI0, PIN_25_TRI, 25, 1)
350 FIELD(MIO_MST_TRI0, PIN_24_TRI, 24, 1)
351 FIELD(MIO_MST_TRI0, PIN_23_TRI, 23, 1)
352 FIELD(MIO_MST_TRI0, PIN_22_TRI, 22, 1)
353 FIELD(MIO_MST_TRI0, PIN_21_TRI, 21, 1)
354 FIELD(MIO_MST_TRI0, PIN_20_TRI, 20, 1)
355 FIELD(MIO_MST_TRI0, PIN_19_TRI, 19, 1)
356 FIELD(MIO_MST_TRI0, PIN_18_TRI, 18, 1)
357 FIELD(MIO_MST_TRI0, PIN_17_TRI, 17, 1)
358 FIELD(MIO_MST_TRI0, PIN_16_TRI, 16, 1)
359 FIELD(MIO_MST_TRI0, PIN_15_TRI, 15, 1)
360 FIELD(MIO_MST_TRI0, PIN_14_TRI, 14, 1)
361 FIELD(MIO_MST_TRI0, PIN_13_TRI, 13, 1)
362 FIELD(MIO_MST_TRI0, PIN_12_TRI, 12, 1)
363 FIELD(MIO_MST_TRI0, PIN_11_TRI, 11, 1)
364 FIELD(MIO_MST_TRI0, PIN_10_TRI, 10, 1)
365 FIELD(MIO_MST_TRI0, PIN_09_TRI, 9, 1)
366 FIELD(MIO_MST_TRI0, PIN_08_TRI, 8, 1)
367 FIELD(MIO_MST_TRI0, PIN_07_TRI, 7, 1)
368 FIELD(MIO_MST_TRI0, PIN_06_TRI, 6, 1)
369 FIELD(MIO_MST_TRI0, PIN_05_TRI, 5, 1)
370 FIELD(MIO_MST_TRI0, PIN_04_TRI, 4, 1)
371 FIELD(MIO_MST_TRI0, PIN_03_TRI, 3, 1)
372 FIELD(MIO_MST_TRI0, PIN_02_TRI, 2, 1)
373 FIELD(MIO_MST_TRI0, PIN_01_TRI, 1, 1)
374 FIELD(MIO_MST_TRI0, PIN_00_TRI, 0, 1)
375 REG32(MIO_MST_TRI1, 0x204)
376 FIELD(MIO_MST_TRI1, PIN_51_TRI, 25, 1)
377 FIELD(MIO_MST_TRI1, PIN_50_TRI, 24, 1)
378 FIELD(MIO_MST_TRI1, PIN_49_TRI, 23, 1)
379 FIELD(MIO_MST_TRI1, PIN_48_TRI, 22, 1)
380 FIELD(MIO_MST_TRI1, PIN_47_TRI, 21, 1)
381 FIELD(MIO_MST_TRI1, PIN_46_TRI, 20, 1)
382 FIELD(MIO_MST_TRI1, PIN_45_TRI, 19, 1)
383 FIELD(MIO_MST_TRI1, PIN_44_TRI, 18, 1)
384 FIELD(MIO_MST_TRI1, PIN_43_TRI, 17, 1)
385 FIELD(MIO_MST_TRI1, PIN_42_TRI, 16, 1)
386 FIELD(MIO_MST_TRI1, PIN_41_TRI, 15, 1)
387 FIELD(MIO_MST_TRI1, PIN_40_TRI, 14, 1)
388 FIELD(MIO_MST_TRI1, PIN_39_TRI, 13, 1)
389 FIELD(MIO_MST_TRI1, PIN_38_TRI, 12, 1)
390 FIELD(MIO_MST_TRI1, PIN_37_TRI, 11, 1)
391 FIELD(MIO_MST_TRI1, PIN_36_TRI, 10, 1)
392 FIELD(MIO_MST_TRI1, PIN_35_TRI, 9, 1)
393 FIELD(MIO_MST_TRI1, PIN_34_TRI, 8, 1)
394 FIELD(MIO_MST_TRI1, PIN_33_TRI, 7, 1)
395 FIELD(MIO_MST_TRI1, PIN_32_TRI, 6, 1)
396 FIELD(MIO_MST_TRI1, PIN_31_TRI, 5, 1)
397 FIELD(MIO_MST_TRI1, PIN_30_TRI, 4, 1)
398 FIELD(MIO_MST_TRI1, PIN_29_TRI, 3, 1)
399 FIELD(MIO_MST_TRI1, PIN_28_TRI, 2, 1)
400 FIELD(MIO_MST_TRI1, PIN_27_TRI, 1, 1)
401 FIELD(MIO_MST_TRI1, PIN_26_TRI, 0, 1)
402 REG32(BNK1_EN_RX, 0x300)
403 FIELD(BNK1_EN_RX, BNK1_EN_RX, 0, 26)
404 REG32(BNK1_SEL_RX0, 0x304)
405 REG32(BNK1_SEL_RX1, 0x308)
406 FIELD(BNK1_SEL_RX1, BNK1_SEL_RX, 0, 20)
407 REG32(BNK1_EN_RX_SCHMITT_HYST, 0x30c)
408 FIELD(BNK1_EN_RX_SCHMITT_HYST, BNK1_EN_RX_SCHMITT_HYST, 0, 26)
409 REG32(BNK1_EN_WK_PD, 0x310)
410 FIELD(BNK1_EN_WK_PD, BNK1_EN_WK_PD, 0, 26)
411 REG32(BNK1_EN_WK_PU, 0x314)
412 FIELD(BNK1_EN_WK_PU, BNK1_EN_WK_PU, 0, 26)
413 REG32(BNK1_SEL_DRV0, 0x318)
414 REG32(BNK1_SEL_DRV1, 0x31c)
415 FIELD(BNK1_SEL_DRV1, BNK1_SEL_DRV, 0, 20)
416 REG32(BNK1_SEL_SLEW, 0x320)
417 FIELD(BNK1_SEL_SLEW, BNK1_SEL_SLEW, 0, 26)
418 REG32(BNK1_EN_DFT_OPT_INV, 0x324)
419 FIELD(BNK1_EN_DFT_OPT_INV, BNK1_EN_DFT_OPT_INV, 0, 26)
420 REG32(BNK1_EN_PAD2PAD_LOOPBACK, 0x328)
421 FIELD(BNK1_EN_PAD2PAD_LOOPBACK, BNK1_EN_PAD2PAD_LOOPBACK, 0, 13)
422 REG32(BNK1_RX_SPARE0, 0x32c)
423 REG32(BNK1_RX_SPARE1, 0x330)
424 FIELD(BNK1_RX_SPARE1, BNK1_RX_SPARE, 0, 20)
425 REG32(BNK1_TX_SPARE0, 0x334)
426 REG32(BNK1_TX_SPARE1, 0x338)
427 FIELD(BNK1_TX_SPARE1, BNK1_TX_SPARE, 0, 20)
428 REG32(BNK1_SEL_EN1P8, 0x33c)
429 FIELD(BNK1_SEL_EN1P8, BNK1_SEL_EN1P8, 0, 1)
430 REG32(BNK1_EN_B_POR_DETECT, 0x340)
431 FIELD(BNK1_EN_B_POR_DETECT, BNK1_EN_B_POR_DETECT, 0, 1)
432 REG32(BNK1_LPF_BYP_POR_DETECT, 0x344)
433 FIELD(BNK1_LPF_BYP_POR_DETECT, BNK1_LPF_BYP_POR_DETECT, 0, 1)
434 REG32(BNK1_EN_LATCH, 0x348)
435 FIELD(BNK1_EN_LATCH, BNK1_EN_LATCH, 0, 1)
436 REG32(BNK1_VBG_LPF_BYP_B, 0x34c)
437 FIELD(BNK1_VBG_LPF_BYP_B, BNK1_VBG_LPF_BYP_B, 0, 1)
438 REG32(BNK1_EN_AMP_B, 0x350)
439 FIELD(BNK1_EN_AMP_B, BNK1_EN_AMP_B, 0, 2)
440 REG32(BNK1_SPARE_BIAS, 0x354)
441 FIELD(BNK1_SPARE_BIAS, BNK1_SPARE_BIAS, 0, 4)
442 REG32(BNK1_DRIVER_BIAS, 0x358)
443 FIELD(BNK1_DRIVER_BIAS, BNK1_DRIVER_BIAS, 0, 15)
444 REG32(BNK1_VMODE, 0x35c)
445 FIELD(BNK1_VMODE, BNK1_VMODE, 0, 1)
446 REG32(BNK1_SEL_AUX_IO_RX, 0x360)
447 FIELD(BNK1_SEL_AUX_IO_RX, BNK1_SEL_AUX_IO_RX, 0, 26)
448 REG32(BNK1_EN_TX_HS_MODE, 0x364)
449 FIELD(BNK1_EN_TX_HS_MODE, BNK1_EN_TX_HS_MODE, 0, 26)
450 REG32(SD0_CLK_CTRL, 0x400)
451 FIELD(SD0_CLK_CTRL, SDIO0_FBCLK_SEL, 2, 1)
452 FIELD(SD0_CLK_CTRL, SDIO0_RX_SRC_SEL, 0, 2)
453 REG32(SD0_CTRL_REG, 0x404)
454 FIELD(SD0_CTRL_REG, SD0_EMMC_SEL, 0, 1)
455 REG32(SD0_CONFIG_REG1, 0x410)
456 FIELD(SD0_CONFIG_REG1, SD0_BASECLK, 7, 8)
457 FIELD(SD0_CONFIG_REG1, SD0_TUNIGCOUNT, 1, 6)
458 FIELD(SD0_CONFIG_REG1, SD0_ASYNCWKPENA, 0, 1)
459 REG32(SD0_CONFIG_REG2, 0x414)
460 FIELD(SD0_CONFIG_REG2, SD0_SLOTTYPE, 12, 2)
461 FIELD(SD0_CONFIG_REG2, SD0_ASYCINTR, 11, 1)
462 FIELD(SD0_CONFIG_REG2, SD0_64BIT, 10, 1)
463 FIELD(SD0_CONFIG_REG2, SD0_1P8V, 9, 1)
464 FIELD(SD0_CONFIG_REG2, SD0_3P0V, 8, 1)
465 FIELD(SD0_CONFIG_REG2, SD0_3P3V, 7, 1)
466 FIELD(SD0_CONFIG_REG2, SD0_SUSPRES, 6, 1)
467 FIELD(SD0_CONFIG_REG2, SD0_SDMA, 5, 1)
468 FIELD(SD0_CONFIG_REG2, SD0_HIGHSPEED, 4, 1)
469 FIELD(SD0_CONFIG_REG2, SD0_ADMA2, 3, 1)
470 FIELD(SD0_CONFIG_REG2, SD0_8BIT, 2, 1)
471 FIELD(SD0_CONFIG_REG2, SD0_MAXBLK, 0, 2)
472 REG32(SD0_CONFIG_REG3, 0x418)
473 FIELD(SD0_CONFIG_REG3, SD0_TUNINGSDR50, 10, 1)
474 FIELD(SD0_CONFIG_REG3, SD0_RETUNETMR, 6, 4)
475 FIELD(SD0_CONFIG_REG3, SD0_DDRIVER, 5, 1)
476 FIELD(SD0_CONFIG_REG3, SD0_CDRIVER, 4, 1)
477 FIELD(SD0_CONFIG_REG3, SD0_ADRIVER, 3, 1)
478 FIELD(SD0_CONFIG_REG3, SD0_DDR50, 2, 1)
479 FIELD(SD0_CONFIG_REG3, SD0_SDR104, 1, 1)
480 FIELD(SD0_CONFIG_REG3, SD0_SDR50, 0, 1)
481 REG32(SD0_INITPRESET, 0x41c)
482 FIELD(SD0_INITPRESET, SD0_INITPRESET, 0, 13)
483 REG32(SD0_DSPPRESET, 0x420)
484 FIELD(SD0_DSPPRESET, SD0_DSPPRESET, 0, 13)
485 REG32(SD0_HSPDPRESET, 0x424)
486 FIELD(SD0_HSPDPRESET, SD0_HSPDPRESET, 0, 13)
487 REG32(SD0_SDR12PRESET, 0x428)
488 FIELD(SD0_SDR12PRESET, SD0_SDR12PRESET, 0, 13)
489 REG32(SD0_SDR25PRESET, 0x42c)
490 FIELD(SD0_SDR25PRESET, SD0_SDR25PRESET, 0, 13)
491 REG32(SD0_SDR50PRSET, 0x430)
492 FIELD(SD0_SDR50PRSET, SD0_SDR50PRESET, 0, 13)
493 REG32(SD0_SDR104PRST, 0x434)
494 FIELD(SD0_SDR104PRST, SD0_SDR104PRESET, 0, 13)
495 REG32(SD0_DDR50PRESET, 0x438)
496 FIELD(SD0_DDR50PRESET, SD0_DDR50PRESET, 0, 13)
497 REG32(SD0_MAXCUR1P8, 0x43c)
498 FIELD(SD0_MAXCUR1P8, SD0_MAXCUR1P8, 0, 8)
499 REG32(SD0_MAXCUR3P0, 0x440)
500 FIELD(SD0_MAXCUR3P0, SD0_MAXCUR3P0, 0, 8)
501 REG32(SD0_MAXCUR3P3, 0x444)
502 FIELD(SD0_MAXCUR3P3, SD0_MAXCUR3P3, 0, 8)
503 REG32(SD0_DLL_CTRL, 0x448)
504 FIELD(SD0_DLL_CTRL, SD0_CLKSTABLE_CFG, 9, 1)
505 FIELD(SD0_DLL_CTRL, SD0_DLL_CFG, 5, 4)
506 FIELD(SD0_DLL_CTRL, SD0_DLL_PSDONE, 4, 1)
507 FIELD(SD0_DLL_CTRL, SD0_DLL_OVF, 3, 1)
508 FIELD(SD0_DLL_CTRL, SD0_DLL_RST, 2, 1)
509 FIELD(SD0_DLL_CTRL, SD0_DLL_TESTMODE, 1, 1)
510 FIELD(SD0_DLL_CTRL, SD0_DLL_LOCK, 0, 1)
511 REG32(SD0_CDN_CTRL, 0x44c)
512 FIELD(SD0_CDN_CTRL, SD0_CDN_CTRL, 0, 1)
513 REG32(SD0_DLL_TEST, 0x450)
514 FIELD(SD0_DLL_TEST, DLL_DIV, 16, 8)
515 FIELD(SD0_DLL_TEST, DLL_TX_SEL, 9, 7)
516 FIELD(SD0_DLL_TEST, DLL_RX_SEL, 0, 9)
517 REG32(SD0_RX_TUNING_SEL, 0x454)
518 FIELD(SD0_RX_TUNING_SEL, SD0_RX_SEL, 0, 9)
519 REG32(SD0_DLL_DIV_MAP0, 0x458)
520 FIELD(SD0_DLL_DIV_MAP0, DIV_3, 24, 8)
521 FIELD(SD0_DLL_DIV_MAP0, DIV_2, 16, 8)
522 FIELD(SD0_DLL_DIV_MAP0, DIV_1, 8, 8)
523 FIELD(SD0_DLL_DIV_MAP0, DIV_0, 0, 8)
524 REG32(SD0_DLL_DIV_MAP1, 0x45c)
525 FIELD(SD0_DLL_DIV_MAP1, DIV_7, 24, 8)
526 FIELD(SD0_DLL_DIV_MAP1, DIV_6, 16, 8)
527 FIELD(SD0_DLL_DIV_MAP1, DIV_5, 8, 8)
528 FIELD(SD0_DLL_DIV_MAP1, DIV_4, 0, 8)
529 REG32(SD0_IOU_COHERENT_CTRL, 0x460)
530 FIELD(SD0_IOU_COHERENT_CTRL, SD0_AXI_COH, 0, 4)
531 REG32(SD0_IOU_INTERCONNECT_ROUTE, 0x464)
532 FIELD(SD0_IOU_INTERCONNECT_ROUTE, SD0, 0, 1)
533 REG32(SD0_IOU_RAM, 0x468)
534 FIELD(SD0_IOU_RAM, EMASA0, 6, 1)
535 FIELD(SD0_IOU_RAM, EMAB0, 3, 3)
536 FIELD(SD0_IOU_RAM, EMAA0, 0, 3)
537 REG32(SD0_IOU_INTERCONNECT_QOS, 0x46c)
538 FIELD(SD0_IOU_INTERCONNECT_QOS, SD0_QOS, 0, 4)
539 REG32(SD1_CLK_CTRL, 0x480)
540 FIELD(SD1_CLK_CTRL, SDIO1_FBCLK_SEL, 1, 1)
541 FIELD(SD1_CLK_CTRL, SDIO1_RX_SRC_SEL, 0, 1)
542 REG32(SD1_CTRL_REG, 0x484)
543 FIELD(SD1_CTRL_REG, SD1_EMMC_SEL, 0, 1)
544 REG32(SD1_CONFIG_REG1, 0x490)
545 FIELD(SD1_CONFIG_REG1, SD1_BASECLK, 7, 8)
546 FIELD(SD1_CONFIG_REG1, SD1_TUNIGCOUNT, 1, 6)
547 FIELD(SD1_CONFIG_REG1, SD1_ASYNCWKPENA, 0, 1)
548 REG32(SD1_CONFIG_REG2, 0x494)
549 FIELD(SD1_CONFIG_REG2, SD1_SLOTTYPE, 12, 2)
550 FIELD(SD1_CONFIG_REG2, SD1_ASYCINTR, 11, 1)
551 FIELD(SD1_CONFIG_REG2, SD1_64BIT, 10, 1)
552 FIELD(SD1_CONFIG_REG2, SD1_1P8V, 9, 1)
553 FIELD(SD1_CONFIG_REG2, SD1_3P0V, 8, 1)
554 FIELD(SD1_CONFIG_REG2, SD1_3P3V, 7, 1)
555 FIELD(SD1_CONFIG_REG2, SD1_SUSPRES, 6, 1)
556 FIELD(SD1_CONFIG_REG2, SD1_SDMA, 5, 1)
557 FIELD(SD1_CONFIG_REG2, SD1_HIGHSPEED, 4, 1)
558 FIELD(SD1_CONFIG_REG2, SD1_ADMA2, 3, 1)
559 FIELD(SD1_CONFIG_REG2, SD1_8BIT, 2, 1)
560 FIELD(SD1_CONFIG_REG2, SD1_MAXBLK, 0, 2)
561 REG32(SD1_CONFIG_REG3, 0x498)
562 FIELD(SD1_CONFIG_REG3, SD1_TUNINGSDR50, 10, 1)
563 FIELD(SD1_CONFIG_REG3, SD1_RETUNETMR, 6, 4)
564 FIELD(SD1_CONFIG_REG3, SD1_DDRIVER, 5, 1)
565 FIELD(SD1_CONFIG_REG3, SD1_CDRIVER, 4, 1)
566 FIELD(SD1_CONFIG_REG3, SD1_ADRIVER, 3, 1)
567 FIELD(SD1_CONFIG_REG3, SD1_DDR50, 2, 1)
568 FIELD(SD1_CONFIG_REG3, SD1_SDR104, 1, 1)
569 FIELD(SD1_CONFIG_REG3, SD1_SDR50, 0, 1)
570 REG32(SD1_INITPRESET, 0x49c)
571 FIELD(SD1_INITPRESET, SD1_INITPRESET, 0, 13)
572 REG32(SD1_DSPPRESET, 0x4a0)
573 FIELD(SD1_DSPPRESET, SD1_DSPPRESET, 0, 13)
574 REG32(SD1_HSPDPRESET, 0x4a4)
575 FIELD(SD1_HSPDPRESET, SD1_HSPDPRESET, 0, 13)
576 REG32(SD1_SDR12PRESET, 0x4a8)
577 FIELD(SD1_SDR12PRESET, SD1_SDR12PRESET, 0, 13)
578 REG32(SD1_SDR25PRESET, 0x4ac)
579 FIELD(SD1_SDR25PRESET, SD1_SDR25PRESET, 0, 13)
580 REG32(SD1_SDR50PRSET, 0x4b0)
581 FIELD(SD1_SDR50PRSET, SD1_SDR50PRESET, 0, 13)
582 REG32(SD1_SDR104PRST, 0x4b4)
583 FIELD(SD1_SDR104PRST, SD1_SDR104PRESET, 0, 13)
584 REG32(SD1_DDR50PRESET, 0x4b8)
585 FIELD(SD1_DDR50PRESET, SD1_DDR50PRESET, 0, 13)
586 REG32(SD1_MAXCUR1P8, 0x4bc)
587 FIELD(SD1_MAXCUR1P8, SD1_MAXCUR1P8, 0, 8)
588 REG32(SD1_MAXCUR3P0, 0x4c0)
589 FIELD(SD1_MAXCUR3P0, SD1_MAXCUR3P0, 0, 8)
590 REG32(SD1_MAXCUR3P3, 0x4c4)
591 FIELD(SD1_MAXCUR3P3, SD1_MAXCUR3P3, 0, 8)
592 REG32(SD1_DLL_CTRL, 0x4c8)
593 FIELD(SD1_DLL_CTRL, SD1_CLKSTABLE_CFG, 9, 1)
594 FIELD(SD1_DLL_CTRL, SD1_DLL_CFG, 5, 4)
595 FIELD(SD1_DLL_CTRL, SD1_DLL_PSDONE, 4, 1)
596 FIELD(SD1_DLL_CTRL, SD1_DLL_OVF, 3, 1)
597 FIELD(SD1_DLL_CTRL, SD1_DLL_RST, 2, 1)
598 FIELD(SD1_DLL_CTRL, SD1_DLL_TESTMODE, 1, 1)
599 FIELD(SD1_DLL_CTRL, SD1_DLL_LOCK, 0, 1)
600 REG32(SD1_CDN_CTRL, 0x4cc)
601 FIELD(SD1_CDN_CTRL, SD1_CDN_CTRL, 0, 1)
602 REG32(SD1_DLL_TEST, 0x4d0)
603 FIELD(SD1_DLL_TEST, DLL_DIV, 16, 8)
604 FIELD(SD1_DLL_TEST, DLL_TX_SEL, 9, 7)
605 FIELD(SD1_DLL_TEST, DLL_RX_SEL, 0, 9)
606 REG32(SD1_RX_TUNING_SEL, 0x4d4)
607 FIELD(SD1_RX_TUNING_SEL, SD1_RX_SEL, 0, 9)
608 REG32(SD1_DLL_DIV_MAP0, 0x4d8)
609 FIELD(SD1_DLL_DIV_MAP0, DIV_3, 24, 8)
610 FIELD(SD1_DLL_DIV_MAP0, DIV_2, 16, 8)
611 FIELD(SD1_DLL_DIV_MAP0, DIV_1, 8, 8)
612 FIELD(SD1_DLL_DIV_MAP0, DIV_0, 0, 8)
613 REG32(SD1_DLL_DIV_MAP1, 0x4dc)
614 FIELD(SD1_DLL_DIV_MAP1, DIV_7, 24, 8)
615 FIELD(SD1_DLL_DIV_MAP1, DIV_6, 16, 8)
616 FIELD(SD1_DLL_DIV_MAP1, DIV_5, 8, 8)
617 FIELD(SD1_DLL_DIV_MAP1, DIV_4, 0, 8)
618 REG32(SD1_IOU_COHERENT_CTRL, 0x4e0)
619 FIELD(SD1_IOU_COHERENT_CTRL, SD1_AXI_COH, 0, 4)
620 REG32(SD1_IOU_INTERCONNECT_ROUTE, 0x4e4)
621 FIELD(SD1_IOU_INTERCONNECT_ROUTE, SD1, 0, 1)
622 REG32(SD1_IOU_RAM, 0x4e8)
623 FIELD(SD1_IOU_RAM, EMASA0, 6, 1)
624 FIELD(SD1_IOU_RAM, EMAB0, 3, 3)
625 FIELD(SD1_IOU_RAM, EMAA0, 0, 3)
626 REG32(SD1_IOU_INTERCONNECT_QOS, 0x4ec)
627 FIELD(SD1_IOU_INTERCONNECT_QOS, SD1_QOS, 0, 4)
628 REG32(OSPI_QSPI_IOU_AXI_MUX_SEL, 0x504)
629 FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL, 1, 1)
630 FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, QSPI_OSPI_MUX_SEL, 0, 1)
631 REG32(QSPI_IOU_COHERENT_CTRL, 0x508)
632 FIELD(QSPI_IOU_COHERENT_CTRL, QSPI_AXI_COH, 0, 4)
633 REG32(QSPI_IOU_INTERCONNECT_ROUTE, 0x50c)
634 FIELD(QSPI_IOU_INTERCONNECT_ROUTE, QSPI, 0, 1)
635 REG32(QSPI_IOU_RAM, 0x510)
636 FIELD(QSPI_IOU_RAM, EMASA1, 13, 1)
637 FIELD(QSPI_IOU_RAM, EMAB1, 10, 3)
638 FIELD(QSPI_IOU_RAM, EMAA1, 7, 3)
639 FIELD(QSPI_IOU_RAM, EMASA0, 6, 1)
640 FIELD(QSPI_IOU_RAM, EMAB0, 3, 3)
641 FIELD(QSPI_IOU_RAM, EMAA0, 0, 3)
642 REG32(QSPI_IOU_INTERCONNECT_QOS, 0x514)
643 FIELD(QSPI_IOU_INTERCONNECT_QOS, QSPI_QOS, 0, 4)
644 REG32(OSPI_IOU_COHERENT_CTRL, 0x530)
645 FIELD(OSPI_IOU_COHERENT_CTRL, OSPI_AXI_COH, 0, 4)
646 REG32(OSPI_IOU_INTERCONNECT_ROUTE, 0x534)
647 FIELD(OSPI_IOU_INTERCONNECT_ROUTE, OSPI, 0, 1)
648 REG32(OSPI_IOU_RAM, 0x538)
649 FIELD(OSPI_IOU_RAM, EMAS0, 5, 1)
650 FIELD(OSPI_IOU_RAM, EMAW0, 3, 2)
651 FIELD(OSPI_IOU_RAM, EMA0, 0, 3)
652 REG32(OSPI_IOU_INTERCONNECT_QOS, 0x53c)
653 FIELD(OSPI_IOU_INTERCONNECT_QOS, OSPI_QOS, 0, 4)
654 REG32(OSPI_REFCLK_DLY_CTRL, 0x540)
655 FIELD(OSPI_REFCLK_DLY_CTRL, DLY1, 3, 2)
656 FIELD(OSPI_REFCLK_DLY_CTRL, DLY0, 0, 3)
657 REG32(CUR_PWR_ST, 0x600)
658 FIELD(CUR_PWR_ST, U2PMU, 0, 2)
659 REG32(CONNECT_ST, 0x604)
660 FIELD(CONNECT_ST, U2PMU, 0, 1)
661 REG32(PW_STATE_REQ, 0x608)
662 FIELD(PW_STATE_REQ, BIT_1_0, 0, 2)
663 REG32(HOST_U2_PORT_DISABLE, 0x60c)
664 FIELD(HOST_U2_PORT_DISABLE, BIT_0, 0, 1)
665 REG32(DBG_U2PMU, 0x610)
666 REG32(DBG_U2PMU_EXT1, 0x614)
667 REG32(DBG_U2PMU_EXT2, 0x618)
668 FIELD(DBG_U2PMU_EXT2, BIT_67_64, 0, 4)
669 REG32(PME_GEN_U2PMU, 0x61c)
670 FIELD(PME_GEN_U2PMU, BIT_0, 0, 1)
671 REG32(PWR_CONFIG_USB2, 0x620)
672 FIELD(PWR_CONFIG_USB2, STRAP, 0, 30)
673 REG32(PHY_HUB, 0x624)
674 FIELD(PHY_HUB, VBUS_CTRL, 1, 1)
675 FIELD(PHY_HUB, OVER_CURRENT, 0, 1)
676 REG32(CTRL, 0x700)
677 FIELD(CTRL, SLVERR_ENABLE, 0, 1)
678 REG32(ISR, 0x800)
679 FIELD(ISR, ADDR_DECODE_ERR, 0, 1)
680 REG32(IMR, 0x804)
681 FIELD(IMR, ADDR_DECODE_ERR, 0, 1)
682 REG32(IER, 0x808)
683 FIELD(IER, ADDR_DECODE_ERR, 0, 1)
684 REG32(IDR, 0x80c)
685 FIELD(IDR, ADDR_DECODE_ERR, 0, 1)
686 REG32(ITR, 0x810)
687 FIELD(ITR, ADDR_DECODE_ERR, 0, 1)
688 REG32(PARITY_ISR, 0x814)
689 FIELD(PARITY_ISR, PERR_AXI_SD1_IOU, 12, 1)
690 FIELD(PARITY_ISR, PERR_AXI_SD0_IOU, 11, 1)
691 FIELD(PARITY_ISR, PERR_AXI_QSPI_IOU, 10, 1)
692 FIELD(PARITY_ISR, PERR_AXI_OSPI_IOU, 9, 1)
693 FIELD(PARITY_ISR, PERR_IOU_SD1, 8, 1)
694 FIELD(PARITY_ISR, PERR_IOU_SD0, 7, 1)
695 FIELD(PARITY_ISR, PERR_IOU_QSPI1, 6, 1)
696 FIELD(PARITY_ISR, PERR_IOUSLCR_SECURE_APB, 5, 1)
697 FIELD(PARITY_ISR, PERR_IOUSLCR_APB, 4, 1)
698 FIELD(PARITY_ISR, PERR_QSPI0_APB, 3, 1)
699 FIELD(PARITY_ISR, PERR_OSPI_APB, 2, 1)
700 FIELD(PARITY_ISR, PERR_I2C_APB, 1, 1)
701 FIELD(PARITY_ISR, PERR_GPIO_APB, 0, 1)
702 REG32(PARITY_IMR, 0x818)
703 FIELD(PARITY_IMR, PERR_AXI_SD1_IOU, 12, 1)
704 FIELD(PARITY_IMR, PERR_AXI_SD0_IOU, 11, 1)
705 FIELD(PARITY_IMR, PERR_AXI_QSPI_IOU, 10, 1)
706 FIELD(PARITY_IMR, PERR_AXI_OSPI_IOU, 9, 1)
707 FIELD(PARITY_IMR, PERR_IOU_SD1, 8, 1)
708 FIELD(PARITY_IMR, PERR_IOU_SD0, 7, 1)
709 FIELD(PARITY_IMR, PERR_IOU_QSPI1, 6, 1)
710 FIELD(PARITY_IMR, PERR_IOUSLCR_SECURE_APB, 5, 1)
711 FIELD(PARITY_IMR, PERR_IOUSLCR_APB, 4, 1)
712 FIELD(PARITY_IMR, PERR_QSPI0_APB, 3, 1)
713 FIELD(PARITY_IMR, PERR_OSPI_APB, 2, 1)
714 FIELD(PARITY_IMR, PERR_I2C_APB, 1, 1)
715 FIELD(PARITY_IMR, PERR_GPIO_APB, 0, 1)
716 REG32(PARITY_IER, 0x81c)
717 FIELD(PARITY_IER, PERR_AXI_SD1_IOU, 12, 1)
718 FIELD(PARITY_IER, PERR_AXI_SD0_IOU, 11, 1)
719 FIELD(PARITY_IER, PERR_AXI_QSPI_IOU, 10, 1)
720 FIELD(PARITY_IER, PERR_AXI_OSPI_IOU, 9, 1)
721 FIELD(PARITY_IER, PERR_IOU_SD1, 8, 1)
722 FIELD(PARITY_IER, PERR_IOU_SD0, 7, 1)
723 FIELD(PARITY_IER, PERR_IOU_QSPI1, 6, 1)
724 FIELD(PARITY_IER, PERR_IOUSLCR_SECURE_APB, 5, 1)
725 FIELD(PARITY_IER, PERR_IOUSLCR_APB, 4, 1)
726 FIELD(PARITY_IER, PERR_QSPI0_APB, 3, 1)
727 FIELD(PARITY_IER, PERR_OSPI_APB, 2, 1)
728 FIELD(PARITY_IER, PERR_I2C_APB, 1, 1)
729 FIELD(PARITY_IER, PERR_GPIO_APB, 0, 1)
730 REG32(PARITY_IDR, 0x820)
731 FIELD(PARITY_IDR, PERR_AXI_SD1_IOU, 12, 1)
732 FIELD(PARITY_IDR, PERR_AXI_SD0_IOU, 11, 1)
733 FIELD(PARITY_IDR, PERR_AXI_QSPI_IOU, 10, 1)
734 FIELD(PARITY_IDR, PERR_AXI_OSPI_IOU, 9, 1)
735 FIELD(PARITY_IDR, PERR_IOU_SD1, 8, 1)
736 FIELD(PARITY_IDR, PERR_IOU_SD0, 7, 1)
737 FIELD(PARITY_IDR, PERR_IOU_QSPI1, 6, 1)
738 FIELD(PARITY_IDR, PERR_IOUSLCR_SECURE_APB, 5, 1)
739 FIELD(PARITY_IDR, PERR_IOUSLCR_APB, 4, 1)
740 FIELD(PARITY_IDR, PERR_QSPI0_APB, 3, 1)
741 FIELD(PARITY_IDR, PERR_OSPI_APB, 2, 1)
742 FIELD(PARITY_IDR, PERR_I2C_APB, 1, 1)
743 FIELD(PARITY_IDR, PERR_GPIO_APB, 0, 1)
744 REG32(PARITY_ITR, 0x824)
745 FIELD(PARITY_ITR, PERR_AXI_SD1_IOU, 12, 1)
746 FIELD(PARITY_ITR, PERR_AXI_SD0_IOU, 11, 1)
747 FIELD(PARITY_ITR, PERR_AXI_QSPI_IOU, 10, 1)
748 FIELD(PARITY_ITR, PERR_AXI_OSPI_IOU, 9, 1)
749 FIELD(PARITY_ITR, PERR_IOU_SD1, 8, 1)
750 FIELD(PARITY_ITR, PERR_IOU_SD0, 7, 1)
751 FIELD(PARITY_ITR, PERR_IOU_QSPI1, 6, 1)
752 FIELD(PARITY_ITR, PERR_IOUSLCR_SECURE_APB, 5, 1)
753 FIELD(PARITY_ITR, PERR_IOUSLCR_APB, 4, 1)
754 FIELD(PARITY_ITR, PERR_QSPI0_APB, 3, 1)
755 FIELD(PARITY_ITR, PERR_OSPI_APB, 2, 1)
756 FIELD(PARITY_ITR, PERR_I2C_APB, 1, 1)
757 FIELD(PARITY_ITR, PERR_GPIO_APB, 0, 1)
758 REG32(WPROT0, 0x828)
759 FIELD(WPROT0, ACTIVE, 0, 1)
760
761 static void parity_imr_update_irq(XlnxVersalPmcIouSlcr *s)
762 {
763 bool pending = s->regs[R_PARITY_ISR] & ~s->regs[R_PARITY_IMR];
764 qemu_set_irq(s->irq_parity_imr, pending);
765 }
766
767 static void parity_isr_postw(RegisterInfo *reg, uint64_t val64)
768 {
769 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
770 parity_imr_update_irq(s);
771 }
772
773 static uint64_t parity_ier_prew(RegisterInfo *reg, uint64_t val64)
774 {
775 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
776 uint32_t val = val64;
777
778 s->regs[R_PARITY_IMR] &= ~val;
779 parity_imr_update_irq(s);
780 return 0;
781 }
782
783 static uint64_t parity_idr_prew(RegisterInfo *reg, uint64_t val64)
784 {
785 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
786 uint32_t val = val64;
787
788 s->regs[R_PARITY_IMR] |= val;
789 parity_imr_update_irq(s);
790 return 0;
791 }
792
793 static uint64_t parity_itr_prew(RegisterInfo *reg, uint64_t val64)
794 {
795 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
796 uint32_t val = val64;
797
798 s->regs[R_PARITY_ISR] |= val;
799 parity_imr_update_irq(s);
800 return 0;
801 }
802
803 static void imr_update_irq(XlnxVersalPmcIouSlcr *s)
804 {
805 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
806 qemu_set_irq(s->irq_imr, pending);
807 }
808
809 static void isr_postw(RegisterInfo *reg, uint64_t val64)
810 {
811 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
812 imr_update_irq(s);
813 }
814
815 static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64)
816 {
817 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
818 uint32_t val = val64;
819
820 s->regs[R_IMR] &= ~val;
821 imr_update_irq(s);
822 return 0;
823 }
824
825 static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64)
826 {
827 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
828 uint32_t val = val64;
829
830 s->regs[R_IMR] |= val;
831 imr_update_irq(s);
832 return 0;
833 }
834
835 static uint64_t itr_prew(RegisterInfo *reg, uint64_t val64)
836 {
837 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
838 uint32_t val = val64;
839
840 s->regs[R_ISR] |= val;
841 imr_update_irq(s);
842 return 0;
843 }
844
845 static uint64_t sd0_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64)
846 {
847 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
848 uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD0_CTRL_REG, SD0_EMMC_SEL);
849
850 if (prev != (val64 & R_SD0_CTRL_REG_SD0_EMMC_SEL_MASK)) {
851 qemu_set_irq(s->sd_emmc_sel[0], !!val64);
852 }
853
854 return val64;
855 }
856
857 static uint64_t sd1_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64)
858 {
859 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
860 uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD1_CTRL_REG, SD1_EMMC_SEL);
861
862 if (prev != (val64 & R_SD1_CTRL_REG_SD1_EMMC_SEL_MASK)) {
863 qemu_set_irq(s->sd_emmc_sel[1], !!val64);
864 }
865
866 return val64;
867 }
868
869 static uint64_t ospi_qspi_iou_axi_mux_sel_prew(RegisterInfo *reg,
870 uint64_t val64)
871 {
872 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);
873 uint32_t val32 = (uint32_t) val64;
874 uint8_t ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL,
875 OSPI_MUX_SEL);
876 uint8_t qspi_ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL,
877 QSPI_OSPI_MUX_SEL);
878
879 if (ospi_mux_sel !=
880 ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL)) {
881 qemu_set_irq(s->ospi_mux_sel, !!ospi_mux_sel);
882 }
883
884 if (qspi_ospi_mux_sel !=
885 ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL,
886 QSPI_OSPI_MUX_SEL)) {
887 qemu_set_irq(s->qspi_ospi_mux_sel, !!qspi_ospi_mux_sel);
888 }
889
890 return val64;
891 }
892
893 static RegisterAccessInfo pmc_iou_slcr_regs_info[] = {
894 { .name = "MIO_PIN_0", .addr = A_MIO_PIN_0,
895 .rsvd = 0xfffffc01,
896 },{ .name = "MIO_PIN_1", .addr = A_MIO_PIN_1,
897 .rsvd = 0xfffffc01,
898 },{ .name = "MIO_PIN_2", .addr = A_MIO_PIN_2,
899 .rsvd = 0xfffffc01,
900 },{ .name = "MIO_PIN_3", .addr = A_MIO_PIN_3,
901 .rsvd = 0xfffffc01,
902 },{ .name = "MIO_PIN_4", .addr = A_MIO_PIN_4,
903 .rsvd = 0xfffffc01,
904 },{ .name = "MIO_PIN_5", .addr = A_MIO_PIN_5,
905 .rsvd = 0xfffffc01,
906 },{ .name = "MIO_PIN_6", .addr = A_MIO_PIN_6,
907 .rsvd = 0xfffffc01,
908 },{ .name = "MIO_PIN_7", .addr = A_MIO_PIN_7,
909 .rsvd = 0xfffffc01,
910 },{ .name = "MIO_PIN_8", .addr = A_MIO_PIN_8,
911 .rsvd = 0xfffffc01,
912 },{ .name = "MIO_PIN_9", .addr = A_MIO_PIN_9,
913 .rsvd = 0xfffffc01,
914 },{ .name = "MIO_PIN_10", .addr = A_MIO_PIN_10,
915 .rsvd = 0xfffffc01,
916 },{ .name = "MIO_PIN_11", .addr = A_MIO_PIN_11,
917 .rsvd = 0xfffffc01,
918 },{ .name = "MIO_PIN_12", .addr = A_MIO_PIN_12,
919 .rsvd = 0xfffffc01,
920 },{ .name = "MIO_PIN_13", .addr = A_MIO_PIN_13,
921 .rsvd = 0xfffffc01,
922 },{ .name = "MIO_PIN_14", .addr = A_MIO_PIN_14,
923 .rsvd = 0xfffffc01,
924 },{ .name = "MIO_PIN_15", .addr = A_MIO_PIN_15,
925 .rsvd = 0xfffffc01,
926 },{ .name = "MIO_PIN_16", .addr = A_MIO_PIN_16,
927 .rsvd = 0xfffffc01,
928 },{ .name = "MIO_PIN_17", .addr = A_MIO_PIN_17,
929 .rsvd = 0xfffffc01,
930 },{ .name = "MIO_PIN_18", .addr = A_MIO_PIN_18,
931 .rsvd = 0xfffffc01,
932 },{ .name = "MIO_PIN_19", .addr = A_MIO_PIN_19,
933 .rsvd = 0xfffffc01,
934 },{ .name = "MIO_PIN_20", .addr = A_MIO_PIN_20,
935 .rsvd = 0xfffffc01,
936 },{ .name = "MIO_PIN_21", .addr = A_MIO_PIN_21,
937 .rsvd = 0xfffffc01,
938 },{ .name = "MIO_PIN_22", .addr = A_MIO_PIN_22,
939 .rsvd = 0xfffffc01,
940 },{ .name = "MIO_PIN_23", .addr = A_MIO_PIN_23,
941 .rsvd = 0xfffffc01,
942 },{ .name = "MIO_PIN_24", .addr = A_MIO_PIN_24,
943 .rsvd = 0xfffffc01,
944 },{ .name = "MIO_PIN_25", .addr = A_MIO_PIN_25,
945 .rsvd = 0xfffffc01,
946 },{ .name = "MIO_PIN_26", .addr = A_MIO_PIN_26,
947 .rsvd = 0xfffffc01,
948 },{ .name = "MIO_PIN_27", .addr = A_MIO_PIN_27,
949 .rsvd = 0xfffffc01,
950 },{ .name = "MIO_PIN_28", .addr = A_MIO_PIN_28,
951 .rsvd = 0xfffffc01,
952 },{ .name = "MIO_PIN_29", .addr = A_MIO_PIN_29,
953 .rsvd = 0xfffffc01,
954 },{ .name = "MIO_PIN_30", .addr = A_MIO_PIN_30,
955 .rsvd = 0xfffffc01,
956 },{ .name = "MIO_PIN_31", .addr = A_MIO_PIN_31,
957 .rsvd = 0xfffffc01,
958 },{ .name = "MIO_PIN_32", .addr = A_MIO_PIN_32,
959 .rsvd = 0xfffffc01,
960 },{ .name = "MIO_PIN_33", .addr = A_MIO_PIN_33,
961 .rsvd = 0xfffffc01,
962 },{ .name = "MIO_PIN_34", .addr = A_MIO_PIN_34,
963 .rsvd = 0xfffffc01,
964 },{ .name = "MIO_PIN_35", .addr = A_MIO_PIN_35,
965 .rsvd = 0xfffffc01,
966 },{ .name = "MIO_PIN_36", .addr = A_MIO_PIN_36,
967 .rsvd = 0xfffffc01,
968 },{ .name = "MIO_PIN_37", .addr = A_MIO_PIN_37,
969 .rsvd = 0xfffffc01,
970 },{ .name = "MIO_PIN_38", .addr = A_MIO_PIN_38,
971 .rsvd = 0xfffffc01,
972 },{ .name = "MIO_PIN_39", .addr = A_MIO_PIN_39,
973 .rsvd = 0xfffffc01,
974 },{ .name = "MIO_PIN_40", .addr = A_MIO_PIN_40,
975 .rsvd = 0xfffffc01,
976 },{ .name = "MIO_PIN_41", .addr = A_MIO_PIN_41,
977 .rsvd = 0xfffffc01,
978 },{ .name = "MIO_PIN_42", .addr = A_MIO_PIN_42,
979 .rsvd = 0xfffffc01,
980 },{ .name = "MIO_PIN_43", .addr = A_MIO_PIN_43,
981 .rsvd = 0xfffffc01,
982 },{ .name = "MIO_PIN_44", .addr = A_MIO_PIN_44,
983 .rsvd = 0xfffffc01,
984 },{ .name = "MIO_PIN_45", .addr = A_MIO_PIN_45,
985 .rsvd = 0xfffffc01,
986 },{ .name = "MIO_PIN_46", .addr = A_MIO_PIN_46,
987 .rsvd = 0xfffffc01,
988 },{ .name = "MIO_PIN_47", .addr = A_MIO_PIN_47,
989 .rsvd = 0xfffffc01,
990 },{ .name = "MIO_PIN_48", .addr = A_MIO_PIN_48,
991 .rsvd = 0xfffffc01,
992 },{ .name = "MIO_PIN_49", .addr = A_MIO_PIN_49,
993 .rsvd = 0xfffffc01,
994 },{ .name = "MIO_PIN_50", .addr = A_MIO_PIN_50,
995 .rsvd = 0xfffffc01,
996 },{ .name = "MIO_PIN_51", .addr = A_MIO_PIN_51,
997 .rsvd = 0xfffffc01,
998 },{ .name = "BNK0_EN_RX", .addr = A_BNK0_EN_RX,
999 .reset = 0x3ffffff,
1000 .rsvd = 0xfc000000,
1001 },{ .name = "BNK0_SEL_RX0", .addr = A_BNK0_SEL_RX0,
1002 .reset = 0xffffffff,
1003 },{ .name = "BNK0_SEL_RX1", .addr = A_BNK0_SEL_RX1,
1004 .reset = 0xfffff,
1005 .rsvd = 0xfff00000,
1006 },{ .name = "BNK0_EN_RX_SCHMITT_HYST", .addr = A_BNK0_EN_RX_SCHMITT_HYST,
1007 .rsvd = 0xfc000000,
1008 },{ .name = "BNK0_EN_WK_PD", .addr = A_BNK0_EN_WK_PD,
1009 .rsvd = 0xfc000000,
1010 },{ .name = "BNK0_EN_WK_PU", .addr = A_BNK0_EN_WK_PU,
1011 .reset = 0x3ffffff,
1012 .rsvd = 0xfc000000,
1013 },{ .name = "BNK0_SEL_DRV0", .addr = A_BNK0_SEL_DRV0,
1014 .reset = 0xffffffff,
1015 },{ .name = "BNK0_SEL_DRV1", .addr = A_BNK0_SEL_DRV1,
1016 .reset = 0xfffff,
1017 .rsvd = 0xfff00000,
1018 },{ .name = "BNK0_SEL_SLEW", .addr = A_BNK0_SEL_SLEW,
1019 .rsvd = 0xfc000000,
1020 },{ .name = "BNK0_EN_DFT_OPT_INV", .addr = A_BNK0_EN_DFT_OPT_INV,
1021 .rsvd = 0xfc000000,
1022 },{ .name = "BNK0_EN_PAD2PAD_LOOPBACK",
1023 .addr = A_BNK0_EN_PAD2PAD_LOOPBACK,
1024 .rsvd = 0xffffe000,
1025 },{ .name = "BNK0_RX_SPARE0", .addr = A_BNK0_RX_SPARE0,
1026 },{ .name = "BNK0_RX_SPARE1", .addr = A_BNK0_RX_SPARE1,
1027 .rsvd = 0xfff00000,
1028 },{ .name = "BNK0_TX_SPARE0", .addr = A_BNK0_TX_SPARE0,
1029 },{ .name = "BNK0_TX_SPARE1", .addr = A_BNK0_TX_SPARE1,
1030 .rsvd = 0xfff00000,
1031 },{ .name = "BNK0_SEL_EN1P8", .addr = A_BNK0_SEL_EN1P8,
1032 .rsvd = 0xfffffffe,
1033 },{ .name = "BNK0_EN_B_POR_DETECT", .addr = A_BNK0_EN_B_POR_DETECT,
1034 .rsvd = 0xfffffffe,
1035 },{ .name = "BNK0_LPF_BYP_POR_DETECT", .addr = A_BNK0_LPF_BYP_POR_DETECT,
1036 .reset = 0x1,
1037 .rsvd = 0xfffffffe,
1038 },{ .name = "BNK0_EN_LATCH", .addr = A_BNK0_EN_LATCH,
1039 .rsvd = 0xfffffffe,
1040 },{ .name = "BNK0_VBG_LPF_BYP_B", .addr = A_BNK0_VBG_LPF_BYP_B,
1041 .reset = 0x1,
1042 .rsvd = 0xfffffffe,
1043 },{ .name = "BNK0_EN_AMP_B", .addr = A_BNK0_EN_AMP_B,
1044 .rsvd = 0xfffffffc,
1045 },{ .name = "BNK0_SPARE_BIAS", .addr = A_BNK0_SPARE_BIAS,
1046 .rsvd = 0xfffffff0,
1047 },{ .name = "BNK0_DRIVER_BIAS", .addr = A_BNK0_DRIVER_BIAS,
1048 .rsvd = 0xffff8000,
1049 },{ .name = "BNK0_VMODE", .addr = A_BNK0_VMODE,
1050 .rsvd = 0xfffffffe,
1051 .ro = 0x1,
1052 },{ .name = "BNK0_SEL_AUX_IO_RX", .addr = A_BNK0_SEL_AUX_IO_RX,
1053 .rsvd = 0xfc000000,
1054 },{ .name = "BNK0_EN_TX_HS_MODE", .addr = A_BNK0_EN_TX_HS_MODE,
1055 .rsvd = 0xfc000000,
1056 },{ .name = "MIO_MST_TRI0", .addr = A_MIO_MST_TRI0,
1057 .reset = 0x3ffffff,
1058 .rsvd = 0xfc000000,
1059 },{ .name = "MIO_MST_TRI1", .addr = A_MIO_MST_TRI1,
1060 .reset = 0x3ffffff,
1061 .rsvd = 0xfc000000,
1062 },{ .name = "BNK1_EN_RX", .addr = A_BNK1_EN_RX,
1063 .reset = 0x3ffffff,
1064 .rsvd = 0xfc000000,
1065 },{ .name = "BNK1_SEL_RX0", .addr = A_BNK1_SEL_RX0,
1066 .reset = 0xffffffff,
1067 },{ .name = "BNK1_SEL_RX1", .addr = A_BNK1_SEL_RX1,
1068 .reset = 0xfffff,
1069 .rsvd = 0xfff00000,
1070 },{ .name = "BNK1_EN_RX_SCHMITT_HYST", .addr = A_BNK1_EN_RX_SCHMITT_HYST,
1071 .rsvd = 0xfc000000,
1072 },{ .name = "BNK1_EN_WK_PD", .addr = A_BNK1_EN_WK_PD,
1073 .rsvd = 0xfc000000,
1074 },{ .name = "BNK1_EN_WK_PU", .addr = A_BNK1_EN_WK_PU,
1075 .reset = 0x3ffffff,
1076 .rsvd = 0xfc000000,
1077 },{ .name = "BNK1_SEL_DRV0", .addr = A_BNK1_SEL_DRV0,
1078 .reset = 0xffffffff,
1079 },{ .name = "BNK1_SEL_DRV1", .addr = A_BNK1_SEL_DRV1,
1080 .reset = 0xfffff,
1081 .rsvd = 0xfff00000,
1082 },{ .name = "BNK1_SEL_SLEW", .addr = A_BNK1_SEL_SLEW,
1083 .rsvd = 0xfc000000,
1084 },{ .name = "BNK1_EN_DFT_OPT_INV", .addr = A_BNK1_EN_DFT_OPT_INV,
1085 .rsvd = 0xfc000000,
1086 },{ .name = "BNK1_EN_PAD2PAD_LOOPBACK",
1087 .addr = A_BNK1_EN_PAD2PAD_LOOPBACK,
1088 .rsvd = 0xffffe000,
1089 },{ .name = "BNK1_RX_SPARE0", .addr = A_BNK1_RX_SPARE0,
1090 },{ .name = "BNK1_RX_SPARE1", .addr = A_BNK1_RX_SPARE1,
1091 .rsvd = 0xfff00000,
1092 },{ .name = "BNK1_TX_SPARE0", .addr = A_BNK1_TX_SPARE0,
1093 },{ .name = "BNK1_TX_SPARE1", .addr = A_BNK1_TX_SPARE1,
1094 .rsvd = 0xfff00000,
1095 },{ .name = "BNK1_SEL_EN1P8", .addr = A_BNK1_SEL_EN1P8,
1096 .rsvd = 0xfffffffe,
1097 },{ .name = "BNK1_EN_B_POR_DETECT", .addr = A_BNK1_EN_B_POR_DETECT,
1098 .rsvd = 0xfffffffe,
1099 },{ .name = "BNK1_LPF_BYP_POR_DETECT", .addr = A_BNK1_LPF_BYP_POR_DETECT,
1100 .reset = 0x1,
1101 .rsvd = 0xfffffffe,
1102 },{ .name = "BNK1_EN_LATCH", .addr = A_BNK1_EN_LATCH,
1103 .rsvd = 0xfffffffe,
1104 },{ .name = "BNK1_VBG_LPF_BYP_B", .addr = A_BNK1_VBG_LPF_BYP_B,
1105 .reset = 0x1,
1106 .rsvd = 0xfffffffe,
1107 },{ .name = "BNK1_EN_AMP_B", .addr = A_BNK1_EN_AMP_B,
1108 .rsvd = 0xfffffffc,
1109 },{ .name = "BNK1_SPARE_BIAS", .addr = A_BNK1_SPARE_BIAS,
1110 .rsvd = 0xfffffff0,
1111 },{ .name = "BNK1_DRIVER_BIAS", .addr = A_BNK1_DRIVER_BIAS,
1112 .rsvd = 0xffff8000,
1113 },{ .name = "BNK1_VMODE", .addr = A_BNK1_VMODE,
1114 .rsvd = 0xfffffffe,
1115 .ro = 0x1,
1116 },{ .name = "BNK1_SEL_AUX_IO_RX", .addr = A_BNK1_SEL_AUX_IO_RX,
1117 .rsvd = 0xfc000000,
1118 },{ .name = "BNK1_EN_TX_HS_MODE", .addr = A_BNK1_EN_TX_HS_MODE,
1119 .rsvd = 0xfc000000,
1120 },{ .name = "SD0_CLK_CTRL", .addr = A_SD0_CLK_CTRL,
1121 .rsvd = 0xfffffff8,
1122 },{ .name = "SD0_CTRL_REG", .addr = A_SD0_CTRL_REG,
1123 .rsvd = 0xfffffffe,
1124 .pre_write = sd0_ctrl_reg_prew,
1125 },{ .name = "SD0_CONFIG_REG1", .addr = A_SD0_CONFIG_REG1,
1126 .reset = 0x3250,
1127 .rsvd = 0xffff8000,
1128 },{ .name = "SD0_CONFIG_REG2", .addr = A_SD0_CONFIG_REG2,
1129 .reset = 0xffc,
1130 .rsvd = 0xffffc000,
1131 },{ .name = "SD0_CONFIG_REG3", .addr = A_SD0_CONFIG_REG3,
1132 .reset = 0x407,
1133 .rsvd = 0xfffff800,
1134 },{ .name = "SD0_INITPRESET", .addr = A_SD0_INITPRESET,
1135 .reset = 0x100,
1136 .rsvd = 0xffffe000,
1137 },{ .name = "SD0_DSPPRESET", .addr = A_SD0_DSPPRESET,
1138 .reset = 0x4,
1139 .rsvd = 0xffffe000,
1140 },{ .name = "SD0_HSPDPRESET", .addr = A_SD0_HSPDPRESET,
1141 .reset = 0x2,
1142 .rsvd = 0xffffe000,
1143 },{ .name = "SD0_SDR12PRESET", .addr = A_SD0_SDR12PRESET,
1144 .reset = 0x4,
1145 .rsvd = 0xffffe000,
1146 },{ .name = "SD0_SDR25PRESET", .addr = A_SD0_SDR25PRESET,
1147 .reset = 0x2,
1148 .rsvd = 0xffffe000,
1149 },{ .name = "SD0_SDR50PRSET", .addr = A_SD0_SDR50PRSET,
1150 .reset = 0x1,
1151 .rsvd = 0xffffe000,
1152 },{ .name = "SD0_SDR104PRST", .addr = A_SD0_SDR104PRST,
1153 .rsvd = 0xffffe000,
1154 },{ .name = "SD0_DDR50PRESET", .addr = A_SD0_DDR50PRESET,
1155 .reset = 0x2,
1156 .rsvd = 0xffffe000,
1157 },{ .name = "SD0_MAXCUR1P8", .addr = A_SD0_MAXCUR1P8,
1158 .rsvd = 0xffffff00,
1159 },{ .name = "SD0_MAXCUR3P0", .addr = A_SD0_MAXCUR3P0,
1160 .rsvd = 0xffffff00,
1161 },{ .name = "SD0_MAXCUR3P3", .addr = A_SD0_MAXCUR3P3,
1162 .rsvd = 0xffffff00,
1163 },{ .name = "SD0_DLL_CTRL", .addr = A_SD0_DLL_CTRL,
1164 .reset = 0x1,
1165 .rsvd = 0xfffffc00,
1166 .ro = 0x19,
1167 },{ .name = "SD0_CDN_CTRL", .addr = A_SD0_CDN_CTRL,
1168 .rsvd = 0xfffffffe,
1169 },{ .name = "SD0_DLL_TEST", .addr = A_SD0_DLL_TEST,
1170 .rsvd = 0xff000000,
1171 },{ .name = "SD0_RX_TUNING_SEL", .addr = A_SD0_RX_TUNING_SEL,
1172 .rsvd = 0xfffffe00,
1173 .ro = 0x1ff,
1174 },{ .name = "SD0_DLL_DIV_MAP0", .addr = A_SD0_DLL_DIV_MAP0,
1175 .reset = 0x50505050,
1176 },{ .name = "SD0_DLL_DIV_MAP1", .addr = A_SD0_DLL_DIV_MAP1,
1177 .reset = 0x50505050,
1178 },{ .name = "SD0_IOU_COHERENT_CTRL", .addr = A_SD0_IOU_COHERENT_CTRL,
1179 .rsvd = 0xfffffff0,
1180 },{ .name = "SD0_IOU_INTERCONNECT_ROUTE",
1181 .addr = A_SD0_IOU_INTERCONNECT_ROUTE,
1182 .rsvd = 0xfffffffe,
1183 },{ .name = "SD0_IOU_RAM", .addr = A_SD0_IOU_RAM,
1184 .reset = 0x24,
1185 .rsvd = 0xffffff80,
1186 },{ .name = "SD0_IOU_INTERCONNECT_QOS",
1187 .addr = A_SD0_IOU_INTERCONNECT_QOS,
1188 .rsvd = 0xfffffff0,
1189 },{ .name = "SD1_CLK_CTRL", .addr = A_SD1_CLK_CTRL,
1190 .rsvd = 0xfffffffc,
1191 },{ .name = "SD1_CTRL_REG", .addr = A_SD1_CTRL_REG,
1192 .rsvd = 0xfffffffe,
1193 .pre_write = sd1_ctrl_reg_prew,
1194 },{ .name = "SD1_CONFIG_REG1", .addr = A_SD1_CONFIG_REG1,
1195 .reset = 0x3250,
1196 .rsvd = 0xffff8000,
1197 },{ .name = "SD1_CONFIG_REG2", .addr = A_SD1_CONFIG_REG2,
1198 .reset = 0xffc,
1199 .rsvd = 0xffffc000,
1200 },{ .name = "SD1_CONFIG_REG3", .addr = A_SD1_CONFIG_REG3,
1201 .reset = 0x407,
1202 .rsvd = 0xfffff800,
1203 },{ .name = "SD1_INITPRESET", .addr = A_SD1_INITPRESET,
1204 .reset = 0x100,
1205 .rsvd = 0xffffe000,
1206 },{ .name = "SD1_DSPPRESET", .addr = A_SD1_DSPPRESET,
1207 .reset = 0x4,
1208 .rsvd = 0xffffe000,
1209 },{ .name = "SD1_HSPDPRESET", .addr = A_SD1_HSPDPRESET,
1210 .reset = 0x2,
1211 .rsvd = 0xffffe000,
1212 },{ .name = "SD1_SDR12PRESET", .addr = A_SD1_SDR12PRESET,
1213 .reset = 0x4,
1214 .rsvd = 0xffffe000,
1215 },{ .name = "SD1_SDR25PRESET", .addr = A_SD1_SDR25PRESET,
1216 .reset = 0x2,
1217 .rsvd = 0xffffe000,
1218 },{ .name = "SD1_SDR50PRSET", .addr = A_SD1_SDR50PRSET,
1219 .reset = 0x1,
1220 .rsvd = 0xffffe000,
1221 },{ .name = "SD1_SDR104PRST", .addr = A_SD1_SDR104PRST,
1222 .rsvd = 0xffffe000,
1223 },{ .name = "SD1_DDR50PRESET", .addr = A_SD1_DDR50PRESET,
1224 .reset = 0x2,
1225 .rsvd = 0xffffe000,
1226 },{ .name = "SD1_MAXCUR1P8", .addr = A_SD1_MAXCUR1P8,
1227 .rsvd = 0xffffff00,
1228 },{ .name = "SD1_MAXCUR3P0", .addr = A_SD1_MAXCUR3P0,
1229 .rsvd = 0xffffff00,
1230 },{ .name = "SD1_MAXCUR3P3", .addr = A_SD1_MAXCUR3P3,
1231 .rsvd = 0xffffff00,
1232 },{ .name = "SD1_DLL_CTRL", .addr = A_SD1_DLL_CTRL,
1233 .reset = 0x1,
1234 .rsvd = 0xfffffc00,
1235 .ro = 0x19,
1236 },{ .name = "SD1_CDN_CTRL", .addr = A_SD1_CDN_CTRL,
1237 .rsvd = 0xfffffffe,
1238 },{ .name = "SD1_DLL_TEST", .addr = A_SD1_DLL_TEST,
1239 .rsvd = 0xff000000,
1240 },{ .name = "SD1_RX_TUNING_SEL", .addr = A_SD1_RX_TUNING_SEL,
1241 .rsvd = 0xfffffe00,
1242 .ro = 0x1ff,
1243 },{ .name = "SD1_DLL_DIV_MAP0", .addr = A_SD1_DLL_DIV_MAP0,
1244 .reset = 0x50505050,
1245 },{ .name = "SD1_DLL_DIV_MAP1", .addr = A_SD1_DLL_DIV_MAP1,
1246 .reset = 0x50505050,
1247 },{ .name = "SD1_IOU_COHERENT_CTRL", .addr = A_SD1_IOU_COHERENT_CTRL,
1248 .rsvd = 0xfffffff0,
1249 },{ .name = "SD1_IOU_INTERCONNECT_ROUTE",
1250 .addr = A_SD1_IOU_INTERCONNECT_ROUTE,
1251 .rsvd = 0xfffffffe,
1252 },{ .name = "SD1_IOU_RAM", .addr = A_SD1_IOU_RAM,
1253 .reset = 0x24,
1254 .rsvd = 0xffffff80,
1255 },{ .name = "SD1_IOU_INTERCONNECT_QOS",
1256 .addr = A_SD1_IOU_INTERCONNECT_QOS,
1257 .rsvd = 0xfffffff0,
1258 },{ .name = "OSPI_QSPI_IOU_AXI_MUX_SEL",
1259 .addr = A_OSPI_QSPI_IOU_AXI_MUX_SEL,
1260 .reset = 0x1,
1261 .rsvd = 0xfffffffc,
1262 .pre_write = ospi_qspi_iou_axi_mux_sel_prew,
1263 },{ .name = "QSPI_IOU_COHERENT_CTRL", .addr = A_QSPI_IOU_COHERENT_CTRL,
1264 .rsvd = 0xfffffff0,
1265 },{ .name = "QSPI_IOU_INTERCONNECT_ROUTE",
1266 .addr = A_QSPI_IOU_INTERCONNECT_ROUTE,
1267 .rsvd = 0xfffffffe,
1268 },{ .name = "QSPI_IOU_RAM", .addr = A_QSPI_IOU_RAM,
1269 .reset = 0x1224,
1270 .rsvd = 0xffffc000,
1271 },{ .name = "QSPI_IOU_INTERCONNECT_QOS",
1272 .addr = A_QSPI_IOU_INTERCONNECT_QOS,
1273 .rsvd = 0xfffffff0,
1274 },{ .name = "OSPI_IOU_COHERENT_CTRL", .addr = A_OSPI_IOU_COHERENT_CTRL,
1275 .rsvd = 0xfffffff0,
1276 },{ .name = "OSPI_IOU_INTERCONNECT_ROUTE",
1277 .addr = A_OSPI_IOU_INTERCONNECT_ROUTE,
1278 .rsvd = 0xfffffffe,
1279 },{ .name = "OSPI_IOU_RAM", .addr = A_OSPI_IOU_RAM,
1280 .reset = 0xa,
1281 .rsvd = 0xffffffc0,
1282 },{ .name = "OSPI_IOU_INTERCONNECT_QOS",
1283 .addr = A_OSPI_IOU_INTERCONNECT_QOS,
1284 .rsvd = 0xfffffff0,
1285 },{ .name = "OSPI_REFCLK_DLY_CTRL", .addr = A_OSPI_REFCLK_DLY_CTRL,
1286 .reset = 0x13,
1287 .rsvd = 0xffffffe0,
1288 },{ .name = "CUR_PWR_ST", .addr = A_CUR_PWR_ST,
1289 .rsvd = 0xfffffffc,
1290 .ro = 0x3,
1291 },{ .name = "CONNECT_ST", .addr = A_CONNECT_ST,
1292 .rsvd = 0xfffffffe,
1293 .ro = 0x1,
1294 },{ .name = "PW_STATE_REQ", .addr = A_PW_STATE_REQ,
1295 .rsvd = 0xfffffffc,
1296 },{ .name = "HOST_U2_PORT_DISABLE", .addr = A_HOST_U2_PORT_DISABLE,
1297 .rsvd = 0xfffffffe,
1298 },{ .name = "DBG_U2PMU", .addr = A_DBG_U2PMU,
1299 .ro = 0xffffffff,
1300 },{ .name = "DBG_U2PMU_EXT1", .addr = A_DBG_U2PMU_EXT1,
1301 .ro = 0xffffffff,
1302 },{ .name = "DBG_U2PMU_EXT2", .addr = A_DBG_U2PMU_EXT2,
1303 .rsvd = 0xfffffff0,
1304 .ro = 0xf,
1305 },{ .name = "PME_GEN_U2PMU", .addr = A_PME_GEN_U2PMU,
1306 .rsvd = 0xfffffffe,
1307 .ro = 0x1,
1308 },{ .name = "PWR_CONFIG_USB2", .addr = A_PWR_CONFIG_USB2,
1309 .rsvd = 0xc0000000,
1310 },{ .name = "PHY_HUB", .addr = A_PHY_HUB,
1311 .rsvd = 0xfffffffc,
1312 .ro = 0x2,
1313 },{ .name = "CTRL", .addr = A_CTRL,
1314 },{ .name = "ISR", .addr = A_ISR,
1315 .w1c = 0x1,
1316 .post_write = isr_postw,
1317 },{ .name = "IMR", .addr = A_IMR,
1318 .reset = 0x1,
1319 .ro = 0x1,
1320 },{ .name = "IER", .addr = A_IER,
1321 .pre_write = ier_prew,
1322 },{ .name = "IDR", .addr = A_IDR,
1323 .pre_write = idr_prew,
1324 },{ .name = "ITR", .addr = A_ITR,
1325 .pre_write = itr_prew,
1326 },{ .name = "PARITY_ISR", .addr = A_PARITY_ISR,
1327 .w1c = 0x1fff,
1328 .post_write = parity_isr_postw,
1329 },{ .name = "PARITY_IMR", .addr = A_PARITY_IMR,
1330 .reset = 0x1fff,
1331 .ro = 0x1fff,
1332 },{ .name = "PARITY_IER", .addr = A_PARITY_IER,
1333 .pre_write = parity_ier_prew,
1334 },{ .name = "PARITY_IDR", .addr = A_PARITY_IDR,
1335 .pre_write = parity_idr_prew,
1336 },{ .name = "PARITY_ITR", .addr = A_PARITY_ITR,
1337 .pre_write = parity_itr_prew,
1338 },{ .name = "WPROT0", .addr = A_WPROT0,
1339 .reset = 0x1,
1340 }
1341 };
1342
1343 static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType type)
1344 {
1345 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);
1346 unsigned int i;
1347
1348 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
1349 register_reset(&s->regs_info[i]);
1350 }
1351 }
1352
1353 static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj, ResetType type)
1354 {
1355 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);
1356
1357 parity_imr_update_irq(s);
1358 imr_update_irq(s);
1359
1360 /*
1361 * Setup OSPI_QSPI mux
1362 * By default axi slave interface is enabled for ospi-dma
1363 */
1364 qemu_set_irq(s->ospi_mux_sel, 0);
1365 qemu_set_irq(s->qspi_ospi_mux_sel, 1);
1366 }
1367
1368 static const MemoryRegionOps pmc_iou_slcr_ops = {
1369 .read = register_read_memory,
1370 .write = register_write_memory,
1371 .endianness = DEVICE_LITTLE_ENDIAN,
1372 .valid = {
1373 .min_access_size = 4,
1374 .max_access_size = 4,
1375 },
1376 };
1377
1378 static void xlnx_versal_pmc_iou_slcr_realize(DeviceState *dev, Error **errp)
1379 {
1380 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(dev);
1381
1382 qdev_init_gpio_out_named(dev, s->sd_emmc_sel, "sd-emmc-sel", 2);
1383 qdev_init_gpio_out_named(dev, &s->qspi_ospi_mux_sel,
1384 "qspi-ospi-mux-sel", 1);
1385 qdev_init_gpio_out_named(dev, &s->ospi_mux_sel, "ospi-mux-sel", 1);
1386 }
1387
1388 static void xlnx_versal_pmc_iou_slcr_init(Object *obj)
1389 {
1390 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);
1391 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1392 RegisterInfoArray *reg_array;
1393
1394 memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_PMC_IOU_SLCR,
1395 XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4);
1396 reg_array =
1397 register_init_block32(DEVICE(obj), pmc_iou_slcr_regs_info,
1398 ARRAY_SIZE(pmc_iou_slcr_regs_info),
1399 s->regs_info, s->regs,
1400 &pmc_iou_slcr_ops,
1401 XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG,
1402 XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4);
1403 memory_region_add_subregion(&s->iomem,
1404 0x0,
1405 &reg_array->mem);
1406 sysbus_init_mmio(sbd, &s->iomem);
1407 sysbus_init_irq(sbd, &s->irq_parity_imr);
1408 sysbus_init_irq(sbd, &s->irq_imr);
1409 }
1410
1411 static const VMStateDescription vmstate_pmc_iou_slcr = {
1412 .name = TYPE_XILINX_VERSAL_PMC_IOU_SLCR,
1413 .version_id = 1,
1414 .minimum_version_id = 1,
1415 .fields = (const VMStateField[]) {
1416 VMSTATE_UINT32_ARRAY(regs, XlnxVersalPmcIouSlcr,
1417 XILINX_VERSAL_PMC_IOU_SLCR_R_MAX),
1418 VMSTATE_END_OF_LIST(),
1419 }
1420 };
1421
1422 static void xlnx_versal_pmc_iou_slcr_class_init(ObjectClass *klass,
1423 const void *data)
1424 {
1425 DeviceClass *dc = DEVICE_CLASS(klass);
1426 ResettableClass *rc = RESETTABLE_CLASS(klass);
1427
1428 dc->realize = xlnx_versal_pmc_iou_slcr_realize;
1429 dc->vmsd = &vmstate_pmc_iou_slcr;
1430 rc->phases.enter = xlnx_versal_pmc_iou_slcr_reset_init;
1431 rc->phases.hold = xlnx_versal_pmc_iou_slcr_reset_hold;
1432 }
1433
1434 static const TypeInfo xlnx_versal_pmc_iou_slcr_info = {
1435 .name = TYPE_XILINX_VERSAL_PMC_IOU_SLCR,
1436 .parent = TYPE_SYS_BUS_DEVICE,
1437 .instance_size = sizeof(XlnxVersalPmcIouSlcr),
1438 .class_init = xlnx_versal_pmc_iou_slcr_class_init,
1439 .instance_init = xlnx_versal_pmc_iou_slcr_init,
1440 };
1441
1442 static void xlnx_versal_pmc_iou_slcr_register_types(void)
1443 {
1444 type_register_static(&xlnx_versal_pmc_iou_slcr_info);
1445 }
1446
1447 type_init(xlnx_versal_pmc_iou_slcr_register_types)