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1 /*
2 * QEMU model of the ZynqMP APU Control.
3 *
4 * Copyright (c) 2013-2022 Xilinx Inc
5 * SPDX-License-Identifier: GPL-2.0-or-later
6 *
7 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
8 * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9 */
10
11 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/log.h"
14 #include "migration/vmstate.h"
15 #include "hw/core/qdev-properties.h"
16 #include "hw/core/sysbus.h"
17 #include "hw/core/irq.h"
18 #include "hw/core/register.h"
19
20 #include "qemu/bitops.h"
21
22 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
23
24 #ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
25 #define XILINX_ZYNQMP_APU_ERR_DEBUG 0
26 #endif
27
28 static void update_wfi_out(void *opaque)
29 {
30 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
31 unsigned int i, wfi_pending;
32
33 wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
34 for (i = 0; i < APU_MAX_CPU; i++) {
35 qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
36 }
37 }
38
39 static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
40 {
41 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
42 int i;
43
44 for (i = 0; i < APU_MAX_CPU; ++i) {
45 uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
46 ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
47 if (s->cpus[i]) {
48 object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
49 &error_abort);
50 }
51 }
52 }
53
54 static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
55 {
56 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
57 unsigned int i, new;
58
59 for (i = 0; i < APU_MAX_CPU; i++) {
60 new = val & (1 << i);
61 /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
62 if (new != (s->cpu_pwrdwn_req & (1 << i))) {
63 qemu_set_irq(s->cpu_power_status[i], !!new);
64 }
65 s->cpu_pwrdwn_req &= ~(1 << i);
66 s->cpu_pwrdwn_req |= new;
67 }
68 update_wfi_out(s);
69 }
70
71 static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
72 {
73 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
74 qemu_set_irq(s->irq_imr, pending);
75 }
76
77 static void isr_postw(RegisterInfo *reg, uint64_t val64)
78 {
79 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
80 imr_update_irq(s);
81 }
82
83 static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
84 {
85 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
86 uint32_t val = val64;
87
88 s->regs[R_IMR] &= ~val;
89 imr_update_irq(s);
90 return 0;
91 }
92
93 static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
94 {
95 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
96 uint32_t val = val64;
97
98 s->regs[R_IMR] |= val;
99 imr_update_irq(s);
100 return 0;
101 }
102
103 static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
104 #define RVBAR_REGDEF(n) \
105 { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
106 .reset = 0xffff0000ul, \
107 .post_write = zynqmp_apu_rvbar_post_write, \
108 },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
109 .post_write = zynqmp_apu_rvbar_post_write, \
110 }
111 { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
112 },{ .name = "ISR", .addr = A_ISR,
113 .w1c = 0x1,
114 .post_write = isr_postw,
115 },{ .name = "IMR", .addr = A_IMR,
116 .reset = 0x1,
117 .ro = 0x1,
118 },{ .name = "IEN", .addr = A_IEN,
119 .pre_write = ien_prew,
120 },{ .name = "IDS", .addr = A_IDS,
121 .pre_write = ids_prew,
122 },{ .name = "CONFIG_0", .addr = A_CONFIG_0,
123 .reset = 0xf0f,
124 },{ .name = "CONFIG_1", .addr = A_CONFIG_1,
125 },
126 RVBAR_REGDEF(0),
127 RVBAR_REGDEF(1),
128 RVBAR_REGDEF(2),
129 RVBAR_REGDEF(3),
130 { .name = "ACE_CTRL", .addr = A_ACE_CTRL,
131 .reset = 0xf000f,
132 },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
133 },{ .name = "PWRCTL", .addr = A_PWRCTL,
134 .post_write = zynqmp_apu_pwrctl_post_write,
135 },{ .name = "PWRSTAT", .addr = A_PWRSTAT,
136 .ro = 0x3000f,
137 }
138 };
139
140 static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
141 {
142 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
143 int i;
144
145 for (i = 0; i < APU_R_MAX; ++i) {
146 register_reset(&s->regs_info[i]);
147 }
148
149 s->cpu_pwrdwn_req = 0;
150 s->cpu_in_wfi = 0;
151 }
152
153 static void zynqmp_apu_reset_hold(Object *obj, ResetType type)
154 {
155 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
156
157 update_wfi_out(s);
158 imr_update_irq(s);
159 }
160
161 static const MemoryRegionOps zynqmp_apu_ops = {
162 .read = register_read_memory,
163 .write = register_write_memory,
164 .endianness = DEVICE_LITTLE_ENDIAN,
165 .valid = {
166 .min_access_size = 4,
167 .max_access_size = 4,
168 }
169 };
170
171 static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
172 {
173 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
174
175 s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
176 update_wfi_out(s);
177 }
178
179 static void zynqmp_apu_init(Object *obj)
180 {
181 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
182 RegisterInfoArray *reg_array;
183 int i;
184
185 reg_array =
186 register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
187 ARRAY_SIZE(zynqmp_apu_regs_info),
188 s->regs_info, s->regs,
189 &zynqmp_apu_ops,
190 XILINX_ZYNQMP_APU_ERR_DEBUG,
191 APU_R_MAX * 4);
192 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &reg_array->mem);
193 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
194
195 for (i = 0; i < APU_MAX_CPU; ++i) {
196 g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
197 object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
198 (Object **)&s->cpus[i],
199 qdev_prop_allow_set_link_before_realize,
200 OBJ_PROP_LINK_STRONG);
201 }
202
203 /* wfi_out is used to connect to PMU GPIs. */
204 qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
205 /* CPU_POWER_STATUS is used to connect to INTC redirect. */
206 qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
207 "CPU_POWER_STATUS", 4);
208 /* wfi_in is used as input from CPUs as wfi request. */
209 qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
210 }
211
212 static const VMStateDescription vmstate_zynqmp_apu = {
213 .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
214 .version_id = 1,
215 .minimum_version_id = 1,
216 .fields = (const VMStateField[]) {
217 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
218 VMSTATE_END_OF_LIST(),
219 }
220 };
221
222 static void zynqmp_apu_class_init(ObjectClass *klass, const void *data)
223 {
224 ResettableClass *rc = RESETTABLE_CLASS(klass);
225 DeviceClass *dc = DEVICE_CLASS(klass);
226
227 dc->vmsd = &vmstate_zynqmp_apu;
228
229 rc->phases.enter = zynqmp_apu_reset_enter;
230 rc->phases.hold = zynqmp_apu_reset_hold;
231 }
232
233 static const TypeInfo zynqmp_apu_info = {
234 .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
235 .parent = TYPE_SYS_BUS_DEVICE,
236 .instance_size = sizeof(XlnxZynqMPAPUCtrl),
237 .class_init = zynqmp_apu_class_init,
238 .instance_init = zynqmp_apu_init,
239 };
240
241 static void zynqmp_apu_register_types(void)
242 {
243 type_register_static(&zynqmp_apu_info);
244 }
245
246 type_init(zynqmp_apu_register_types)