| 1 | /* |
| 2 | * Status and system control registers for Xilinx Zynq Platform |
| 3 | * |
| 4 | * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> |
| 5 | * Copyright (c) 2012 PetaLogix Pty Ltd. |
| 6 | * Based on hw/arm_sysctl.c, written by Paul Brook |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * as published by the Free Software Foundation; either version |
| 11 | * 2 of the License, or (at your option) any later version. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along |
| 14 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | #include "qemu/timer.h" |
| 19 | #include "system/runstate.h" |
| 20 | #include "hw/core/sysbus.h" |
| 21 | #include "migration/vmstate.h" |
| 22 | #include "qemu/log.h" |
| 23 | #include "qemu/module.h" |
| 24 | #include "hw/core/registerfields.h" |
| 25 | #include "hw/core/qdev-clock.h" |
| 26 | #include "qom/object.h" |
| 27 | #include "hw/core/qdev-properties.h" |
| 28 | #include "qapi/error.h" |
| 29 | |
| 30 | #ifndef ZYNQ_SLCR_ERR_DEBUG |
| 31 | #define ZYNQ_SLCR_ERR_DEBUG 0 |
| 32 | #endif |
| 33 | |
| 34 | #define DB_PRINT(...) do { \ |
| 35 | if (ZYNQ_SLCR_ERR_DEBUG) { \ |
| 36 | fprintf(stderr, ": %s: ", __func__); \ |
| 37 | fprintf(stderr, ## __VA_ARGS__); \ |
| 38 | } \ |
| 39 | } while (0) |
| 40 | |
| 41 | #define XILINX_LOCK_KEY 0x767b |
| 42 | #define XILINX_UNLOCK_KEY 0xdf0d |
| 43 | |
| 44 | REG32(SCL, 0x000) |
| 45 | REG32(LOCK, 0x004) |
| 46 | REG32(UNLOCK, 0x008) |
| 47 | REG32(LOCKSTA, 0x00c) |
| 48 | |
| 49 | REG32(ARM_PLL_CTRL, 0x100) |
| 50 | REG32(DDR_PLL_CTRL, 0x104) |
| 51 | REG32(IO_PLL_CTRL, 0x108) |
| 52 | /* fields for [ARM|DDR|IO]_PLL_CTRL registers */ |
| 53 | FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1) |
| 54 | FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1) |
| 55 | FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1) |
| 56 | FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1) |
| 57 | FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7) |
| 58 | REG32(PLL_STATUS, 0x10c) |
| 59 | REG32(ARM_PLL_CFG, 0x110) |
| 60 | REG32(DDR_PLL_CFG, 0x114) |
| 61 | REG32(IO_PLL_CFG, 0x118) |
| 62 | |
| 63 | REG32(ARM_CLK_CTRL, 0x120) |
| 64 | REG32(DDR_CLK_CTRL, 0x124) |
| 65 | REG32(DCI_CLK_CTRL, 0x128) |
| 66 | REG32(APER_CLK_CTRL, 0x12c) |
| 67 | REG32(USB0_CLK_CTRL, 0x130) |
| 68 | REG32(USB1_CLK_CTRL, 0x134) |
| 69 | REG32(GEM0_RCLK_CTRL, 0x138) |
| 70 | REG32(GEM1_RCLK_CTRL, 0x13c) |
| 71 | REG32(GEM0_CLK_CTRL, 0x140) |
| 72 | REG32(GEM1_CLK_CTRL, 0x144) |
| 73 | REG32(SMC_CLK_CTRL, 0x148) |
| 74 | REG32(LQSPI_CLK_CTRL, 0x14c) |
| 75 | REG32(SDIO_CLK_CTRL, 0x150) |
| 76 | REG32(UART_CLK_CTRL, 0x154) |
| 77 | FIELD(UART_CLK_CTRL, CLKACT0, 0, 1) |
| 78 | FIELD(UART_CLK_CTRL, CLKACT1, 1, 1) |
| 79 | FIELD(UART_CLK_CTRL, SRCSEL, 4, 2) |
| 80 | FIELD(UART_CLK_CTRL, DIVISOR, 8, 6) |
| 81 | REG32(SPI_CLK_CTRL, 0x158) |
| 82 | REG32(CAN_CLK_CTRL, 0x15c) |
| 83 | REG32(CAN_MIOCLK_CTRL, 0x160) |
| 84 | REG32(DBG_CLK_CTRL, 0x164) |
| 85 | REG32(PCAP_CLK_CTRL, 0x168) |
| 86 | REG32(TOPSW_CLK_CTRL, 0x16c) |
| 87 | |
| 88 | #define FPGA_CTRL_REGS(n, start) \ |
| 89 | REG32(FPGA ## n ## _CLK_CTRL, (start)) \ |
| 90 | REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\ |
| 91 | REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\ |
| 92 | REG32(FPGA ## n ## _THR_STA, (start) + 0xc) |
| 93 | FPGA_CTRL_REGS(0, 0x170) |
| 94 | FPGA_CTRL_REGS(1, 0x180) |
| 95 | FPGA_CTRL_REGS(2, 0x190) |
| 96 | FPGA_CTRL_REGS(3, 0x1a0) |
| 97 | |
| 98 | REG32(BANDGAP_TRIP, 0x1b8) |
| 99 | REG32(PLL_PREDIVISOR, 0x1c0) |
| 100 | REG32(CLK_621_TRUE, 0x1c4) |
| 101 | |
| 102 | REG32(PSS_RST_CTRL, 0x200) |
| 103 | FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1) |
| 104 | REG32(DDR_RST_CTRL, 0x204) |
| 105 | REG32(TOPSW_RESET_CTRL, 0x208) |
| 106 | REG32(DMAC_RST_CTRL, 0x20c) |
| 107 | REG32(USB_RST_CTRL, 0x210) |
| 108 | REG32(GEM_RST_CTRL, 0x214) |
| 109 | REG32(SDIO_RST_CTRL, 0x218) |
| 110 | REG32(SPI_RST_CTRL, 0x21c) |
| 111 | REG32(CAN_RST_CTRL, 0x220) |
| 112 | REG32(I2C_RST_CTRL, 0x224) |
| 113 | REG32(UART_RST_CTRL, 0x228) |
| 114 | REG32(GPIO_RST_CTRL, 0x22c) |
| 115 | REG32(LQSPI_RST_CTRL, 0x230) |
| 116 | REG32(SMC_RST_CTRL, 0x234) |
| 117 | REG32(OCM_RST_CTRL, 0x238) |
| 118 | REG32(FPGA_RST_CTRL, 0x240) |
| 119 | REG32(A9_CPU_RST_CTRL, 0x244) |
| 120 | |
| 121 | REG32(RS_AWDT_CTRL, 0x24c) |
| 122 | REG32(RST_REASON, 0x250) |
| 123 | |
| 124 | REG32(REBOOT_STATUS, 0x258) |
| 125 | REG32(BOOT_MODE, 0x25c) |
| 126 | FIELD(BOOT_MODE, BOOT_MODE, 0, 4) |
| 127 | |
| 128 | REG32(APU_CTRL, 0x300) |
| 129 | REG32(WDT_CLK_SEL, 0x304) |
| 130 | |
| 131 | REG32(TZ_DMA_NS, 0x440) |
| 132 | REG32(TZ_DMA_IRQ_NS, 0x444) |
| 133 | REG32(TZ_DMA_PERIPH_NS, 0x448) |
| 134 | |
| 135 | REG32(PSS_IDCODE, 0x530) |
| 136 | |
| 137 | REG32(DDR_URGENT, 0x600) |
| 138 | REG32(DDR_CAL_START, 0x60c) |
| 139 | REG32(DDR_REF_START, 0x614) |
| 140 | REG32(DDR_CMD_STA, 0x618) |
| 141 | REG32(DDR_URGENT_SEL, 0x61c) |
| 142 | REG32(DDR_DFI_STATUS, 0x620) |
| 143 | |
| 144 | REG32(MIO, 0x700) |
| 145 | #define MIO_LENGTH 54 |
| 146 | |
| 147 | REG32(MIO_LOOPBACK, 0x804) |
| 148 | REG32(MIO_MST_TRI0, 0x808) |
| 149 | REG32(MIO_MST_TRI1, 0x80c) |
| 150 | |
| 151 | REG32(SD0_WP_CD_SEL, 0x830) |
| 152 | REG32(SD1_WP_CD_SEL, 0x834) |
| 153 | |
| 154 | REG32(LVL_SHFTR_EN, 0x900) |
| 155 | REG32(OCM_CFG, 0x910) |
| 156 | |
| 157 | REG32(CPU_RAM, 0xa00) |
| 158 | |
| 159 | REG32(IOU, 0xa30) |
| 160 | |
| 161 | REG32(DMAC_RAM, 0xa50) |
| 162 | |
| 163 | REG32(AFI0, 0xa60) |
| 164 | REG32(AFI1, 0xa6c) |
| 165 | REG32(AFI2, 0xa78) |
| 166 | REG32(AFI3, 0xa84) |
| 167 | #define AFI_LENGTH 3 |
| 168 | |
| 169 | REG32(OCM, 0xa90) |
| 170 | |
| 171 | REG32(DEVCI_RAM, 0xaa0) |
| 172 | |
| 173 | REG32(CSG_RAM, 0xab0) |
| 174 | |
| 175 | REG32(GPIOB_CTRL, 0xb00) |
| 176 | REG32(GPIOB_CFG_CMOS18, 0xb04) |
| 177 | REG32(GPIOB_CFG_CMOS25, 0xb08) |
| 178 | REG32(GPIOB_CFG_CMOS33, 0xb0c) |
| 179 | REG32(GPIOB_CFG_HSTL, 0xb14) |
| 180 | REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) |
| 181 | |
| 182 | REG32(DDRIOB, 0xb40) |
| 183 | REG32(DDRIOB_DCI_CTRL, 0xb70) |
| 184 | FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) |
| 185 | FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) |
| 186 | FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) |
| 187 | REG32(DDRIOB_DCI_STATUS, 0xb74) |
| 188 | FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) |
| 189 | #define DDRIOB_LENGTH 14 |
| 190 | |
| 191 | #define ZYNQ_SLCR_MMIO_SIZE 0x1000 |
| 192 | #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) |
| 193 | |
| 194 | #define TYPE_ZYNQ_SLCR "xilinx-zynq_slcr" |
| 195 | OBJECT_DECLARE_SIMPLE_TYPE(ZynqSLCRState, ZYNQ_SLCR) |
| 196 | |
| 197 | struct ZynqSLCRState { |
| 198 | SysBusDevice parent_obj; |
| 199 | |
| 200 | MemoryRegion iomem; |
| 201 | |
| 202 | bool ddriob_dci_ctrl_reset_toggled; |
| 203 | |
| 204 | uint32_t regs[ZYNQ_SLCR_NUM_REGS]; |
| 205 | |
| 206 | Clock *ps_clk; |
| 207 | Clock *uart0_ref_clk; |
| 208 | Clock *uart1_ref_clk; |
| 209 | uint8_t boot_mode; |
| 210 | }; |
| 211 | |
| 212 | /* |
| 213 | * return the output frequency of ARM/DDR/IO pll |
| 214 | * using input frequency and PLL_CTRL register |
| 215 | */ |
| 216 | static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg) |
| 217 | { |
| 218 | uint32_t mult = ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >> |
| 219 | R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT); |
| 220 | |
| 221 | /* first, check if pll is bypassed */ |
| 222 | if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) { |
| 223 | return input; |
| 224 | } |
| 225 | |
| 226 | /* is pll disabled ? */ |
| 227 | if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK | |
| 228 | R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) { |
| 229 | return 0; |
| 230 | } |
| 231 | |
| 232 | /* Consider zero feedback as maximum divide ratio possible */ |
| 233 | if (!mult) { |
| 234 | mult = 1 << R_xxx_PLL_CTRL_PLL_FPDIV_LENGTH; |
| 235 | } |
| 236 | |
| 237 | /* frequency multiplier -> period division */ |
| 238 | return input / mult; |
| 239 | } |
| 240 | |
| 241 | /* |
| 242 | * return the output period of a clock given: |
| 243 | * + the periods in an array corresponding to input mux selector |
| 244 | * + the register xxx_CLK_CTRL value |
| 245 | * + enable bit index in ctrl register |
| 246 | * |
| 247 | * This function makes the assumption that the ctrl_reg value is organized as |
| 248 | * follows: |
| 249 | * + bits[13:8] clock frequency divisor |
| 250 | * + bits[5:4] clock mux selector (index in array) |
| 251 | * + bits[index] clock enable |
| 252 | */ |
| 253 | static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], |
| 254 | uint32_t ctrl_reg, |
| 255 | unsigned index) |
| 256 | { |
| 257 | uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */ |
| 258 | uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */ |
| 259 | |
| 260 | /* first, check if clock is disabled */ |
| 261 | if (((ctrl_reg >> index) & 1u) == 0) { |
| 262 | return 0; |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * according to the Zynq technical ref. manual UG585 v1.12.2 in |
| 267 | * Clocks chapter, section 25.10.1 page 705: |
| 268 | * "The 6-bit divider provides a divide range of 1 to 63" |
| 269 | * We follow here what is implemented in linux kernel and consider |
| 270 | * the 0 value as a bypass (no division). |
| 271 | */ |
| 272 | /* frequency divisor -> period multiplication */ |
| 273 | return periods[srcsel] * (divisor ? divisor : 1u); |
| 274 | } |
| 275 | |
| 276 | /* |
| 277 | * macro helper around zynq_slcr_compute_clock to avoid repeating |
| 278 | * the register name. |
| 279 | */ |
| 280 | #define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ |
| 281 | zynq_slcr_compute_clock((plls), (state)->regs[reg], \ |
| 282 | reg ## _ ## enable_field ## _SHIFT) |
| 283 | |
| 284 | static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk) |
| 285 | { |
| 286 | uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]); |
| 287 | uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]); |
| 288 | uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]); |
| 289 | |
| 290 | uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll}; |
| 291 | |
| 292 | /* compute uartX reference clocks */ |
| 293 | clock_set(s->uart0_ref_clk, |
| 294 | ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); |
| 295 | clock_set(s->uart1_ref_clk, |
| 296 | ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); |
| 297 | } |
| 298 | |
| 299 | /** |
| 300 | * Compute and set the outputs clocks periods. |
| 301 | * But do not propagate them further. Connected clocks |
| 302 | * will not receive any updates (See zynq_slcr_compute_clocks()) |
| 303 | */ |
| 304 | static void zynq_slcr_compute_clocks(ZynqSLCRState *s) |
| 305 | { |
| 306 | uint64_t ps_clk = clock_get(s->ps_clk); |
| 307 | |
| 308 | /* consider outputs clocks are disabled while in reset */ |
| 309 | if (device_is_in_reset(DEVICE(s))) { |
| 310 | ps_clk = 0; |
| 311 | } |
| 312 | |
| 313 | zynq_slcr_compute_clocks_internal(s, ps_clk); |
| 314 | } |
| 315 | |
| 316 | /** |
| 317 | * Propagate the outputs clocks. |
| 318 | * zynq_slcr_compute_clocks() should have been called before |
| 319 | * to configure them. |
| 320 | */ |
| 321 | static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) |
| 322 | { |
| 323 | clock_propagate(s->uart0_ref_clk); |
| 324 | clock_propagate(s->uart1_ref_clk); |
| 325 | } |
| 326 | |
| 327 | static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) |
| 328 | { |
| 329 | ZynqSLCRState *s = (ZynqSLCRState *) opaque; |
| 330 | |
| 331 | zynq_slcr_compute_clocks(s); |
| 332 | zynq_slcr_propagate_clocks(s); |
| 333 | } |
| 334 | |
| 335 | static void zynq_slcr_reset_init(Object *obj, ResetType type) |
| 336 | { |
| 337 | ZynqSLCRState *s = ZYNQ_SLCR(obj); |
| 338 | int i; |
| 339 | |
| 340 | DB_PRINT("RESET\n"); |
| 341 | |
| 342 | s->ddriob_dci_ctrl_reset_toggled = false; |
| 343 | |
| 344 | s->regs[R_LOCKSTA] = 1; |
| 345 | /* 0x100 - 0x11C */ |
| 346 | s->regs[R_ARM_PLL_CTRL] = 0x0001A008; |
| 347 | s->regs[R_DDR_PLL_CTRL] = 0x0001A008; |
| 348 | s->regs[R_IO_PLL_CTRL] = 0x0001A008; |
| 349 | s->regs[R_PLL_STATUS] = 0x0000003F; |
| 350 | s->regs[R_ARM_PLL_CFG] = 0x00014000; |
| 351 | s->regs[R_DDR_PLL_CFG] = 0x00014000; |
| 352 | s->regs[R_IO_PLL_CFG] = 0x00014000; |
| 353 | |
| 354 | /* 0x120 - 0x16C */ |
| 355 | s->regs[R_ARM_CLK_CTRL] = 0x1F000400; |
| 356 | s->regs[R_DDR_CLK_CTRL] = 0x18400003; |
| 357 | s->regs[R_DCI_CLK_CTRL] = 0x01E03201; |
| 358 | s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD; |
| 359 | s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941; |
| 360 | s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001; |
| 361 | s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01; |
| 362 | s->regs[R_SMC_CLK_CTRL] = 0x00003C01; |
| 363 | s->regs[R_LQSPI_CLK_CTRL] = 0x00002821; |
| 364 | s->regs[R_SDIO_CLK_CTRL] = 0x00001E03; |
| 365 | s->regs[R_UART_CLK_CTRL] = 0x00003F03; |
| 366 | s->regs[R_SPI_CLK_CTRL] = 0x00003F03; |
| 367 | s->regs[R_CAN_CLK_CTRL] = 0x00501903; |
| 368 | s->regs[R_DBG_CLK_CTRL] = 0x00000F03; |
| 369 | s->regs[R_PCAP_CLK_CTRL] = 0x00000F01; |
| 370 | |
| 371 | /* 0x170 - 0x1AC */ |
| 372 | s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL] |
| 373 | = s->regs[R_FPGA2_CLK_CTRL] |
| 374 | = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800; |
| 375 | s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA] |
| 376 | = s->regs[R_FPGA2_THR_STA] |
| 377 | = s->regs[R_FPGA3_THR_STA] = 0x00010000; |
| 378 | |
| 379 | /* 0x1B0 - 0x1D8 */ |
| 380 | s->regs[R_BANDGAP_TRIP] = 0x0000001F; |
| 381 | s->regs[R_PLL_PREDIVISOR] = 0x00000001; |
| 382 | s->regs[R_CLK_621_TRUE] = 0x00000001; |
| 383 | |
| 384 | /* 0x200 - 0x25C */ |
| 385 | s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; |
| 386 | s->regs[R_RST_REASON] = 0x00000040; |
| 387 | |
| 388 | s->regs[R_BOOT_MODE] = s->boot_mode & R_BOOT_MODE_BOOT_MODE_MASK; |
| 389 | |
| 390 | /* 0x700 - 0x7D4 */ |
| 391 | for (i = 0; i < 54; i++) { |
| 392 | s->regs[R_MIO + i] = 0x00001601; |
| 393 | } |
| 394 | for (i = 2; i <= 8; i++) { |
| 395 | s->regs[R_MIO + i] = 0x00000601; |
| 396 | } |
| 397 | |
| 398 | s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF; |
| 399 | |
| 400 | s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3] |
| 401 | = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7] |
| 402 | = 0x00010101; |
| 403 | s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101; |
| 404 | s->regs[R_CPU_RAM + 6] = 0x00000001; |
| 405 | |
| 406 | s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2] |
| 407 | = s->regs[R_IOU + 3] = 0x09090909; |
| 408 | s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909; |
| 409 | s->regs[R_IOU + 6] = 0x00000909; |
| 410 | |
| 411 | s->regs[R_DMAC_RAM] = 0x00000009; |
| 412 | |
| 413 | s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909; |
| 414 | s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909; |
| 415 | s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909; |
| 416 | s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909; |
| 417 | s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2] |
| 418 | = s->regs[R_AFI3 + 2] = 0x00000909; |
| 419 | |
| 420 | s->regs[R_OCM + 0] = 0x01010101; |
| 421 | s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909; |
| 422 | |
| 423 | s->regs[R_DEVCI_RAM] = 0x00000909; |
| 424 | s->regs[R_CSG_RAM] = 0x00000001; |
| 425 | |
| 426 | s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2] |
| 427 | = s->regs[R_DDRIOB + 3] = 0x00000e00; |
| 428 | s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] |
| 429 | = 0x00000e00; |
| 430 | |
| 431 | s->regs[R_DDRIOB_DCI_CTRL] = 0x00000020; |
| 432 | } |
| 433 | |
| 434 | static void zynq_slcr_reset_hold(Object *obj, ResetType type) |
| 435 | { |
| 436 | ZynqSLCRState *s = ZYNQ_SLCR(obj); |
| 437 | |
| 438 | /* will disable all output clocks */ |
| 439 | zynq_slcr_compute_clocks_internal(s, 0); |
| 440 | zynq_slcr_propagate_clocks(s); |
| 441 | } |
| 442 | |
| 443 | static void zynq_slcr_reset_exit(Object *obj, ResetType type) |
| 444 | { |
| 445 | ZynqSLCRState *s = ZYNQ_SLCR(obj); |
| 446 | |
| 447 | /* will compute output clocks according to ps_clk and registers */ |
| 448 | zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk)); |
| 449 | zynq_slcr_propagate_clocks(s); |
| 450 | } |
| 451 | |
| 452 | static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) |
| 453 | { |
| 454 | switch (offset) { |
| 455 | case R_LOCK: |
| 456 | case R_UNLOCK: |
| 457 | case R_DDR_CAL_START: |
| 458 | case R_DDR_REF_START: |
| 459 | return !rnw; /* Write only */ |
| 460 | case R_LOCKSTA: |
| 461 | case R_FPGA0_THR_STA: |
| 462 | case R_FPGA1_THR_STA: |
| 463 | case R_FPGA2_THR_STA: |
| 464 | case R_FPGA3_THR_STA: |
| 465 | case R_BOOT_MODE: |
| 466 | case R_PSS_IDCODE: |
| 467 | case R_DDR_CMD_STA: |
| 468 | case R_DDR_DFI_STATUS: |
| 469 | case R_PLL_STATUS: |
| 470 | return rnw;/* read only */ |
| 471 | case R_SCL: |
| 472 | case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL: |
| 473 | case R_ARM_PLL_CFG ... R_IO_PLL_CFG: |
| 474 | case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL: |
| 475 | case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT: |
| 476 | case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT: |
| 477 | case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT: |
| 478 | case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT: |
| 479 | case R_BANDGAP_TRIP: |
| 480 | case R_PLL_PREDIVISOR: |
| 481 | case R_CLK_621_TRUE: |
| 482 | case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL: |
| 483 | case R_RS_AWDT_CTRL: |
| 484 | case R_RST_REASON: |
| 485 | case R_REBOOT_STATUS: |
| 486 | case R_APU_CTRL: |
| 487 | case R_WDT_CLK_SEL: |
| 488 | case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS: |
| 489 | case R_DDR_URGENT: |
| 490 | case R_DDR_URGENT_SEL: |
| 491 | case R_MIO ... R_MIO + MIO_LENGTH - 1: |
| 492 | case R_MIO_LOOPBACK ... R_MIO_MST_TRI1: |
| 493 | case R_SD0_WP_CD_SEL: |
| 494 | case R_SD1_WP_CD_SEL: |
| 495 | case R_LVL_SHFTR_EN: |
| 496 | case R_OCM_CFG: |
| 497 | case R_CPU_RAM: |
| 498 | case R_IOU: |
| 499 | case R_DMAC_RAM: |
| 500 | case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1: |
| 501 | case R_OCM: |
| 502 | case R_DEVCI_RAM: |
| 503 | case R_CSG_RAM: |
| 504 | case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33: |
| 505 | case R_GPIOB_CFG_HSTL: |
| 506 | case R_GPIOB_DRVR_BIAS_CTRL: |
| 507 | case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1: |
| 508 | return true; |
| 509 | default: |
| 510 | return false; |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | static uint64_t zynq_slcr_read(void *opaque, hwaddr offset, |
| 515 | unsigned size) |
| 516 | { |
| 517 | ZynqSLCRState *s = opaque; |
| 518 | offset /= 4; |
| 519 | uint32_t ret = s->regs[offset]; |
| 520 | |
| 521 | if (!zynq_slcr_check_offset(offset, true)) { |
| 522 | qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " |
| 523 | " addr %" HWADDR_PRIx "\n", offset * 4); |
| 524 | } |
| 525 | |
| 526 | DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret); |
| 527 | return ret; |
| 528 | } |
| 529 | |
| 530 | static void zynq_slcr_write(void *opaque, hwaddr offset, |
| 531 | uint64_t val, unsigned size) |
| 532 | { |
| 533 | ZynqSLCRState *s = (ZynqSLCRState *)opaque; |
| 534 | offset /= 4; |
| 535 | |
| 536 | DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); |
| 537 | |
| 538 | if (!zynq_slcr_check_offset(offset, false)) { |
| 539 | qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to " |
| 540 | "addr %" HWADDR_PRIx "\n", offset * 4); |
| 541 | return; |
| 542 | } |
| 543 | |
| 544 | switch (offset) { |
| 545 | case R_SCL: |
| 546 | s->regs[R_SCL] = val & 0x1; |
| 547 | return; |
| 548 | case R_LOCK: |
| 549 | if ((val & 0xFFFF) == XILINX_LOCK_KEY) { |
| 550 | DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, |
| 551 | (unsigned)val & 0xFFFF); |
| 552 | s->regs[R_LOCKSTA] = 1; |
| 553 | } else { |
| 554 | DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", |
| 555 | (int)offset, (unsigned)val & 0xFFFF); |
| 556 | } |
| 557 | return; |
| 558 | case R_UNLOCK: |
| 559 | if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) { |
| 560 | DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, |
| 561 | (unsigned)val & 0xFFFF); |
| 562 | s->regs[R_LOCKSTA] = 0; |
| 563 | } else { |
| 564 | DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", |
| 565 | (int)offset, (unsigned)val & 0xFFFF); |
| 566 | } |
| 567 | return; |
| 568 | |
| 569 | case R_DDRIOB_DCI_CTRL: |
| 570 | if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && |
| 571 | FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)) { |
| 572 | |
| 573 | s->ddriob_dci_ctrl_reset_toggled = true; |
| 574 | DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); |
| 575 | } |
| 576 | |
| 577 | if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && |
| 578 | FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && |
| 579 | !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && |
| 580 | s->ddriob_dci_ctrl_reset_toggled) { |
| 581 | |
| 582 | s->regs[R_DDRIOB_DCI_STATUS] |= R_DDRIOB_DCI_STATUS_DONE_MASK; |
| 583 | } else { |
| 584 | s->regs[R_DDRIOB_DCI_STATUS] &= ~R_DDRIOB_DCI_STATUS_DONE_MASK; |
| 585 | } |
| 586 | break; |
| 587 | } |
| 588 | |
| 589 | if (s->regs[R_LOCKSTA]) { |
| 590 | qemu_log_mask(LOG_GUEST_ERROR, |
| 591 | "SCLR registers are locked. Unlock them first\n"); |
| 592 | return; |
| 593 | } |
| 594 | s->regs[offset] = val; |
| 595 | |
| 596 | switch (offset) { |
| 597 | case R_PSS_RST_CTRL: |
| 598 | if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) { |
| 599 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 600 | } |
| 601 | break; |
| 602 | case R_IO_PLL_CTRL: |
| 603 | case R_ARM_PLL_CTRL: |
| 604 | case R_DDR_PLL_CTRL: |
| 605 | case R_UART_CLK_CTRL: |
| 606 | zynq_slcr_compute_clocks(s); |
| 607 | zynq_slcr_propagate_clocks(s); |
| 608 | break; |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | static const MemoryRegionOps slcr_ops = { |
| 613 | .read = zynq_slcr_read, |
| 614 | .write = zynq_slcr_write, |
| 615 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 616 | }; |
| 617 | |
| 618 | static const ClockPortInitArray zynq_slcr_clocks = { |
| 619 | QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, ClockUpdate), |
| 620 | QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), |
| 621 | QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), |
| 622 | QDEV_CLOCK_END |
| 623 | }; |
| 624 | |
| 625 | static void zynq_slcr_realize(DeviceState *dev, Error **errp) |
| 626 | { |
| 627 | ZynqSLCRState *s = ZYNQ_SLCR(dev); |
| 628 | |
| 629 | if (s->boot_mode > 0xF) { |
| 630 | error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | static void zynq_slcr_init(Object *obj) |
| 635 | { |
| 636 | ZynqSLCRState *s = ZYNQ_SLCR(obj); |
| 637 | |
| 638 | memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", |
| 639 | ZYNQ_SLCR_MMIO_SIZE); |
| 640 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); |
| 641 | |
| 642 | qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); |
| 643 | } |
| 644 | |
| 645 | static const VMStateDescription vmstate_zynq_slcr = { |
| 646 | .name = "zynq_slcr", |
| 647 | .version_id = 3, |
| 648 | .minimum_version_id = 2, |
| 649 | .fields = (const VMStateField[]) { |
| 650 | VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS), |
| 651 | VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3), |
| 652 | VMSTATE_END_OF_LIST() |
| 653 | } |
| 654 | }; |
| 655 | |
| 656 | static const Property zynq_slcr_props[] = { |
| 657 | DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), |
| 658 | }; |
| 659 | |
| 660 | static void zynq_slcr_class_init(ObjectClass *klass, const void *data) |
| 661 | { |
| 662 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 663 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 664 | |
| 665 | dc->vmsd = &vmstate_zynq_slcr; |
| 666 | dc->realize = zynq_slcr_realize; |
| 667 | rc->phases.enter = zynq_slcr_reset_init; |
| 668 | rc->phases.hold = zynq_slcr_reset_hold; |
| 669 | rc->phases.exit = zynq_slcr_reset_exit; |
| 670 | device_class_set_props(dc, zynq_slcr_props); |
| 671 | } |
| 672 | |
| 673 | static const TypeInfo zynq_slcr_info = { |
| 674 | .class_init = zynq_slcr_class_init, |
| 675 | .name = TYPE_ZYNQ_SLCR, |
| 676 | .parent = TYPE_SYS_BUS_DEVICE, |
| 677 | .instance_size = sizeof(ZynqSLCRState), |
| 678 | .instance_init = zynq_slcr_init, |
| 679 | }; |
| 680 | |
| 681 | static void zynq_slcr_register_types(void) |
| 682 | { |
| 683 | type_register_static(&zynq_slcr_info); |
| 684 | } |
| 685 | |
| 686 | type_init(zynq_slcr_register_types) |