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1 /*
2 * PCM-3680i PCI CAN device (SJA1000 based) emulation
3 *
4 * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com)
5 *
6 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by
7 * Jin Yang and Pavel Pisa
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "qemu/module.h"
30 #include "qapi/error.h"
31 #include "hw/core/irq.h"
32 #include "hw/pci/pci_device.h"
33 #include "hw/core/qdev-properties.h"
34 #include "migration/vmstate.h"
35 #include "net/can_emu.h"
36
37 #include "can_sja1000.h"
38 #include "qom/object.h"
39
40 #define TYPE_CAN_PCI_DEV "pcm3680_pci"
41
42 typedef struct Pcm3680iPCIState Pcm3680iPCIState;
43 DECLARE_INSTANCE_CHECKER(Pcm3680iPCIState, PCM3680i_PCI_DEV,
44 TYPE_CAN_PCI_DEV)
45
46 /* the PCI device and vendor IDs */
47 #ifndef PCM3680i_PCI_VENDOR_ID1
48 #define PCM3680i_PCI_VENDOR_ID1 0x13fe
49 #endif
50
51 #ifndef PCM3680i_PCI_DEVICE_ID1
52 #define PCM3680i_PCI_DEVICE_ID1 0xc002
53 #endif
54
55 #define PCM3680i_PCI_SJA_COUNT 2
56 #define PCM3680i_PCI_SJA_RANGE 0x100
57
58 #define PCM3680i_PCI_BYTES_PER_SJA 0x20
59
60 struct Pcm3680iPCIState {
61 /*< private >*/
62 PCIDevice dev;
63 /*< public >*/
64 MemoryRegion sja_io[PCM3680i_PCI_SJA_COUNT];
65
66 CanSJA1000State sja_state[PCM3680i_PCI_SJA_COUNT];
67 qemu_irq irq;
68
69 char *model; /* The model that support, only SJA1000 now. */
70 CanBusState *canbus[PCM3680i_PCI_SJA_COUNT];
71 };
72
73 static void pcm3680i_pci_reset(DeviceState *dev)
74 {
75 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(dev);
76 int i;
77
78 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) {
79 can_sja_hardware_reset(&d->sja_state[i]);
80 }
81 }
82
83 static uint64_t pcm3680i_pci_sja1_io_read(void *opaque, hwaddr addr,
84 unsigned size)
85 {
86 Pcm3680iPCIState *d = opaque;
87 CanSJA1000State *s = &d->sja_state[0];
88
89 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) {
90 return 0;
91 }
92
93 return can_sja_mem_read(s, addr, size);
94 }
95
96 static void pcm3680i_pci_sja1_io_write(void *opaque, hwaddr addr,
97 uint64_t data, unsigned size)
98 {
99 Pcm3680iPCIState *d = opaque;
100 CanSJA1000State *s = &d->sja_state[0];
101
102 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) {
103 return;
104 }
105
106 can_sja_mem_write(s, addr, data, size);
107 }
108
109 static uint64_t pcm3680i_pci_sja2_io_read(void *opaque, hwaddr addr,
110 unsigned size)
111 {
112 Pcm3680iPCIState *d = opaque;
113 CanSJA1000State *s = &d->sja_state[1];
114
115 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) {
116 return 0;
117 }
118
119 return can_sja_mem_read(s, addr, size);
120 }
121
122 static void pcm3680i_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data,
123 unsigned size)
124 {
125 Pcm3680iPCIState *d = opaque;
126 CanSJA1000State *s = &d->sja_state[1];
127
128 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) {
129 return;
130 }
131
132 can_sja_mem_write(s, addr, data, size);
133 }
134
135 static const MemoryRegionOps pcm3680i_pci_sja1_io_ops = {
136 .read = pcm3680i_pci_sja1_io_read,
137 .write = pcm3680i_pci_sja1_io_write,
138 .endianness = DEVICE_LITTLE_ENDIAN,
139 .impl = {
140 .max_access_size = 1,
141 },
142 };
143
144 static const MemoryRegionOps pcm3680i_pci_sja2_io_ops = {
145 .read = pcm3680i_pci_sja2_io_read,
146 .write = pcm3680i_pci_sja2_io_write,
147 .endianness = DEVICE_LITTLE_ENDIAN,
148 .impl = {
149 .max_access_size = 1,
150 },
151 };
152
153 static void pcm3680i_pci_realize(PCIDevice *pci_dev, Error **errp)
154 {
155 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(pci_dev);
156 uint8_t *pci_conf;
157 int i;
158
159 pci_conf = pci_dev->config;
160 pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
161
162 d->irq = pci_allocate_irq(&d->dev);
163
164 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) {
165 can_sja_init(&d->sja_state[i], d->irq);
166 }
167
168 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) {
169 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) {
170 error_setg(errp, "can_sja_connect_to_bus failed");
171 return;
172 }
173 }
174
175 memory_region_init_io(&d->sja_io[0], OBJECT(d), &pcm3680i_pci_sja1_io_ops,
176 d, "pcm3680i_pci-sja1", PCM3680i_PCI_SJA_RANGE);
177
178 memory_region_init_io(&d->sja_io[1], OBJECT(d), &pcm3680i_pci_sja2_io_ops,
179 d, "pcm3680i_pci-sja2", PCM3680i_PCI_SJA_RANGE);
180
181 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) {
182 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO,
183 &d->sja_io[i]);
184 }
185 }
186
187 static void pcm3680i_pci_exit(PCIDevice *pci_dev)
188 {
189 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(pci_dev);
190 int i;
191
192 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) {
193 can_sja_disconnect(&d->sja_state[i]);
194 }
195
196 qemu_free_irq(d->irq);
197 }
198
199 static const VMStateDescription vmstate_pcm3680i_pci = {
200 .name = "pcm3680i_pci",
201 .version_id = 1,
202 .minimum_version_id = 1,
203 .fields = (const VMStateField[]) {
204 VMSTATE_PCI_DEVICE(dev, Pcm3680iPCIState),
205 VMSTATE_STRUCT(sja_state[0], Pcm3680iPCIState, 0,
206 vmstate_can_sja, CanSJA1000State),
207 VMSTATE_STRUCT(sja_state[1], Pcm3680iPCIState, 0,
208 vmstate_can_sja, CanSJA1000State),
209 VMSTATE_END_OF_LIST()
210 }
211 };
212
213 static void pcm3680i_pci_instance_init(Object *obj)
214 {
215 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(obj);
216
217 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
218 (Object **)&d->canbus[0],
219 qdev_prop_allow_set_link_before_realize,
220 0);
221 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
222 (Object **)&d->canbus[1],
223 qdev_prop_allow_set_link_before_realize,
224 0);
225 }
226
227 static void pcm3680i_pci_class_init(ObjectClass *klass, const void *data)
228 {
229 DeviceClass *dc = DEVICE_CLASS(klass);
230 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
231
232 k->realize = pcm3680i_pci_realize;
233 k->exit = pcm3680i_pci_exit;
234 k->vendor_id = PCM3680i_PCI_VENDOR_ID1;
235 k->device_id = PCM3680i_PCI_DEVICE_ID1;
236 k->revision = 0x00;
237 k->class_id = 0x000c09;
238 k->subsystem_vendor_id = PCM3680i_PCI_VENDOR_ID1;
239 k->subsystem_id = PCM3680i_PCI_DEVICE_ID1;
240 dc->desc = "Pcm3680i PCICANx";
241 dc->vmsd = &vmstate_pcm3680i_pci;
242 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
243 device_class_set_legacy_reset(dc, pcm3680i_pci_reset);
244 }
245
246 static const TypeInfo pcm3680i_pci_info = {
247 .name = TYPE_CAN_PCI_DEV,
248 .parent = TYPE_PCI_DEVICE,
249 .instance_size = sizeof(Pcm3680iPCIState),
250 .class_init = pcm3680i_pci_class_init,
251 .instance_init = pcm3680i_pci_instance_init,
252 .interfaces = (const InterfaceInfo[]) {
253 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
254 { },
255 },
256 };
257
258 static void pcm3680i_pci_register_types(void)
259 {
260 type_register_static(&pcm3680i_pci_info);
261 }
262
263 type_init(pcm3680i_pci_register_types)