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1 /*
2 * CAN device - SJA1000 chip emulation for QEMU
3 *
4 * Copyright (c) 2013-2014 Jin Yang
5 * Copyright (c) 2014-2018 Pavel Pisa
6 *
7 * Initial development supported by Google GSoC 2013 from RTEMS project slot
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "qemu/log.h"
30 #include "qemu/bitops.h"
31 #include "hw/core/irq.h"
32 #include "migration/vmstate.h"
33 #include "net/can_emu.h"
34
35 #include "can_sja1000.h"
36
37 #ifndef DEBUG_FILTER
38 #define DEBUG_FILTER 0
39 #endif /*DEBUG_FILTER*/
40
41 #ifndef DEBUG_CAN
42 #define DEBUG_CAN 0
43 #endif /*DEBUG_CAN*/
44
45 #define DPRINTF(fmt, ...) \
46 do { \
47 if (DEBUG_CAN) { \
48 qemu_log("[cansja]: " fmt , ## __VA_ARGS__); \
49 } \
50 } while (0)
51
52 static void can_sja_software_reset(CanSJA1000State *s)
53 {
54 s->mode &= ~0x31;
55 s->mode |= 0x01;
56 s->status_pel &= ~0x37;
57 s->status_pel |= 0x34;
58
59 s->rxbuf_start = 0x00;
60 s->rxmsg_cnt = 0x00;
61 s->rx_cnt = 0x00;
62 }
63
64 void can_sja_hardware_reset(CanSJA1000State *s)
65 {
66 /* Reset by hardware, p10 */
67 s->mode = 0x01;
68 s->status_pel = 0x3c;
69 s->interrupt_pel = 0x00;
70 s->clock = 0x00;
71 s->rxbuf_start = 0x00;
72 s->rxmsg_cnt = 0x00;
73 s->rx_cnt = 0x00;
74
75 s->control = 0x01;
76 s->status_bas = 0x0c;
77 s->interrupt_bas = 0x00;
78
79 qemu_irq_lower(s->irq);
80 }
81
82 static
83 void can_sja_single_filter(struct qemu_can_filter *filter,
84 const uint8_t *acr, const uint8_t *amr, int extended)
85 {
86 if (extended) {
87 filter->can_id = (uint32_t)acr[0] << 21;
88 filter->can_id |= (uint32_t)acr[1] << 13;
89 filter->can_id |= (uint32_t)acr[2] << 5;
90 filter->can_id |= (uint32_t)acr[3] >> 3;
91 if (acr[3] & 4) {
92 filter->can_id |= QEMU_CAN_RTR_FLAG;
93 }
94
95 filter->can_mask = (uint32_t)amr[0] << 21;
96 filter->can_mask |= (uint32_t)amr[1] << 13;
97 filter->can_mask |= (uint32_t)amr[2] << 5;
98 filter->can_mask |= (uint32_t)amr[3] >> 3;
99 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK;
100 if (!(amr[3] & 4)) {
101 filter->can_mask |= QEMU_CAN_RTR_FLAG;
102 }
103 } else {
104 filter->can_id = (uint32_t)acr[0] << 3;
105 filter->can_id |= (uint32_t)acr[1] >> 5;
106 if (acr[1] & 0x10) {
107 filter->can_id |= QEMU_CAN_RTR_FLAG;
108 }
109
110 filter->can_mask = (uint32_t)amr[0] << 3;
111 filter->can_mask |= (uint32_t)amr[1] >> 5;
112 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK;
113 if (!(amr[1] & 0x10)) {
114 filter->can_mask |= QEMU_CAN_RTR_FLAG;
115 }
116 }
117 }
118
119 static
120 void can_sja_dual_filter(struct qemu_can_filter *filter,
121 const uint8_t *acr, const uint8_t *amr, int extended)
122 {
123 if (extended) {
124 filter->can_id = (uint32_t)acr[0] << 21;
125 filter->can_id |= (uint32_t)acr[1] << 13;
126
127 filter->can_mask = (uint32_t)amr[0] << 21;
128 filter->can_mask |= (uint32_t)amr[1] << 13;
129 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK & ~0x1fff;
130 } else {
131 filter->can_id = (uint32_t)acr[0] << 3;
132 filter->can_id |= (uint32_t)acr[1] >> 5;
133 if (acr[1] & 0x10) {
134 filter->can_id |= QEMU_CAN_RTR_FLAG;
135 }
136
137 filter->can_mask = (uint32_t)amr[0] << 3;
138 filter->can_mask |= (uint32_t)amr[1] >> 5;
139 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK;
140 if (!(amr[1] & 0x10)) {
141 filter->can_mask |= QEMU_CAN_RTR_FLAG;
142 }
143 }
144 }
145
146 /* Details in DS-p22, what we need to do here is to test the data. */
147 static
148 int can_sja_accept_filter(CanSJA1000State *s,
149 const qemu_can_frame *frame)
150 {
151
152 struct qemu_can_filter filter;
153
154 if (s->clock & 0x80) { /* PeliCAN Mode */
155 if (s->mode & (1 << 3)) { /* Single mode. */
156 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */
157 can_sja_single_filter(&filter,
158 s->code_mask + 0, s->code_mask + 4, 1);
159
160 if (!can_bus_filter_match(&filter, frame->can_id)) {
161 return 0;
162 }
163 } else { /* SFF */
164 can_sja_single_filter(&filter,
165 s->code_mask + 0, s->code_mask + 4, 0);
166
167 if (!can_bus_filter_match(&filter, frame->can_id)) {
168 return 0;
169 }
170
171 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */
172 return 1;
173 }
174
175 if (frame->can_dlc == 0) {
176 return 1;
177 }
178
179 if ((frame->data[0] & ~(s->code_mask[6])) !=
180 (s->code_mask[2] & ~(s->code_mask[6]))) {
181 return 0;
182 }
183
184 if (frame->can_dlc < 2) {
185 return 1;
186 }
187
188 if ((frame->data[1] & ~(s->code_mask[7])) ==
189 (s->code_mask[3] & ~(s->code_mask[7]))) {
190 return 1;
191 }
192
193 return 0;
194 }
195 } else { /* Dual mode */
196 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */
197 can_sja_dual_filter(&filter,
198 s->code_mask + 0, s->code_mask + 4, 1);
199
200 if (can_bus_filter_match(&filter, frame->can_id)) {
201 return 1;
202 }
203
204 can_sja_dual_filter(&filter,
205 s->code_mask + 2, s->code_mask + 6, 1);
206
207 if (can_bus_filter_match(&filter, frame->can_id)) {
208 return 1;
209 }
210
211 return 0;
212 } else {
213 can_sja_dual_filter(&filter,
214 s->code_mask + 0, s->code_mask + 4, 0);
215
216 if (can_bus_filter_match(&filter, frame->can_id)) {
217 uint8_t expect;
218 uint8_t mask;
219 expect = s->code_mask[1] << 4;
220 expect |= s->code_mask[3] & 0x0f;
221
222 mask = s->code_mask[5] << 4;
223 mask |= s->code_mask[7] & 0x0f;
224 mask = ~mask & 0xff;
225
226 if ((frame->data[0] & mask) ==
227 (expect & mask)) {
228 return 1;
229 }
230 }
231
232 can_sja_dual_filter(&filter,
233 s->code_mask + 2, s->code_mask + 6, 0);
234
235 if (can_bus_filter_match(&filter, frame->can_id)) {
236 return 1;
237 }
238
239 return 0;
240 }
241 }
242 }
243
244 return 1;
245 }
246
247 static void can_display_msg(const char *prefix, const qemu_can_frame *msg)
248 {
249 int i;
250 FILE *logfile = qemu_log_trylock();
251
252 if (logfile) {
253 fprintf(logfile, "%s%03X [%01d] %s %s",
254 prefix,
255 msg->can_id & QEMU_CAN_EFF_MASK,
256 msg->can_dlc,
257 msg->can_id & QEMU_CAN_EFF_FLAG ? "EFF" : "SFF",
258 msg->can_id & QEMU_CAN_RTR_FLAG ? "RTR" : "DAT");
259
260 for (i = 0; i < msg->can_dlc; i++) {
261 fprintf(logfile, " %02X", msg->data[i]);
262 }
263 fprintf(logfile, "\n");
264 qemu_log_unlock(logfile);
265 }
266 }
267
268 static void buff2frame_pel(const uint8_t *buff, qemu_can_frame *frame)
269 {
270 uint8_t i;
271
272 frame->flags = 0;
273 frame->can_id = 0;
274 if (buff[0] & 0x40) { /* RTR */
275 frame->can_id = QEMU_CAN_RTR_FLAG;
276 }
277 frame->can_dlc = buff[0] & 0x0f;
278
279 if (frame->can_dlc > 8) {
280 frame->can_dlc = 8;
281 }
282
283 if (buff[0] & 0x80) { /* Extended */
284 frame->can_id |= QEMU_CAN_EFF_FLAG;
285 frame->can_id |= buff[1] << 21; /* ID.28~ID.21 */
286 frame->can_id |= buff[2] << 13; /* ID.20~ID.13 */
287 frame->can_id |= buff[3] << 5;
288 frame->can_id |= buff[4] >> 3;
289 for (i = 0; i < frame->can_dlc; i++) {
290 frame->data[i] = buff[5 + i];
291 }
292 for (; i < 8; i++) {
293 frame->data[i] = 0;
294 }
295 } else {
296 frame->can_id |= buff[1] << 3;
297 frame->can_id |= buff[2] >> 5;
298 for (i = 0; i < frame->can_dlc; i++) {
299 frame->data[i] = buff[3 + i];
300 }
301 for (; i < 8; i++) {
302 frame->data[i] = 0;
303 }
304 }
305 }
306
307
308 static void buff2frame_bas(const uint8_t *buff, qemu_can_frame *frame)
309 {
310 uint8_t i;
311
312 frame->flags = 0;
313 frame->can_id = ((buff[0] << 3) & (0xff << 3)) + ((buff[1] >> 5) & 0x07);
314 if (buff[1] & 0x10) { /* RTR */
315 frame->can_id = QEMU_CAN_RTR_FLAG;
316 }
317 frame->can_dlc = buff[1] & 0x0f;
318
319 if (frame->can_dlc > 8) {
320 frame->can_dlc = 8;
321 }
322
323 for (i = 0; i < frame->can_dlc; i++) {
324 frame->data[i] = buff[2 + i];
325 }
326 for (; i < 8; i++) {
327 frame->data[i] = 0;
328 }
329 }
330
331
332 static int frame2buff_pel(const qemu_can_frame *frame, uint8_t *buff)
333 {
334 int i;
335 int dlen = frame->can_dlc;
336
337 if (frame->can_id & QEMU_CAN_ERR_FLAG) { /* error frame, NOT support now. */
338 return -1;
339 }
340
341 if (dlen > 8) {
342 return -1;
343 }
344
345 buff[0] = 0x0f & frame->can_dlc; /* DLC */
346 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */
347 buff[0] |= (1 << 6);
348 }
349 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */
350 buff[0] |= (1 << 7);
351 buff[1] = extract32(frame->can_id, 21, 8); /* ID.28~ID.21 */
352 buff[2] = extract32(frame->can_id, 13, 8); /* ID.20~ID.13 */
353 buff[3] = extract32(frame->can_id, 5, 8); /* ID.12~ID.05 */
354 buff[4] = extract32(frame->can_id, 0, 5) << 3; /* ID.04~ID.00,xxx */
355 for (i = 0; i < dlen; i++) {
356 buff[5 + i] = frame->data[i];
357 }
358 return dlen + 5;
359 } else { /* SFF */
360 buff[1] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */
361 buff[2] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */
362 for (i = 0; i < dlen; i++) {
363 buff[3 + i] = frame->data[i];
364 }
365
366 return dlen + 3;
367 }
368
369 return -1;
370 }
371
372 static int frame2buff_bas(const qemu_can_frame *frame, uint8_t *buff)
373 {
374 int i;
375 int dlen = frame->can_dlc;
376
377 /*
378 * EFF, no support for BasicMode
379 * No use for Error frames now,
380 * they could be used in future to update SJA1000 error state
381 */
382 if ((frame->can_id & QEMU_CAN_EFF_FLAG) ||
383 (frame->can_id & QEMU_CAN_ERR_FLAG)) {
384 return -1;
385 }
386
387 if (dlen > 8) {
388 return -1;
389 }
390
391 buff[0] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */
392 buff[1] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */
393 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */
394 buff[1] |= (1 << 4);
395 }
396 buff[1] |= frame->can_dlc & 0x0f;
397 for (i = 0; i < dlen; i++) {
398 buff[2 + i] = frame->data[i];
399 }
400
401 return dlen + 2;
402 }
403
404 static void can_sja_update_pel_irq(CanSJA1000State *s)
405 {
406 if (s->interrupt_en & s->interrupt_pel) {
407 qemu_irq_raise(s->irq);
408 } else {
409 qemu_irq_lower(s->irq);
410 }
411 }
412
413 static void can_sja_update_bas_irq(CanSJA1000State *s)
414 {
415 if ((s->control >> 1) & s->interrupt_bas) {
416 qemu_irq_raise(s->irq);
417 } else {
418 qemu_irq_lower(s->irq);
419 }
420 }
421
422 void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
423 unsigned size)
424 {
425 qemu_can_frame frame;
426 uint32_t tmp;
427 uint8_t tmp8, count;
428
429
430 DPRINTF("write 0x%02llx addr 0x%02x\n",
431 (unsigned long long)val, (unsigned int)addr);
432
433 if (addr > CAN_SJA_MEM_SIZE) {
434 return;
435 }
436
437 if (s->clock & 0x80) { /* PeliCAN Mode */
438 switch (addr) {
439 case SJA_MOD: /* Mode register */
440 s->mode = 0x1f & val;
441 if ((s->mode & 0x01) && ((val & 0x01) == 0)) {
442 /* Go to operation mode from reset mode. */
443 if (s->mode & (1 << 3)) { /* Single mode. */
444 /* For EFF */
445 can_sja_single_filter(&s->filter[0],
446 s->code_mask + 0, s->code_mask + 4, 1);
447
448 /* For SFF */
449 can_sja_single_filter(&s->filter[1],
450 s->code_mask + 0, s->code_mask + 4, 0);
451
452 can_bus_client_set_filters(&s->bus_client, s->filter, 2);
453 } else { /* Dual mode */
454 /* For EFF */
455 can_sja_dual_filter(&s->filter[0],
456 s->code_mask + 0, s->code_mask + 4, 1);
457
458 can_sja_dual_filter(&s->filter[1],
459 s->code_mask + 2, s->code_mask + 6, 1);
460
461 /* For SFF */
462 can_sja_dual_filter(&s->filter[2],
463 s->code_mask + 0, s->code_mask + 4, 0);
464
465 can_sja_dual_filter(&s->filter[3],
466 s->code_mask + 2, s->code_mask + 6, 0);
467
468 can_bus_client_set_filters(&s->bus_client, s->filter, 4);
469 }
470
471 s->rxmsg_cnt = 0;
472 s->rx_cnt = 0;
473 }
474 break;
475
476 case SJA_CMR: /* Command register. */
477 if (0x01 & val) { /* Send transmission request. */
478 buff2frame_pel(s->tx_buff, &frame);
479 if (DEBUG_FILTER) {
480 can_display_msg("[cansja]: Tx request " , &frame);
481 }
482
483 /*
484 * Clear transmission complete status,
485 * and Transmit Buffer Status.
486 * write to the backends.
487 */
488 s->status_pel &= ~(3 << 2);
489
490 can_bus_client_send(&s->bus_client, &frame, 1);
491
492 /*
493 * Set transmission complete status
494 * and Transmit Buffer Status.
495 */
496 s->status_pel |= (3 << 2);
497
498 /* Clear transmit status. */
499 s->status_pel &= ~(1 << 5);
500 s->interrupt_pel |= 0x02;
501 can_sja_update_pel_irq(s);
502 }
503 if (0x04 & val) { /* Release Receive Buffer */
504 if (s->rxmsg_cnt <= 0) {
505 break;
506 }
507
508 tmp8 = s->rx_buff[s->rxbuf_start]; count = 0;
509 if (tmp8 & (1 << 7)) { /* EFF */
510 count += 2;
511 }
512 count += 3;
513 if (!(tmp8 & (1 << 6))) { /* DATA */
514 count += (tmp8 & 0x0f);
515 }
516
517 if (DEBUG_FILTER) {
518 qemu_log("[cansja]: message released from "
519 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count);
520 }
521
522 s->rxbuf_start += count;
523 s->rxbuf_start %= SJA_RCV_BUF_LEN;
524
525 s->rx_cnt -= count;
526 s->rxmsg_cnt--;
527 if (s->rxmsg_cnt == 0) {
528 s->status_pel &= ~(1 << 0);
529 s->interrupt_pel &= ~(1 << 0);
530 can_sja_update_pel_irq(s);
531 }
532 }
533 if (0x08 & val) { /* Clear data overrun */
534 s->status_pel &= ~(1 << 1);
535 s->interrupt_pel &= ~(1 << 3);
536 can_sja_update_pel_irq(s);
537 }
538 break;
539 case SJA_SR: /* Status register */
540 case SJA_IR: /* Interrupt register */
541 break; /* Do nothing */
542 case SJA_IER: /* Interrupt enable register */
543 s->interrupt_en = val;
544 break;
545 case 16: /* RX frame information addr16-28. */
546 s->status_pel |= (1 << 5); /* Set transmit status. */
547 /* fallthrough */
548 case 17 ... 28:
549 if (s->mode & 0x01) { /* Reset mode */
550 if (addr < 24) {
551 s->code_mask[addr - 16] = val;
552 }
553 } else { /* Operation mode */
554 s->tx_buff[addr - 16] = val; /* Store to TX buffer directly. */
555 }
556 break;
557 case SJA_CDR:
558 s->clock = val;
559 break;
560 }
561 } else { /* Basic Mode */
562 switch (addr) {
563 case SJA_BCAN_CTR: /* Control register, addr 0 */
564 if ((s->control & 0x01) && ((val & 0x01) == 0)) {
565 /* Go to operation mode from reset mode. */
566 s->filter[0].can_id = (s->code << 3) & (0xff << 3);
567 tmp = (~(s->mask << 3)) & (0xff << 3);
568 tmp |= QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */
569 s->filter[0].can_mask = tmp;
570 can_bus_client_set_filters(&s->bus_client, s->filter, 1);
571
572 s->rxmsg_cnt = 0;
573 s->rx_cnt = 0;
574 } else if (!(s->control & 0x01) && !(val & 0x01)) {
575 can_sja_software_reset(s);
576 }
577
578 s->control = 0x1f & val;
579 break;
580 case SJA_BCAN_CMR: /* Command register, addr 1 */
581 if (0x01 & val) { /* Send transmission request. */
582 buff2frame_bas(s->tx_buff, &frame);
583 if (DEBUG_FILTER) {
584 can_display_msg("[cansja]: Tx request " , &frame);
585 }
586
587 /*
588 * Clear transmission complete status,
589 * and Transmit Buffer Status.
590 */
591 s->status_bas &= ~(3 << 2);
592
593 /* write to the backends. */
594 can_bus_client_send(&s->bus_client, &frame, 1);
595
596 /*
597 * Set transmission complete status,
598 * and Transmit Buffer Status.
599 */
600 s->status_bas |= (3 << 2);
601
602 /* Clear transmit status. */
603 s->status_bas &= ~(1 << 5);
604 s->interrupt_bas |= 0x02;
605 can_sja_update_bas_irq(s);
606 }
607 if (0x04 & val) { /* Release Receive Buffer */
608 if (s->rxmsg_cnt <= 0) {
609 break;
610 }
611
612 tmp8 = s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN];
613 count = 2 + (tmp8 & 0x0f);
614
615 if (DEBUG_FILTER) {
616 qemu_log("[cansja]: message released from "
617 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count);
618 }
619
620 s->rxbuf_start += count;
621 s->rxbuf_start %= SJA_RCV_BUF_LEN;
622 s->rx_cnt -= count;
623 s->rxmsg_cnt--;
624
625 if (s->rxmsg_cnt == 0) {
626 s->status_bas &= ~(1 << 0);
627 s->interrupt_bas &= ~(1 << 0);
628 can_sja_update_bas_irq(s);
629 }
630 }
631 if (0x08 & val) { /* Clear data overrun */
632 s->status_bas &= ~(1 << 1);
633 s->interrupt_bas &= ~(1 << 3);
634 can_sja_update_bas_irq(s);
635 }
636 break;
637 case 4:
638 s->code = val;
639 break;
640 case 5:
641 s->mask = val;
642 break;
643 case 10:
644 s->status_bas |= (1 << 5); /* Set transmit status. */
645 /* fallthrough */
646 case 11 ... 19:
647 if ((s->control & 0x01) == 0) { /* Operation mode */
648 s->tx_buff[addr - 10] = val; /* Store to TX buffer directly. */
649 }
650 break;
651 case SJA_CDR:
652 s->clock = val;
653 break;
654 }
655 }
656 }
657
658 uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size)
659 {
660 uint64_t temp = 0;
661
662 DPRINTF("read addr 0x%02x ...\n", (unsigned int)addr);
663
664 if (addr > CAN_SJA_MEM_SIZE) {
665 return 0;
666 }
667
668 if (s->clock & 0x80) { /* PeliCAN Mode */
669 switch (addr) {
670 case SJA_MOD: /* Mode register, addr 0 */
671 temp = s->mode;
672 break;
673 case SJA_CMR: /* Command register, addr 1 */
674 temp = 0x00; /* Command register, cannot be read. */
675 break;
676 case SJA_SR: /* Status register, addr 2 */
677 temp = s->status_pel;
678 break;
679 case SJA_IR: /* Interrupt register, addr 3 */
680 temp = s->interrupt_pel;
681 s->interrupt_pel = 0;
682 if (s->rxmsg_cnt) {
683 s->interrupt_pel |= (1 << 0); /* Receive interrupt. */
684 }
685 can_sja_update_pel_irq(s);
686 break;
687 case SJA_IER: /* Interrupt enable register, addr 4 */
688 temp = s->interrupt_en;
689 break;
690 case 5: /* Reserved */
691 case 6: /* Bus timing 0, hardware related, not support now. */
692 case 7: /* Bus timing 1, hardware related, not support now. */
693 case 8: /*
694 * Output control register, hardware related,
695 * not supported for now.
696 */
697 case 9: /* Test. */
698 case 10 ... 15: /* Reserved */
699 temp = 0x00;
700 break;
701
702 case 16 ... 28:
703 if (s->mode & 0x01) { /* Reset mode */
704 if (addr < 24) {
705 temp = s->code_mask[addr - 16];
706 } else {
707 temp = 0x00;
708 }
709 } else { /* Operation mode */
710 temp = s->rx_buff[(s->rxbuf_start + addr - 16) %
711 SJA_RCV_BUF_LEN];
712 }
713 break;
714 case SJA_CDR:
715 temp = s->clock;
716 break;
717 default:
718 temp = 0xff;
719 }
720 } else { /* Basic Mode */
721 switch (addr) {
722 case SJA_BCAN_CTR: /* Control register, addr 0 */
723 temp = s->control;
724 break;
725 case SJA_BCAN_SR: /* Status register, addr 2 */
726 temp = s->status_bas;
727 break;
728 case SJA_BCAN_IR: /* Interrupt register, addr 3 */
729 temp = s->interrupt_bas;
730 s->interrupt_bas = 0;
731 if (s->rxmsg_cnt) {
732 s->interrupt_bas |= (1 << 0); /* Receive interrupt. */
733 }
734 can_sja_update_bas_irq(s);
735 break;
736 case 4:
737 temp = s->code;
738 break;
739 case 5:
740 temp = s->mask;
741 break;
742 case 20 ... 29:
743 temp = s->rx_buff[(s->rxbuf_start + addr - 20) % SJA_RCV_BUF_LEN];
744 break;
745 case 31:
746 temp = s->clock;
747 break;
748 default:
749 temp = 0xff;
750 break;
751 }
752 }
753 DPRINTF("read addr 0x%02x, %d bytes, content 0x%02lx\n",
754 (int)addr, size, (long unsigned int)temp);
755
756 return temp;
757 }
758
759 bool can_sja_can_receive(CanBusClientState *client)
760 {
761 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client);
762
763 if (s->clock & 0x80) { /* PeliCAN Mode */
764 if (s->mode & 0x01) { /* reset mode. */
765 return false;
766 }
767 } else { /* BasicCAN mode */
768 if (s->control & 0x01) {
769 return false;
770 }
771 }
772
773 return true; /* always return true, when operation mode */
774 }
775
776 ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames,
777 size_t frames_cnt)
778 {
779 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client);
780 static uint8_t rcv[SJA_MSG_MAX_LEN];
781 int i;
782 int ret = -1;
783 const qemu_can_frame *frame = frames;
784
785 if (frames_cnt <= 0) {
786 return 0;
787 }
788 if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) {
789 if (DEBUG_FILTER) {
790 can_display_msg("[cansja]: ignor fd frame ", frame);
791 }
792 return 1;
793 }
794
795 if (DEBUG_FILTER) {
796 can_display_msg("[cansja]: receive ", frame);
797 }
798
799 if (s->clock & 0x80) { /* PeliCAN Mode */
800
801 /* the CAN controller is receiving a message */
802 s->status_pel |= (1 << 4);
803
804 if (can_sja_accept_filter(s, frame) == 0) {
805 s->status_pel &= ~(1 << 4);
806 if (DEBUG_FILTER) {
807 qemu_log("[cansja]: filter rejects message\n");
808 }
809 return ret;
810 }
811
812 ret = frame2buff_pel(frame, rcv);
813 if (ret < 0) {
814 s->status_pel &= ~(1 << 4);
815 if (DEBUG_FILTER) {
816 qemu_log("[cansja]: message store failed\n");
817 }
818 return ret; /* maybe not support now. */
819 }
820
821 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */
822 s->status_pel |= (1 << 1); /* Overrun status */
823 s->interrupt_pel |= (1 << 3);
824 s->status_pel &= ~(1 << 4);
825 if (DEBUG_FILTER) {
826 qemu_log("[cansja]: receive FIFO overrun\n");
827 }
828 can_sja_update_pel_irq(s);
829 return ret;
830 }
831 s->rx_cnt += ret;
832 s->rxmsg_cnt++;
833 if (DEBUG_FILTER) {
834 qemu_log("[cansja]: message stored in receive FIFO\n");
835 }
836
837 for (i = 0; i < ret; i++) {
838 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i];
839 }
840 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */
841
842 s->status_pel |= 0x01; /* Set the Receive Buffer Status. DS-p23 */
843 s->interrupt_pel |= 0x01;
844 s->status_pel &= ~(1 << 4);
845 can_sja_update_pel_irq(s);
846 } else { /* BasicCAN mode */
847
848 /* the CAN controller is receiving a message */
849 s->status_bas |= (1 << 4);
850
851 ret = frame2buff_bas(frame, rcv);
852 if (ret < 0) {
853 s->status_bas &= ~(1 << 4);
854 if (DEBUG_FILTER) {
855 qemu_log("[cansja]: message store failed\n");
856 }
857 return ret; /* maybe not support now. */
858 }
859
860 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */
861 s->status_bas |= (1 << 1); /* Overrun status */
862 s->status_bas &= ~(1 << 4);
863 s->interrupt_bas |= (1 << 3);
864 can_sja_update_bas_irq(s);
865 if (DEBUG_FILTER) {
866 qemu_log("[cansja]: receive FIFO overrun\n");
867 }
868 return ret;
869 }
870 s->rx_cnt += ret;
871 s->rxmsg_cnt++;
872
873 if (DEBUG_FILTER) {
874 qemu_log("[cansja]: message stored\n");
875 }
876
877 for (i = 0; i < ret; i++) {
878 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i];
879 }
880 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */
881
882 s->status_bas |= 0x01; /* Set the Receive Buffer Status. DS-p15 */
883 s->status_bas &= ~(1 << 4);
884 s->interrupt_bas |= (1 << 0);
885 can_sja_update_bas_irq(s);
886 }
887 return 1;
888 }
889
890 static CanBusClientInfo can_sja_bus_client_info = {
891 .can_receive = can_sja_can_receive,
892 .receive = can_sja_receive,
893 };
894
895
896 int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus)
897 {
898 s->bus_client.info = &can_sja_bus_client_info;
899
900 if (!bus) {
901 return -EINVAL;
902 }
903
904 if (can_bus_insert_client(bus, &s->bus_client) < 0) {
905 return -1;
906 }
907
908 return 0;
909 }
910
911 void can_sja_disconnect(CanSJA1000State *s)
912 {
913 can_bus_remove_client(&s->bus_client);
914 }
915
916 int can_sja_init(CanSJA1000State *s, qemu_irq irq)
917 {
918 s->irq = irq;
919
920 qemu_irq_lower(s->irq);
921
922 can_sja_hardware_reset(s);
923
924 return 0;
925 }
926
927 const VMStateDescription vmstate_qemu_can_filter = {
928 .name = "qemu_can_filter",
929 .version_id = 1,
930 .minimum_version_id = 1,
931 .fields = (const VMStateField[]) {
932 VMSTATE_UINT32(can_id, qemu_can_filter),
933 VMSTATE_UINT32(can_mask, qemu_can_filter),
934 VMSTATE_END_OF_LIST()
935 }
936 };
937
938 static int can_sja_post_load(void *opaque, int version_id)
939 {
940 CanSJA1000State *s = opaque;
941 if (s->clock & 0x80) { /* PeliCAN Mode */
942 can_sja_update_pel_irq(s);
943 } else {
944 can_sja_update_bas_irq(s);
945 }
946 return 0;
947 }
948
949 /* VMState is needed for live migration of QEMU images */
950 const VMStateDescription vmstate_can_sja = {
951 .name = "can_sja",
952 .version_id = 1,
953 .minimum_version_id = 1,
954 .post_load = can_sja_post_load,
955 .fields = (const VMStateField[]) {
956 VMSTATE_UINT8(mode, CanSJA1000State),
957
958 VMSTATE_UINT8(status_pel, CanSJA1000State),
959 VMSTATE_UINT8(interrupt_pel, CanSJA1000State),
960 VMSTATE_UINT8(interrupt_en, CanSJA1000State),
961 VMSTATE_UINT8(rxmsg_cnt, CanSJA1000State),
962 VMSTATE_UINT8(rxbuf_start, CanSJA1000State),
963 VMSTATE_UINT8(clock, CanSJA1000State),
964
965 VMSTATE_BUFFER(code_mask, CanSJA1000State),
966 VMSTATE_BUFFER(tx_buff, CanSJA1000State),
967
968 VMSTATE_BUFFER(rx_buff, CanSJA1000State),
969
970 VMSTATE_UINT32(rx_ptr, CanSJA1000State),
971 VMSTATE_UINT32(rx_cnt, CanSJA1000State),
972
973 VMSTATE_UINT8(control, CanSJA1000State),
974
975 VMSTATE_UINT8(status_bas, CanSJA1000State),
976 VMSTATE_UINT8(interrupt_bas, CanSJA1000State),
977 VMSTATE_UINT8(code, CanSJA1000State),
978 VMSTATE_UINT8(mask, CanSJA1000State),
979
980 VMSTATE_STRUCT_ARRAY(filter, CanSJA1000State, 4, 0,
981 vmstate_qemu_can_filter, qemu_can_filter),
982
983
984 VMSTATE_END_OF_LIST()
985 }
986 };