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1 /*
2 * CTU CAN FD device emulation
3 * http://canbus.pages.fel.cvut.cz/
4 *
5 * Copyright (c) 2019 Jan Charvat (jancharvat.charvat@gmail.com)
6 *
7 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by
8 * Jin Yang and Pavel Pisa
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28 #ifndef HW_CAN_CTUCAN_CORE_H
29 #define HW_CAN_CTUCAN_CORE_H
30
31 #include "exec/hwaddr.h"
32 #include "net/can_emu.h"
33
34 #if !HOST_BIG_ENDIAN
35 #define __LITTLE_ENDIAN_BITFIELD 1
36 #endif
37
38 #include "ctu_can_fd_frame.h"
39 #include "ctu_can_fd_regs.h"
40
41 #define CTUCAN_CORE_MEM_SIZE 0x500
42
43 /* The max size for a message in FIFO */
44 #define CTUCAN_MSG_MAX_LEN (CTU_CAN_FD_DATA_1_4_W + 64)
45 /* The receive buffer size. */
46 #define CTUCAN_RCV_BUF_LEN (1024 * 8)
47
48
49 /* The max size for a message buffer */
50 #define CTUCAN_CORE_MSG_MAX_LEN 0x50
51 /* The receive buffer size. */
52 #define CTUCAN_CORE_RCV_BUF_LEN 0x1000
53
54 #define CTUCAN_CORE_TXBUF_NUM 4
55
56 typedef struct CtuCanCoreMsgBuffer {
57 uint8_t data[CTUCAN_CORE_MSG_MAX_LEN];
58 } CtuCanCoreMsgBuffer;
59
60 typedef struct CtuCanCoreState {
61 union ctu_can_fd_mode_settings mode_settings;
62 union ctu_can_fd_status status;
63 union ctu_can_fd_int_stat int_stat;
64 union ctu_can_fd_int_ena_set int_ena;
65 union ctu_can_fd_int_mask_set int_mask;
66 union ctu_can_fd_btr brt;
67 union ctu_can_fd_btr_fd brt_fd;
68 union ctu_can_fd_ewl_erp_fault_state ewl_erp_fault_state;
69 union ctu_can_fd_rec_tec rec_tec;
70 union ctu_can_fd_err_norm_err_fd err_norm_err_fd;
71 union ctu_can_fd_ctr_pres ctr_pres;
72 union ctu_can_fd_filter_a_mask filter_a_mask;
73 union ctu_can_fd_filter_a_val filter_a_val;
74 union ctu_can_fd_filter_b_mask filter_b_mask;
75 union ctu_can_fd_filter_b_val filter_b_val;
76 union ctu_can_fd_filter_c_mask filter_c_mask;
77 union ctu_can_fd_filter_c_val filter_c_val;
78 union ctu_can_fd_filter_ran_low filter_ran_low;
79 union ctu_can_fd_filter_ran_high filter_ran_high;
80 union ctu_can_fd_filter_control_filter_status filter_control_filter_status;
81 union ctu_can_fd_rx_mem_info rx_mem_info;
82 union ctu_can_fd_rx_pointers rx_pointers;
83 union ctu_can_fd_rx_status_rx_settings rx_status_rx_settings;
84 union ctu_can_fd_tx_status tx_status;
85 union ctu_can_fd_tx_priority tx_priority;
86 union ctu_can_fd_err_capt_alc err_capt_alc;
87 union ctu_can_fd_trv_delay_ssp_cfg trv_delay_ssp_cfg;
88 union ctu_can_fd_rx_fr_ctr rx_fr_ctr;
89 union ctu_can_fd_tx_fr_ctr tx_fr_ctr;
90 union ctu_can_fd_debug_register debug_register;
91 union ctu_can_fd_yolo_reg yolo_reg;
92 union ctu_can_fd_timestamp_low timestamp_low;
93 union ctu_can_fd_timestamp_high timestamp_high;
94
95 CtuCanCoreMsgBuffer tx_buffer[CTUCAN_CORE_TXBUF_NUM];
96
97 uint8_t rx_buff[CTUCAN_RCV_BUF_LEN]; /* 32~95 .. 64bytes Rx FIFO */
98 uint32_t rx_tail_pos; /* Count by bytes. */
99 uint32_t rx_cnt; /* Count by bytes. */
100 uint32_t rx_frame_rem;
101
102 qemu_irq irq;
103 CanBusClientState bus_client;
104 } CtuCanCoreState;
105
106 void ctucan_hardware_reset(CtuCanCoreState *s);
107
108 void ctucan_mem_write(CtuCanCoreState *s, hwaddr addr, uint64_t val,
109 unsigned size);
110
111 uint64_t ctucan_mem_read(CtuCanCoreState *s, hwaddr addr, unsigned size);
112
113 int ctucan_connect_to_bus(CtuCanCoreState *s, CanBusState *bus);
114
115 void ctucan_disconnect(CtuCanCoreState *s);
116
117 int ctucan_init(CtuCanCoreState *s, qemu_irq irq);
118
119 bool ctucan_can_receive(CanBusClientState *client);
120
121 ssize_t ctucan_receive(CanBusClientState *client,
122 const qemu_can_frame *frames, size_t frames_cnt);
123
124 extern const VMStateDescription vmstate_ctucan;
125
126 #endif