| 1 | /* |
| 2 | * Field bitmasks and register structs definitions for FlexCAN |
| 3 | * |
| 4 | * This implementation is based on the following datasheet: |
| 5 | * i.MX 6Dual/6Quad Applications Processor Reference Manual |
| 6 | * Document Number: IMX6DQRM, Rev. 6, 05/2020 |
| 7 | * |
| 8 | * Copyright (c) 2025 Matyas Bobek <matyas.bobek@gmail.com> |
| 9 | * |
| 10 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 11 | */ |
| 12 | #include "qemu/bitops.h" |
| 13 | |
| 14 | #ifndef HW_CAN_FLEXCAN_REGS_H |
| 15 | #define HW_CAN_FLEXCAN_REGS_H |
| 16 | |
| 17 | #define FLEXCAN_GENMASK(h, l) (((~(uint32_t)0) >> (31 - (h) + (l))) << (l)) |
| 18 | |
| 19 | /** |
| 20 | * The following macros were originally written for the Linux kernel by: |
| 21 | * Andrey Volkov <andrey@volkov.fr> |
| 22 | * Sascha Hauer <s.hauer@pengutronix.de> |
| 23 | * Marc Kleine-Budde <mkl@pengutronix.de> |
| 24 | * David Jander <david@protonic.nl> |
| 25 | * and they have agreed to license them under GPL-2.0-or-later. |
| 26 | */ |
| 27 | |
| 28 | /* FLEXCAN module configuration register (CANMCR) bits */ |
| 29 | #define FLEXCAN_MCR_MDIS BIT(31) |
| 30 | #define FLEXCAN_MCR_FRZ BIT(30) |
| 31 | #define FLEXCAN_MCR_FEN BIT(29) |
| 32 | #define FLEXCAN_MCR_HALT BIT(28) |
| 33 | #define FLEXCAN_MCR_NOT_RDY BIT(27) |
| 34 | #define FLEXCAN_MCR_WAK_MSK BIT(26) |
| 35 | #define FLEXCAN_MCR_SOFTRST BIT(25) |
| 36 | #define FLEXCAN_MCR_FRZ_ACK BIT(24) |
| 37 | #define FLEXCAN_MCR_SUPV BIT(23) |
| 38 | #define FLEXCAN_MCR_SLF_WAK BIT(22) |
| 39 | #define FLEXCAN_MCR_WRN_EN BIT(21) |
| 40 | #define FLEXCAN_MCR_LPM_ACK BIT(20) |
| 41 | #define FLEXCAN_MCR_WAK_SRC BIT(19) |
| 42 | #define FLEXCAN_MCR_DOZE BIT(18) |
| 43 | #define FLEXCAN_MCR_SRX_DIS BIT(17) |
| 44 | #define FLEXCAN_MCR_IRMQ BIT(16) |
| 45 | #define FLEXCAN_MCR_LPRIO_EN BIT(13) |
| 46 | #define FLEXCAN_MCR_AEN BIT(12) |
| 47 | #define FLEXCAN_MCR_FDEN BIT(11) |
| 48 | #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) |
| 49 | #define FLEXCAN_MCR_IDAM_A (0x0 << 8) |
| 50 | #define FLEXCAN_MCR_IDAM_B (0x1 << 8) |
| 51 | #define FLEXCAN_MCR_IDAM_C (0x2 << 8) |
| 52 | #define FLEXCAN_MCR_IDAM_D (0x3 << 8) |
| 53 | #define FLEXCAN_MCR_IDAM_MASK (0x3 << 8) |
| 54 | |
| 55 | /* FLEXCAN control register (CANCTRL) bits */ |
| 56 | #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24) |
| 57 | #define FLEXCAN_CTRL_PRESDIV_MASK FLEXCAN_CTRL_PRESDIV(UINT32_MAX) |
| 58 | #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) |
| 59 | #define FLEXCAN_CTRL_RJW_MASK FLEXCAN_CTRL_RJW(UINT32_MAX) |
| 60 | #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) |
| 61 | #define FLEXCAN_CTRL_PSEG1_MASK FLEXCAN_CTRL_PSEG1(UINT32_MAX) |
| 62 | #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) |
| 63 | #define FLEXCAN_CTRL_PSEG2_MASK FLEXCAN_CTRL_PSEG2(UINT32_MAX) |
| 64 | #define FLEXCAN_CTRL_BOFF_MSK BIT(15) |
| 65 | #define FLEXCAN_CTRL_ERR_MSK BIT(14) |
| 66 | #define FLEXCAN_CTRL_CLK_SRC BIT(13) |
| 67 | #define FLEXCAN_CTRL_LPB BIT(12) |
| 68 | #define FLEXCAN_CTRL_TWRN_MSK BIT(11) |
| 69 | #define FLEXCAN_CTRL_RWRN_MSK BIT(10) |
| 70 | #define FLEXCAN_CTRL_SMP BIT(7) |
| 71 | #define FLEXCAN_CTRL_BOFF_REC BIT(6) |
| 72 | #define FLEXCAN_CTRL_TSYN BIT(5) |
| 73 | #define FLEXCAN_CTRL_LBUF BIT(4) |
| 74 | #define FLEXCAN_CTRL_LOM BIT(3) |
| 75 | #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) |
| 76 | #define FLEXCAN_CTRL_PROPSEG_MASK FLEXCAN_CTRL_PROPSEG(UINT32_MAX) |
| 77 | #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) |
| 78 | #define FLEXCAN_CTRL_ERR_STATE \ |
| 79 | (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ |
| 80 | FLEXCAN_CTRL_BOFF_MSK) |
| 81 | #define FLEXCAN_CTRL_ERR_ALL \ |
| 82 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) |
| 83 | |
| 84 | /* FLEXCAN control register 2 (CTRL2) bits */ |
| 85 | #define FLEXCAN_CTRL2_ECRWRE BIT(29) |
| 86 | #define FLEXCAN_CTRL2_WRMFRZ BIT(28) |
| 87 | #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) |
| 88 | #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) |
| 89 | #define FLEXCAN_CTRL2_MRP BIT(18) |
| 90 | #define FLEXCAN_CTRL2_RRS BIT(17) |
| 91 | #define FLEXCAN_CTRL2_EACEN BIT(16) |
| 92 | #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12) |
| 93 | |
| 94 | /* FLEXCAN memory error control register (MECR) bits */ |
| 95 | #define FLEXCAN_MECR_ECRWRDIS BIT(31) |
| 96 | #define FLEXCAN_MECR_HANCEI_MSK BIT(19) |
| 97 | #define FLEXCAN_MECR_FANCEI_MSK BIT(18) |
| 98 | #define FLEXCAN_MECR_CEI_MSK BIT(16) |
| 99 | #define FLEXCAN_MECR_HAERRIE BIT(15) |
| 100 | #define FLEXCAN_MECR_FAERRIE BIT(14) |
| 101 | #define FLEXCAN_MECR_EXTERRIE BIT(13) |
| 102 | #define FLEXCAN_MECR_RERRDIS BIT(9) |
| 103 | #define FLEXCAN_MECR_ECCDIS BIT(8) |
| 104 | #define FLEXCAN_MECR_NCEFAFRZ BIT(7) |
| 105 | |
| 106 | /* FLEXCAN error and status register (ESR) bits */ |
| 107 | #define FLEXCAN_ESR_SYNCH BIT(18) |
| 108 | #define FLEXCAN_ESR_TWRN_INT BIT(17) |
| 109 | #define FLEXCAN_ESR_RWRN_INT BIT(16) |
| 110 | #define FLEXCAN_ESR_BIT1_ERR BIT(15) |
| 111 | #define FLEXCAN_ESR_BIT0_ERR BIT(14) |
| 112 | #define FLEXCAN_ESR_ACK_ERR BIT(13) |
| 113 | #define FLEXCAN_ESR_CRC_ERR BIT(12) |
| 114 | #define FLEXCAN_ESR_FRM_ERR BIT(11) |
| 115 | #define FLEXCAN_ESR_STF_ERR BIT(10) |
| 116 | #define FLEXCAN_ESR_TX_WRN BIT(9) |
| 117 | #define FLEXCAN_ESR_RX_WRN BIT(8) |
| 118 | #define FLEXCAN_ESR_IDLE BIT(7) |
| 119 | #define FLEXCAN_ESR_BOFF_INT BIT(2) |
| 120 | #define FLEXCAN_ESR_ERR_INT BIT(1) |
| 121 | #define FLEXCAN_ESR_WAK_INT BIT(0) |
| 122 | |
| 123 | /* FLEXCAN Bit Timing register (CBT) bits */ |
| 124 | #define FLEXCAN_CBT_BTF BIT(31) |
| 125 | #define FLEXCAN_CBT_EPRESDIV_MASK FLEXCAN_GENMASK(30, 21) |
| 126 | #define FLEXCAN_CBT_ERJW_MASK FLEXCAN_GENMASK(20, 16) |
| 127 | #define FLEXCAN_CBT_EPROPSEG_MASK FLEXCAN_GENMASK(15, 10) |
| 128 | #define FLEXCAN_CBT_EPSEG1_MASK FLEXCAN_GENMASK(9, 5) |
| 129 | #define FLEXCAN_CBT_EPSEG2_MASK FLEXCAN_GENMASK(4, 0) |
| 130 | |
| 131 | /* FLEXCAN FD control register (FDCTRL) bits */ |
| 132 | #define FLEXCAN_FDCTRL_FDRATE BIT(31) |
| 133 | #define FLEXCAN_FDCTRL_MBDSR1 FLEXCAN_GENMASK(20, 19) |
| 134 | #define FLEXCAN_FDCTRL_MBDSR0 FLEXCAN_GENMASK(17, 16) |
| 135 | #define FLEXCAN_FDCTRL_MBDSR_8 0x0 |
| 136 | #define FLEXCAN_FDCTRL_MBDSR_12 0x1 |
| 137 | #define FLEXCAN_FDCTRL_MBDSR_32 0x2 |
| 138 | #define FLEXCAN_FDCTRL_MBDSR_64 0x3 |
| 139 | #define FLEXCAN_FDCTRL_TDCEN BIT(15) |
| 140 | #define FLEXCAN_FDCTRL_TDCFAIL BIT(14) |
| 141 | #define FLEXCAN_FDCTRL_TDCOFF FLEXCAN_GENMASK(12, 8) |
| 142 | #define FLEXCAN_FDCTRL_TDCVAL FLEXCAN_GENMASK(5, 0) |
| 143 | |
| 144 | /* FLEXCAN FD Bit Timing register (FDCBT) bits */ |
| 145 | #define FLEXCAN_FDCBT_FPRESDIV_MASK FLEXCAN_GENMASK(29, 20) |
| 146 | #define FLEXCAN_FDCBT_FRJW_MASK FLEXCAN_GENMASK(18, 16) |
| 147 | #define FLEXCAN_FDCBT_FPROPSEG_MASK FLEXCAN_GENMASK(14, 10) |
| 148 | #define FLEXCAN_FDCBT_FPSEG1_MASK FLEXCAN_GENMASK(7, 5) |
| 149 | #define FLEXCAN_FDCBT_FPSEG2_MASK FLEXCAN_GENMASK(2, 0) |
| 150 | |
| 151 | /* FLEXCAN CRC Register (CRCR) bits */ |
| 152 | #define FLEXCAN_CRCR_MBCRC_MASK FLEXCAN_GENMASK(22, 16) |
| 153 | #define FLEXCAN_CRCR_MBCRC(x) (((x) & FLEXCAN_CRCR_MBCRC_MASK) << 16) |
| 154 | #define FLEXCAN_CRCR_TXCRC_MASK FLEXCAN_GENMASK(14, 0) |
| 155 | #define FLEXCAN_CRCR_TXCRC(x) ((x) & FLEXCAN_CRCR_TXCRC_MASK) |
| 156 | |
| 157 | /* FLEXCAN interrupt flag register (IFLAG) bits */ |
| 158 | /* Errata ERR005829 step7: Reserve first valid MB */ |
| 159 | #define I_FIFO_OVERFLOW 7 |
| 160 | #define I_FIFO_WARN 6 |
| 161 | #define I_FIFO_AVAILABLE 5 |
| 162 | |
| 163 | #define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8 |
| 164 | #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0 |
| 165 | #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1) |
| 166 | #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x) |
| 167 | #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(I_FIFO_OVERFLOW) |
| 168 | #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(I_FIFO_WARN) |
| 169 | #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(I_FIFO_AVAILABLE) |
| 170 | |
| 171 | /* FLEXCAN message buffers */ |
| 172 | #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24) |
| 173 | #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) |
| 174 | #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) |
| 175 | #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) |
| 176 | #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24) |
| 177 | #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) |
| 178 | |
| 179 | #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) |
| 180 | #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) |
| 181 | #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) |
| 182 | #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) |
| 183 | |
| 184 | #define FLEXCAN_MB_CODE(x) (((x) & 0xF) << 24) |
| 185 | #define FLEXCAN_MB_CODE_MASK FLEXCAN_MB_CODE(UINT32_MAX) |
| 186 | |
| 187 | #define FLEXCAN_MB_CNT_EDL BIT(31) |
| 188 | #define FLEXCAN_MB_CNT_BRS BIT(30) |
| 189 | #define FLEXCAN_MB_CNT_ESI BIT(29) |
| 190 | #define FLEXCAN_MB_CNT_SRR BIT(22) |
| 191 | #define FLEXCAN_MB_CNT_IDE BIT(21) |
| 192 | #define FLEXCAN_MB_CNT_RTR BIT(20) |
| 193 | #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xF) << 16) |
| 194 | #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xFFFF) |
| 195 | #define FLEXCAN_MB_CNT_TIMESTAMP_MASK FLEXCAN_MB_CNT_TIMESTAMP(UINT32_MAX) |
| 196 | |
| 197 | #endif |